Nonvolatile memory fabrication methods in which a dielectric layer underlying a floating gate layer is spaced from an edge of an isolation trench and/or an edge of the floating gate layer

The present invention relates to integrated circuits, and more particularly to nonvolatile memories.

FIGS. 1–4 illustrate a nonvolatile memory fabrication process described in U.S. Pat. No. 6,555,427 issued Apr. 29, 2003 to Shimizu et al. These figures show vertical cross sections of the memory structures. A P-well is formed in a semiconductor substrate 110 . Tunnel dielectric 120 is formed on substrate 120 on the P-well. First conductive layer 130 . 1 is formed on dielectric 120 to provide portions of floating gates for the memory cells. A masking layer 140 is formed on layer 130 . 1 . Layers 140 , 130 . 1 , 120 and substrate 110 are etched to form isolation trenches 150 . The sidewalls of trenches 150 and the layer 130 . 1 are oxidized, and dielectric 210 is deposited over the structure. Dielectric 210 is subjected to an etch or chemical mechanical polishing (CMP) to expose the top surface of masking layer 140 .

Layer 140 is removed. An isotropic etch of dielectric 210 laterally recesses the dielectric sidewalls away from the floating gate portions 130 . 1 , widening the empty areas above these floating gate portions.

Second conductive layer 130 . 2 ( FIG. 3 ) is deposited over the structure to provide second portions of the floating gates 130 . Layer 130 . 2 is etched or polished to expose the dielectric 210 . A planar top surface is provided. Then dielectric 210 is etched down to expose sidewalls of layer 130 . 2 .

Inter-gate dielectric 410 ( FIG. 4 ) and control gate layer 420 are formed over the structure to finish the memory cell fabrication.

The memory cells are programmed by injecting a negative charge (electrons) into their floating gates 130 . The cells are erased by removing the negative charge from the floating gates. The cells are read by sensing the charge on the floating gates. These operations require a voltage V FG.S to be induced between the floating gate (FG) 130 and a region of substrate 110 . The voltage V FG.S is induced by establishing a voltage V CG.S between the control gate (CG) 420 and the substrate region, as the control gate is capacitively coupled to the floating gate. In order to reduce the maximum voltage V CG.S needed to induce a given voltage V FG.S , one has to increase the “gate coupling ratio” C CG.FG /C FG.S , where C CG.FG is the capacitance between control gate 420 and floating gate 130 , and C FG.S is the capacitance between the floating gate 130 and the substrate region. The isotropic etch of dielectric 210 ( FIG. 2 ) serves to increase C CG.FG due to the increased width of the top floating gate portions 130 . 2 ( FIG. 3 ). The etch-back of dielectric 210 ( FIG. 3 ) to expose the sidewalls of layer 130 . 2 further increases the capacitance C CG.FG by increasing the capacitive coupling between the sidewalls of layer 130 . 2 and the control gate 420 .

This section summarizes some features of the invention. Other features are described in the subsequent sections. The invention is defined by the appended claims which are incorporated into this section by reference.

The inventor has observed that the isotropic etch of dielectric 210 ( FIG. 2 ) may increase the sub-threshold current leakage near the trench edges 150 E ( FIG. 4 ). Indeed, the dielectric is etched both laterally and vertically, and the etch may expose the substrate 110 and cause a short between the floating gate layer 130 . 2 and the substrate. Even if the short is avoided, the electric field between the floating gate 130 and substrate 110 will be increased at the edges 150 E, thus increasing the leakage current in the off state of the floating gate transistor. This condition can be somewhat alleviated by increasing the thickness of layer 130 . 1 , but this is undesirable because of the increased aspect ratio of the holes into which the dielectric 210 is deposited (the holes formed by trenches 150 and the layers 120 , 130 . 1 , 140 ).

In some embodiments of the present invention, tunnel dielectric 120 is etched laterally after the formation of trenches 150 before the deposition of dielectric 210 . This etch pulls back the dielectric 120 away from the trench edges 150 E. When the structure is later oxidized, the edges 150 E become rounded. Therefore, the electric field will be reduced at the edges. In addition, the bottom edges of layer 130 . 1 will be oxidized, providing an additional oxide thickness between the layer 130 . 1 and the trench edges. This additional oxide serves both to reduce the electric field at the trench edges 150 E and to increase the data retention time.

In some embodiments, the lateral etch of dielectric 120 is also performed in the peripheral area to round the trench edges in the periphery and thus reduce the electric field at the trench corners and the leakage current. This may be especially desirable for high voltage transistors. In some embodiments, the lateral etch of dielectric 120 is performed in the high voltage peripheral area but not in the low voltage peripheral area. In other embodiments, dielectric 120 is etched both in the high voltage and the low voltage peripheral areas.

The invention is not limited to the features described above. In some embodiments, the dielectric 120 is removed at the edge of the trench but not at the edge of layer 130 . 1 (the two edges are not always vertically aligned), or the dielectric 120 may be removed at the edge of layer 130 . 1 but not at the edge of the trench. The invention is applicable to many memory architectures, such as described in U.S. Pat. No. 6,355,524 issued Mar. 12, 2002 to Tuan et al., U.S. Pat. No. 6,417,047 issued Jul. 9, 2002 to Isobe, the aforementioned U.S. Pat. No. 6,555,427, and other architectures, known or to be invented. Other features and advantages of the invention are described below. The invention is defined by the appended claims.

FIGS. 1–4 are cross section illustrations of memory structures in the process of fabrication according to prior art.

FIG. 5A is a top view of a memory structure fabricated according to one embodiment of the present invention.

FIGS. 5B , 5 C, 6 – 8 , 9 A, 9 B, 10 , 11 , 12 A, 12 B, 13 – 15 , 16 , 17 A are cross section illustrations of memory structures in the process of fabrication according to embodiments of the present invention.

FIG. 17B is a top view of a memory structure fabricated according to one embodiment of the present invention.

The embodiments described in this section illustrate but do not limit the invention. The invention is not limited to particular materials, process steps, or dimensions. The invention is defined by the appended claims.

One embodiment of the present invention will now be illustrated on the example of a NOR type flash memory array shown in FIGS. 5A (top view), 5 B (vertical cross section marked B—B in FIG. 5A ), 5 C (vertical cross section marked C—C in FIG. 5A ). Wordlines (control gate lines) 420 run in the X direction (row direction) through the array. Bitlines 510 run in the Y direction (column direction) over active areas 430 . Each memory cell includes N+ doped source/drain regions 520 S, 520 B ( FIGS. 5A , 5 C) formed in active area 430 in substrate 110 on different sides of the floating gate 120 . The cell also includes a P type channel region underlying the floating gate and extending between the source/drain regions 520 S, 520 B in the Y direction. Each region 520 S, 520 B is shared by two adjacent cells in the column (except possibly the first and last cells of the column, or the first and last cells of a block of cells in the column). “Bitline” regions 520 B in each column are connected to a bitline 510 via plugs 524 ( FIG. 5C ) formed in contact openings 530 etched in dielectric 534 . “Source line” regions 520 S in each row are part of a source line 520 S formed as an N+ type region of substrate 110 and running through the array in the X direction. Each isolation trench 150 passes in the column direction under two wordlines 420 and terminates at source lines 520 S. This architecture is exemplary and not limiting.

FIGS. 6–15 show vertical cross sections of intermediate structures during the memory fabrication in the memory array and peripheral areas. The array cross sections are along the line B—B ( FIG. 5A ). In this example, substrate 110 is monocrystalline silicon. The memory is fabricated in and over a P-type well in substrate 110 . Tunnel dielectric 120 (e.g. silicon dioxide) is thermally grown on the substrate to a thickness of 7˜10 nm (7 to 10 nm). The materials and dimensions are exemplary and not limiting. The dimensions given below are believed to be suitable for a minimal photolithographic line width of 0.18 μm unless noted otherwise. (No representation is made that experimentation has been conducted and the dimensions were found suitable. Also, as known in the art, the dimensions may have to be adjusted for a particular fabrication technology.) Polysilicon 130 . 1 is deposited on oxide 120 to an exemplary thickness of 500˜900 Å, and is doped during or after deposition. Silicon nitride 140 is deposited on polysilicon 120 to an exemplary thickness of 900˜2000 Å. A photoresist layer (not shown) is deposited on nitride 140 and patterned to define the trenches 150 . Nitride 140 , polysilicon 130 . 1 , oxide 120 and substrate 110 are etched anisotropically to form the trenches. Active areas 430 (substrate areas not occupied by the trenches) become also defined as a result. If desired, before the etch of oxide 120 , the nitride 140 and/or polysilicon 130 . 1 can be etched laterally to reduce the floating gate dimensions.

In some embodiments, isolation trenches are also created in the peripheral area for peripheral circuitry (i.e. address and data buffers, sense amplifiers, address decoders, voltage generators, clock generators, and possibly other circuitry needed to access the memory). The peripheral trenches can be formed simultaneously with the array trenches or in separate steps (to provide a different trench depth, for example). Thus in some embodiments, FIG. 6 represents both the array and the peripheral area.

As shown in FIG. 7 , tunnel oxide 120 is laterally etched under the polysilicon 130 . 1 to pull the oxide 120 away from trench edges 150 E and from bottom edges 130 E of polysilicon 130 . 1 . In some 0.18 μm line width embodiments, the trench width Wt is 0.26 μm at the top of substrate 110 , the active area width Waa is 0.22 μm at the top of substrate 110 , and the oxide 120 is pulled back by a distance Dx=100 Å from trench edges 150 E and polysilicon edges 130 E. The trench depth Ht=0.2 μm (measured from the top surface of substrate 120 ). In one 0.12 μm line width embodiment, Wt=0.18 μm, Waa=0.14 μm, Dx=50 Å, Ht=0.16 μm. At the conclusion of the etch, the horizontal bottom surface of polysilicon features 130 . 1 overhangs the edges of oxide 120 . Edges 130 E of the horizontal bottom surface of features 130 . 1 overlie the trench edges 150 E. This geometry and dimensions are exemplary and not limiting. For example, the overhanging bottom surface of features 130 . 1 is not horizontal in some embodiments.

The oxide etch can be a wet etch (isotropic) selective to silicon, e.g. a buffered oxide etch or an HF etch.

In some embodiments, the peripheral area is masked during this etch. In other embodiments, the periphery is exposed for the etch, so FIG. 7 also represents the periphery. In some embodiments, the periphery is masked except for a high voltage area. The high voltage area is an area for the transistors generating super high voltages needed for programming and erasing the memory. The super high voltages have higher magnitudes than the voltages needed for reading the memory.

If photoresist was used to mask any part of the wafer, the photoresist is removed. The structure is oxidized (see FIG. 8 ) to grow a silicon dioxide layer 210 . 1 on the exposed surfaces of substrate 110 and polysilicon 130 . 1 . Exemplary oxidation processes include RTO (rapid thermal oxidation) and oxidation in an oven. In one embodiment, the oxidation is performed in a dry atmosphere at 900˜1080° C. to grow 100˜150 Å of silicon dioxide 210 . 1 on substrate 120 . The oxide thickness on polysilicon 130 . 1 may be larger and will depend on the polysilicon doping type and dopant concentration. In some embodiments, the oxide thickness on the polysilicon sidewalls is 200˜300 Å. The oxidation rounds the trench edges 150 E and the polysilicon bottom edges 130 E. If these edges were sharp, they become rounded. If the edges were already rounded, they become more rounded. The rounded profile of trench edges 150 E will reduce the electric field at these edges.

The oxidation step is also performed in the periphery.

Dielectric 210 . 2 ( FIG. 9A ) is formed over the structure to fill the trenches, and is processed by CMP and/or etch-back to expose the nitride 410 and provide a planar top surface.

Optionally, the array is masked with photoresist (not shown), and the oxide 210 . 2 , 210 . 1 is etched down in the periphery. See FIG. 9B , showing a high voltage peripheral area 910 and a low voltage peripheral area 920 . (In this embodiment, the lateral etch of oxide 120 of FIG. 7 was performed both in area 910 and in area 920 .) The etch of oxide 210 . 1 , 210 . 2 will make it easier to pattern the peripheral transistor gates.

The resist masking the array is removed. Nitride 140 is removed in the array and the periphery (by a wet etch, for example). See FIG. 10 . Then the periphery is masked with photoresist (not shown), and portions of oxide layers 210 . 1 , 210 . 2 are removed in the array area adjacent to sidewalls of polysilicon features 130 . 1 (see FIG. 11 ) to form pocket regions 1110 at the sidewalls of the polysilicon features. The sidewalls of polysilicon 130 . 1 are exposed in these pockets. The pockets can be formed by an isotropic wet etch of oxide 210 . 1 , 210 . 2 without masking any part of the array area. The lateral component of the etch causes the sidewalls of oxide 210 . 2 to be laterally recessed in the direction away from the adjacent polysilicon features 130 . 1 and active areas 430 . In some embodiments, the top sidewall portions 210 T of oxide 210 . 2 become positioned over trenches 130 , while the lower sidewall portions of oxide 210 . 2 continue to overlap the active areas. In one embodiment, the isotropic etch laterally recesses the sidewall by an amount Ls in the range of 0.03 μm to 0.05 μm. The depth Ds of each pocket 1110 (measured from the top surface of polysilicon 130 . 1 ) is equal to Ls if the etch is isotropic. The etch also lowers the top surface of oxide 210 . 2 . An anisotropic etch can also be used, to provide a Ds value different from Ls if desired.

In FIG. 11 , the top surface of oxide 210 . 2 is above the top surface of polysilicon 130 . 1 after the oxide etch, but this is not necessary. The top surface of oxide 210 . 2 may be even with, or below, the top surface of polysilicon 130 . 1 .

The photoresist is removed from the periphery. Polysilicon layer 130 . 2 ( FIG. 12A , memory array, and FIG. 12B , periphery) is deposited on the structure, and is doped during or after the deposition to the same conductivity type as the layer 130 . 1 . Layer 130 . 2 will provide portions of the floating gates. Layer 130 . 2 extends into and fills the pockets 1110 (the regions from which the oxide 210 . 1 , 210 . 2 was removed by the oxide etch of FIG. 11 ). An exemplary polysilicon deposition process is conformal low pressure chemical vapor deposition (LPCVD). The thickness of layer 130 . 2 (at least 2000 Å in some embodiments) is chosen to provide a planar top surface. The planar top surface is not necessary however.

Layer 130 . 2 is subjected to CMP and/or an etch to remove the polysilicon 130 . 2 from over the top horizontal surfaces 210 H of oxide features 210 . 2 and thus to isolate the floating gates of each column from the adjacent columns. Each floating gate will include the adjacent portions of layers 130 . 1 , 130 . 2 that contact each other. In some embodiments, if the top surface of polysilicon 130 . 2 is not planar before the etch, it is planarized by depositing an auxiliary layer (e.g. photoresist) having a planar top surface and then etching the auxiliary layer and the polysilicon at equal etch rates. The top surface of layer 130 . 2 may be above, below, or even with the horizontal top surface 210 H of oxide 210 . 2 . In some embodiments, before the CMP, the periphery is masked with photoresist and the polysilicon is etched in the array area only; then the resist is removed and the CMP is conducted. This sequence aims to ensure that the polysilicon 130 . 2 is not polished away in the periphery by the CMP step. In some embodiments, polysilicon 130 . 2 is removed from the periphery during the CMP.

Pockets 1110 ( FIG. 12A ) cause the layer 130 . 2 to reach farther down towards the trench edges 150 E and undesirably increase the electric field E at the trench edges. The rounded profile obtained at the trench edges during the formation of oxide 210 . 1 ( FIG. 8 ) counteracts this disadvantage by reducing the electric field. This field is also reduced due to the oxidation of the bottom edges 130 E of polysilicon 130 . 1 because the polysilicon oxidation increases the distance between the floating gates 130 and the trench edges. The oxidation of silicon edges 150 E, 130 E is facilitated by the lateral etch of oxide 120 ( FIG. 7 ) due to a greater silicon area becoming exposed by the lateral oxide etch.

An optional etch of oxide 210 . 2 ( FIG. 13 ) lowers the top surface of oxide 210 in the array area to a level below the top surface of polysilicon 130 . 2 to increase the capacitive coupling between the floating gates 130 . 1 , 130 . 2 and the control gates 420 ( FIG. 5B ). See U.S. Pat. No. 6,355,524 issued Mar. 12, 2002 to Tuan et al. and incorporated herein by reference.

The memory fabrication can be completed using conventional techniques. In some embodiments, insulating layer 410 ( FIGS. 5B , 5 C) is formed over the structure. Layer 410 can be a sandwich of silicon dioxide, silicon nitride, silicon dioxide (ONO). A conductive layer 420 is deposited over ONO 410 . Layer 420 can be doped polysilicon, polycide (doped polysilicon covered with a metal silicide), or some other conductive material. A dielectric layer (not shown) can optionally be formed on layer 420 . Then the array is masked by photoresist (not shown), and layers 420 , 410 , 130 . 2 , 130 . 1 , 120 are removed from the peripheral area. Oxide 210 . 1 ( FIG. 12B ) covering the sidewalls of polysilicon 130 . 1 is also removed from the periphery. The photoresist is removed, and silicon dioxide 1310 ( FIG. 14 ) is grown on the peripheral active areas on substrate 110 . Oxide 1310 can be removed in the low voltage areas 920 , and then re-grown in the low and high voltage areas, to provide a thicker oxide in high voltage areas 910 and a thinner oxide in low voltage areas 920 . Polysilicon 1320 is deposited and patterned to form the peripheral transistor gates. Polysilicon 1320 is removed from the array area. A photoresist layer (not shown) is deposited to define the wordlines 420 ( FIG. 5A ). Layers 420 , 410 , 130 . 2 , 130 . 1 , 120 are etched in the array area as defined by the photoresist to form the wordlines and the floating gates and to expose the silicon substrate 120 in bitline regions 520 B and source line regions 520 S. N type dopant is implanted into these regions. Suitable doping is performed to form the source and drain regions 1330 ( FIG. 15 ) for the peripheral PMOS and NMOS transistors. FIG. 15 shows a vertical cross section by a plane perpendicular to the plane of FIG. 14 and passing through a peripheral active area (this may be either a high voltage or a low voltage area). In the example of FIG. 15 , regions 1330 are LDD (lightly doped drain) regions, formed by conventional techniques using dielectric spacers 534 . 1 on the sidewalls of gates 1320 . Dielectric 534 . 1 is part of dielectric 534 , and is not shown separately in FIG. 5C . Non-LDD structures are also possible. Formation of dielectric 534 is completed using suitable deposition techniques to provide a planar top surface in the array and peripheral areas. Contact openings 530 ( FIG. 5C ) are etched to bitline regions 520 B. Other contact openings (not shown) are etched to the peripheral transistor regions. Tungsten plugs 524 are formed in the contact openings. A conductive layer 510 (e.g. polysilicon or metal) is deposited and patterned to form the bitlines.

The peripheral processing can be performed using many techniques, known or to be invented. For example, the peripheral transistor gates can be formed from layer 420 . See also the aforementioned U.S. Pat. No. 6,355,524, and see U.S. patent application Ser. No. 10/772,520 filed Feb. 4, 2004 by Chua-Shun Hsiao et al. and incorporated herein by reference.

The floating gate fabrication techniques described above can be incorporated into many memory structures, known or to be invented. Exemplary split-gate cell structures are shown in FIGS. 16 , 17 A, 17 B. FIGS. 16 , 17 A illustrate the memory cross-sections passing through the control gates 420 between the trenches (such as cross section C-C in FIG. 5A ). FIG. 16 illustrates a cell in which the layer 420 provides a control gate and a select gate.

FIG. 17A illustrates a cell in which the select gate is provided by a separate conductive layer 1510 . This type of cell is described in the aforementioned U.S. Pat. No. 6,355,524. The top view of the memory array is shown in FIG. 17B . Line C—C in FIG. 17B marks the cross sectional plane of FIG. 17A . Layer 1514 is a dielectric deposited on wordline layer 420 before the wordlines are defined. Layers 1514 , 420 , 410 , 130 . 2 , 130 . 2 are then patterned as described above in connection with FIG. 5B . Then dielectric 1520 is formed over the sidewalls of each “row” structure defined as a structure formed by the layers 1514 , 420 , 410 , 130 . 2 , 130 . 1 in one memory row. The exposed portions of oxide 120 are etched away, and gate dielectric 1530 is formed on the exposed substrate areas for the select transistors. Doped polysilicon 1510 is conformally deposited and anisotropically etched to form wordlines. Each wordline provides the select gates for one row.

In some embodiments, the lateral etch of oxide 120 ( FIG. 7 ) is performed before the trench-forming etch of substrate 110 .

In some embodiments, the edges 130 E ( FIG. 7 ) of polysilicon 130 . 1 are not aligned directly above the trench edges 150 E at the conclusion of the etch of substrate 110 . For example, the edges 130 E may be positioned above the active area away from the trenches. The etch of oxide 120 may remove the oxide at the trench edges, but the oxide etch does not necessarily etch the oxide under the polysilicon 130 . 1 . The oxide etch may be a vertical etch having no lateral component. Alternatively, the edges polysilicon 130 E and the underlying oxide 120 may overhang the trenches, and the subsequent etch of oxide 120 may remove the oxide at the edges polysilicon 130 E but the oxide 120 may remain at the trench edges 150 E.

The invention is not limited to the structures and methods described above. Each isolation trench 150 may run through the whole array, without terminating at source lines 520 S. The source lines may go up and down traversing the isolation trenches, or individual source line regions 520 S may be separated by the trenches and interconnected by a line formed above the substrate 120 . See U.S. patent application Ser. No. 09/969,841 published as no. 2003-0068859 A1, incorporated herein by reference. The invention covers NAND memories and other array architectures, known or to be invented. The invention is not limited to any materials or fabrication processes. For example, floating gate layers 130 . 1 , 130 . 2 can be formed from different materials. The top surface of layer 130 . 2 could be even with, or below, the top surface of layer 130 . 1 . The invention is not limited to any memory programming or erase mechanisms. For example, the memory of FIGS. 5A–5C can be programmed by channel hot electron injection or Fowler-Nordheim tunneling of electrons from substrate 110 to floating gates 130 , and erased by Fowler-Nordheim tunneling from the floating gates to the substrate. Other programming and erase mechanisms are also possible. Exemplary programming and erase mechanisms for the memory of FIGS. 17A , 17 B are described in the aforementioned U.S. Pat. No. 6,355,524 and U.S. patent application Ser. No. 09/969,841. The invention includes both flash and non-flash memories. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.