Semiconductor memory device including internal clock doubler

1. Field of the Invention

The present invention generally relates to a semiconductor memory device including an internal clock doubler, and more specifically, to a technology of holding output data for 2 clocks only when data are outputted in a read mode.

2. Description of the Prior Art

A random access memory (hereinafter, referred to as “RAM”) of semiconductor memories which can access randomly to a memory place and perform both write and read operations of information has been widely used in a memory device of computer and its peripheral terminal equipment.

The RAM includes a dynamic RAM for performing a refresh operation for each predetermined period not to delete information and a static RAM whose information is not deleted only if the static RAM is connected to power.

Although the static RAM is easily connected to other integrated circuits, the static RAM requires more than 3˜4 times devices if it is used with the same memory capacity as that of the dynamic RAM. As a result, the static RAM becomes more complicated and expensive.

Recently, studies have been made on a pseudo SRAM for performing the same operation as that of the static RAM using a cell of the dynamic RAM. In the pseudo SRAM, the chip size becomes smaller than that of the conventional static RAM, and high integration such as 16 Mbit, 32 Mbit and 64 Mbit can be embodied.

The pseudo SRAM outputs data with 1 clock hold or 2 clock holds. In the 1 clock hold, outputted data are maintained only for 1 clock, and other data are outputted if the next clock enters. In the 2 clock holds, outputted data are maintained for 2 clocks, and other data are outputted if the next clock enters. That is, during the 2 clock holds, if data are outputted in the first clock, the data are maintained until the second clock, and if other data are outputted in the third clock, the other data are maintained until the fourth clock.

In this way, the conventional semiconductor memory device uses an internal clock doubler in order to continuously maintain output data for 2 clocks.

However, the conventional semiconductor memory device holds data for 2 clocks in a read mode as well as in a write mode unnecessarily by using an internal clock doubler. As a result, the whole operation time of the chip increases.

Accordingly, it is an object of the present invention to prevent increase of the whole operation time of the chip by holding output data for 2 clocks only in a read mode in response to a write enable bar signal /WE.

It is another object of the present invention to prevent increase of read time by holding output data for 2 clocks only when data are actually outputted although a read command is inputted using a standby signal.

In an embodiment, a semiconductor memory device including an internal clock doubler comprises an internal clock doubler, a sense amplifier control signal generator, a sense amplifier output unit and an output buffer unit. The internal clock doubler doubles an external clock signal in a read mode to output a double clock signal in response to a plurality of external control signals, and delays the external clock signal to output a clock control signal. The sense amplifier control signal generator receives the clock control signal and a standby signal of the plurality of external control signals which represents an output state of data to generate a plurality of sense amplifier control signals for controlling output of output data of a sense amplifier. The sense amplifier output unit outputs output data of the sense amplifier in response to the plurality of sense amplifier control signals. The output buffer unit outputs output data of the sense amplifier synchronously with respect to the double clock signal in response to the standby signal when data are outputted.

Other aspects and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a diagram illustrating a semiconductor memory device including an internal clock doubler according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of an internal clock doubler of FIG. 1 ;

FIG. 3 is a circuit diagram of a sense amplifier control signal generator of FIG. 1 ;

FIG. 4 is a circuit diagram of a clock shifter of FIG. 3 ;

FIG. 5 is a detailed circuit diagram of a sense amplifier control signal selecting unit of FIG. 3 ;

FIG. 6 is a circuit diagram of a sense amplifier output unit of FIG. 1 ;

FIG. 7 is a detailed circuit diagram of a clock shifter of FIG. 6 ;

FIG. 8 is a circuit diagram of an output buffer unit of FIG. 1 ; and

FIG. 9 is a timing diagram illustrating the operation of a semiconductor memory device including an internal clock doubler according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a semiconductor memory device including an internal clock doubler according to an embodiment of the present invention.

In an embodiment, the semiconductor memory device comprises an internal clock doubler 10 , a sense amplifier control signal generator 20 , a sense amplifier output unit 30 and an output buffer unit 40 .

The internal clock doubler 10 receives a write enable bar signal WEB, a mode register setting signal MRS, an external clock signal CLK and a standby signal WAIT, and outputs a double clock signal CLK_DOUT by doubling a clock period of the external clock signal CLK if data are outputted. Also, the internal clock doubler 10 delays the external clock signal CLK to output a clock control signal CLK_CON.

The sense amplifier control signal generator 20 outputs a sense amplifier control signal SW<0:3> for controlling output of a sense amplifier by using the clock control signal CLK_CON and the standby signal WAIT. Here, the sense amplifier control signal SW<0:3> controls when sense amplifier output data SAOUT sensed in each 1 clock is outputted to the output buffer unit 40 .

The sense amplifier output unit 30 receives the sense amplifier control signal SW<0:3>, a power-up signal PWRUP, the mode register setting signal MRS, the sense amplifier output data SAOUT and the clock control signal CLK_CON, and outputs a selecting data SAIN.

The sense amplifier output unit 30 controls an output timing of the sense amplifier output data SAOUT in response to the sense amplifier control signal SW<0:3>. That is, although a sense amplifier (not shown) outputs data in each 1 clock in a read modes the sense amplifier output unit 30 is controlled by the sense amplifier control signal SW<0:3> and holds output data for 2 clocks to output the data.

The output buffer unit 40 receives the double clock signal CLK_DOUT and the selecting data SAIN, and holds the selecting data SAIN for 2 clocks synchronously with respect to the double clock signal CLK_DOUT in response to the standby signal WAIT to output the selecting data SAIN. Here, the standby signal WAIT is maintained at a low level before data are outputted, and transits to a high level if the data start to be outputted. Accordingly, the output buffer unit 40 holds output data for 2 clocks after the data are outputted in response to the standby signal WAIT.

FIG. 2 is a circuit diagram of the internal clock doubler 10 of FIG. 1 .

The internal clock doubler comprises an input unit 11 , a clock delay unit 12 , a clock doubling unit 13 and an output unit 14 .

The input unit 11 comprises a write enable bar buffer output unit 15 , NAND gates NAND 1 and NAND 2 and inverters I 5 ˜I 8 .

The write enable bar buffer output unit 15 which comprises a plurality of inverter chains I 1 ˜I 4 buffers a write enable bar signal WEB to output a write enable bar input signal WEBIN.

The NAND gate NAND 1 performs a NAND operation on the mode register setting signal MRS and the standby signal WAIT. The inverters I 5 ˜I 7 delay an output signal from the NAND gate NAND 1 , and outputs the delayed signal to the NAND gate NAND 2 . The inverter 18 inverts the output signal from the NAND gate NAND 1 to output a standby input signal WAITIN.

Here, the standby signal WAIT is enable when data are outputted.

The NAND gate NAND 2 performs a NAND operation on the write enable bar input signal WEBIN, the mode register setting signal MRS and output signals from the inverters I 5 ˜ 17 , and outputs an output control signal PASS_CON for controlling the output unit 14 . Here, the semiconductor memory device is operated at 1 clock hold if the mode register setting signal MRS is at a low level, and the semiconductor memory device is operated at 2 clock hold if the mode register setting signal MRS is at a high level. If the write enable bar input signal WEBIN is at a low level, the semiconductor memory device performs a write operation, and if the write enable bar input signal WEBIN is at a high level, the semiconductor memory device performs a read operation.

The clock delay unit 12 comprises inverters I 17 ˜I 20 for delaying the external clock signal CLK to output the clock control signal CLK_CON. Here, the clock control signal CLK_CON for delaying the external clock signal CLK has the same frequency phase as that of the external clock signal CLK.

The clock doubling unit 13 which comprises inverters 19 and 110 , and latch units 16 and 17 doubles the clock control signal CLK_CON.

The latch unit 16 as a selecting non-inversion latch circuit comprises transmission gates T 1 and T 2 , an inverter I 11 and a NAND gate NAND 3 . The transmission gate T 1 is controlled by output signals from the inverters I 9 and I 10 , and transmits an output signal from an inverter I 13 to a node LATCH 1 to initialize the node LATCH 1 . The transmission gate T 2 is controlled by the output signals inverters I 9 and I 10 , and transmits an output signal from the inverter I 11 to the node LATCH 1 .

For example, if the output signal from the inverter 19 is at a high level, the transmission gate T 1 is turned on and the transmission gate T 2 is turned off. As a result, an output signal from the inverter I 13 is transmitted to the node LATCH 1 , and the NAND gate NAND 1 transmits an unlatched signal of the node LATCH 1 to a transmission gate T 3 when the standby input signal WAITIN is at a low level. Meanwhile, if the output signal from the inverter I 9 is at a low level, the transmission gate T 1 is turned off and the transmission gate T 2 is turned on. As a result, the output signal from the inverter I 11 is transmitted to the node LATCH 1 and latched. That is, if the transmission gate T 2 is turned on, the NAND gate NAND 3 and the inverter I 11 form a latch structure. Here, the operation of the signal of the node LATCH 1 is shown in the timing diagram of FIG. 9 .

The latch unit 17 as a selecting non-inversion latch circuit comprises transmission gates T 3 and T 4 , inverters I 12 and I 13 . The transmission gate T 3 is controlled by the output signals from the inverters I 9 and I 10 , and transmits an output signal from the NAND gate NAND 3 to a node LATCH 2 . The transmission gate T 4 is controlled by the output signals from the inverters I 9 and I 10 , and transmits the output signal from the inverter 113 .

For example, if the output signal from the inverter 19 is at the high level, the transmission gate T 3 is turned off and the transmission gate T 4 is turned on. As a result, the output signal from the inverter I 13 is transmitted to the node LATCH 2 , and the inverters I 12 and I 13 form a latch structure. Meanwhile, if the output signal from the inverter I 10 is at a high level, the transmission gate T 3 is turned on and the transmission gate T 4 is turned off. As a result, an the output signal from the NAND gate NAND 3 is transmitted to the node LATCH 2 . Here, the operation of the signal of the node LATCH 2 is shown in the timing diagram of FIG. 9 .

The clock doubling unit 13 latches the clock control signal CLK_CON received from the clock delay unit 12 through latch units 16 and 17 , and outputs a double clock signal CLK_DOUBLE.

The output unit 14 comprises transmission gates T 5 and T 6 , and inverters I 14 ˜I 16 .

The transmission gates T 5 and T 6 are controlled by the output control signal PASS_CON and an output signal from the inverter I 14 , and transmit the clock control signal CLK_CON and the double clock signal CLK_DOUBLE as input of the inverter I 15 , respectively. As a result, output signals from the transmission gates T 5 and T 6 are buffered through the inverters I 15 and I 16 , and outputted as final clock signals CLK_DOUT.

Hereinafter, the operation of the internal clock doubler 10 of FIG. 2 is described.

If the mode register setting signal MRS, the standby signal WAIT and the write enable bar signal WEB are all at a low level, the transmission gate T 6 is turned off and the transmission gate T 5 is turned on. As a result, the internal clock doubler 10 outputs the clock control signal CLK_CON.

Meanwhile, if the mode register setting signal MRS, the standby signal WAIT and the write enable bar signal WEB are at a high level, and the clock control signal CLK_CON is at a low level, the transmission gates T 1 , T 4 and T 6 are turned on. As a result, the internal clock doubler 10 outputs a value of the node LATCH 2 . On the other hand, if the mode register setting signal MRS, the standby signal WAIT and the write enable bar signal WEB are at the high level, and the clock control signal CLK_CON is at a high level, the transmission gates T 2 , T 3 and T 5 are turned on, the internal clock doubler 10 transmits a value of the node LATCH 1 to the node LATCH 2 , and outputs a value of the node LATCH 2 . The internal clock doubler 10 performs the above-described process repeatedly, and outputs the double clock signal CLK_DOUT having twice frequency of the external clock signal CLK.

FIG. 3 is a circuit diagram of the sense amplifier control signal generator 20 of FIG. 1 .

The sense amplifier control signal generator 20 comprises a plurality of clock shifters 21 , a plurality of sense amplifier control signal selecting units 22 and inverters I 17 ˜I 22 .

The plurality of clock shifters 21 receive the standby signal WAIT, the clock control signal CLK_CON and the power-up signal PWRUP, respectively, and outputs a signal for controlling the plurality of sense amplifier control signal selecting units.

The plurality of sense amplifier control signal selecting units 22 receive output signals from the plurality of clock shifters 21 , respectively, and output the sense amplifier control signals SW<0:3>.

The inverters I 17 and I 18 invert the clock control signal CLK_CON and the power-up signal PWRUP, and inverters I 19 ˜I 22 invert output signals from the plurality of sense amplifier control signal selecting units 22 .

FIG. 4 is a circuit diagram of the clock shifter 21 of FIG. 3 .

The clock shifter 21 comprises transmission gates T 7 and T 8 , NMOS transistors NM 1 and NM 2 , latch units 23 and 24 and inverter I 24 , I 27 .

The transmission gate T 7 is controlled by a signal CLK_CONB having the opposite phase to those of the clock control signal CLK_CON and the clock control signal CLK_CON, and transmits an input signal IN as input of a NAND gate NAND 4 .

The latch unit 23 comprises the NAND gate NAND 4 and an inverter I 23 .

The NAND gate NAND 4 selectively outputs an output signal from the transmission gate T 7 in response to the standby signal WAIT. The inverter I 23 inverts an output signal from the NAND gate NAND 4 , and transmits the inverted signal as input of the NAND gate NAND 4 .

The transmission gate T 8 is controlled by the clock control signals CLK_CON and CLK_CONB, and transmits an output signal from the inverter I 24 .

The latch unit 24 which comprises inverters I 25 and 126 latches an output signal from the transmission gate T 8 .

The NMOS transistors NM 1 and NM 2 is controlled by a power-up bar signal PWRUPB having the opposite phase to that of the power-up signal PWRUP, and initialize the output terminal of transmission gates T 7 and T 8 .

Hereinafter, the operation of the clock shifter 21 is described.

The transmission gate T 7 is turned on if the clock control signal CLK_CON is at a low level, and transmits the input signal IN to the latch unit 23 .

The NAND gate NAND 4 outputs a high level signal if the standby signal WAIT is at a low level, and the inverter I 24 inverts the output signal from the NAND gate NAND 4 . Then, when the clock control signal CLK_CON is at a high level, the transmission gate T 8 is turned on and transmits the output signal from the inverter I 24 to an output terminal. Here, while the standby signal WAIT is at the low level, the output signal from the NAND gate NAND 4 becomes at a high level and an output signal OUT from the clock shifter 21 is always at a low level, thereby preventing the sense amplifier control signal SW<0:3> from being enabled.

When the standby signal WAIT transits from the low level to a high level, the output signal OUT from the clock shifter 21 also transits from the low level to a high level. In response to the output signal OUT, the sense amplifier control signal selecting unit 22 selectively outputs the sense amplifier control signal SW<0:3>.

FIG. 5 is a detailed circuit diagram of the sense amplifier control signal selecting unit 22 of FIG. 3 .

The sense amplifier control signal selecting unit 22 which comprises inverters I 28 ˜I 30 and NAND gates NAND 5 ˜NAND 7 outputs a short pulse signal.

The NAND gate NAND 5 performs a NAND operation on the input signal IN and a signal sequentially inverted by the inverters I 28 and I 29 . The inverter 130 inverts an output signal from the NAND gate NAND 5 . The NAND gate NAND 6 performs a NAND operation on the input signal IN and an output signal from the inverter I 30 . The NAND gate NAND 7 performs a NAND operation on the input signal IN and an output signal from the NAND gate NAND 6 .

The plurality of sense amplifier control signal selecting units 22 selectively output the sense amplifier control signals SW 0 ˜SW 3 in response to output signal from the plurality of clock shifters 21 .

FIG. 6 is a circuit diagram of the sense amplifier output unit 30 of FIG. 1 .

The sense amplifier output unit 30 comprises a plurality of clock shifters 31 , a plurality of transmission unit 32 , a latch unit 33 and an output unit 34 .

The plurality of clock shifters 31 shift sense amplifier output data SAOUT synchronously with respect to the clock control signals CLK_CON and CLK_CONB, and transmit an output signal as input of the next clock shifter 31 .

The plurality of transmission unit 32 which comprises inverters I 31 and I 34 , and transmission gates T 7 ˜T 10 is controlled by the sense amplifier control signal SW<0:3>, and transmits output signals from each clock shifter 31 to the latch unit 33 .

The latch unit 33 which comprises inverters I 35 and I 36 latches output signals from the plurality of transmission unit 32 .

The output unit 34 comprises inverters I 37 and I 38 , and transmission gates T 11 and T 12 .

The inverter I 37 inverts an output signal from the latch unit 33 , and the inverter I 38 inverts the mode register setting signal MRS. The transmission gates T 11 and T 12 are controlled by an output signal from the inverter I 38 and the mode register setting signal MRS, and transmit the sense amplifier output data SAOUT and an output signal from the inverter 137 .

The output unit 34 turns on the transmission gate T 11 by the mode register setting signal MRS at the low level during the 1 clock hold operation, and outputs the sense amplifier output data SAOUT as selecting data SAIN. During the 2 clock hold operation, the output unit 34 turns on the transmission gate T 12 by the mode register setting signal MRS at the high level, and outputs an output signal from the inverter I 37 as the selecting data SAIN.

The above-described sense amplifier output unit 30 continuously shifts the sense amplifier output data SAOUT synchronously with respect to the external clock signal CLK, and selects one of the shifted sense amplifier output data SAOUT as the selecting data SAIN to the output buffer unit 40 in response to the sense amplifier control signals SW 0 ˜SW 3 selectively enabled synchronously with respect to the data signal DOUT.

FIG. 7 is a detailed circuit diagram of the clock shifter 31 of FIG. 6 .

The clock shifter 31 comprises transmission gates T 13 and T 14 , latch units 301 and 302 , and inverters I 41 , I 44 .

The transmission gate T 13 is controlled by the clock control signals CLK_CON and CLK_CONB, and transmits an input signal IN to the latch unit 301 . The latch unit 301 which comprises inverters I 39 and I 40 latches an output signal from the transmission gate T 13 .

The inverter I 41 inverts an output signal from the latch unit 301 , and outputs the inverted signal to the transmission gate T 14 . The transmission gate T 14 is controlled by the clock signals CLK_CON and CLK_CONB, and transmits an output signal from the inverter I 41 to a latch unit 302 . The latch unit 302 which comprises inverters I 42 and I 43 latches an output signal from the transmission gate T 14 . The inverter I 44 inverts an output signal from the latch unit 302 .

FIG. 8 is a circuit diagram of the output buffer unit 40 of FIG. 1 .

The output buffer unit 40 comprises a logic operation unit 41 , a transmission unit 42 , latch units 43 and 44 , and a driving unit 45 .

The logic operation unit 41 comprises inverters I 45 ˜I 47 , a NAND gate NAND 8 for performing a NAND operation on the standby signal WAIT and the selecting data SAIN, and a NOR gate NOR for performing a NOR operation on the standby signal WAIT and the selection data SAIN.

The transmission unit 42 comprises an inverter I 48 for inverting the double clock signal CLK_DOUT, and transmission gates T 7 and T 8 which are controlled by the double clock signal CLK_DOUT respectively, and transmit an output signal from the logic operation unit 41 to the latch units 43 and 44 .

The latch unit 43 comprises inverters I 49 and I 50 , and the latch unit 44 comprises inverters I 51 and I 52 . The latch units 43 and 44 latch an output signal from the transmission unit 42 at a predetermined level.

The driving unit 45 which comprises a PMOS transistor PM and a NMOS transistor NM 3 is controlled by output signals PU and PD from the latch units 43 and 44 , and outputs the data signal DOUT.

In the above-described output buffer unit 40 , if the standby signal WAIT is at the low level, the output signal PU from the latch unit 43 becomes at a high level and the output signal PD from the latch unit 44 becomes at a low level. As a result, the driving unit 45 is not operated, and the data signal DOUT becomes at a floating state.

Thereafter, when data start to be outputted, the standby signal WAIT becomes at the high level and the output signal PU becomes at a low level, thereby driving the PMOS transistor PM to output the data output signal DOUT. If the transmission gates T 7 and T 8 transmit an output signal from the logic operation unit 41 to the latch units 43 and 44 in response to the double clock signal CLK_DOUT, the PMOS transistor PM is driven and holds the selecting data SAIN for 2 clocks to output the selecting data SAIN as output data DOUT.

FIG. 9 is a timing diagram illustrating the operation of a semiconductor memory device including an internal clock doubler according to an embodiment of the present invention.

During the read mode, when data start to be outputted, the standby signal WAIT is enabled. If the standby signal WAIT at the high level is inputted, the internal clock doubler 10 doubles the external clock signal CLK through the clock doubling unit 13 and outputs the double clock signal CLK_DOUBLE. During the read mode, the output unit 14 outputs the double clock signal CLK_DOUBLE as a double clock CLK_DOUT. As shown in FIG. 9 , the double clock CLK_DOUT has twice clock frequency of the external clock signal CLK.

Thereafter, the sense amplifier control signal generator 20 sequentially outputs the sense amplifier control signal SW<0:3>, and sequentially generates the sense amplifier output data SAOUT as the selecting data SAIN.

The output buffer unit 40 receives the selecting data SAIN in response to the standby signal WAIT, and outputs data DOUT synchronously with respect to the double clock CLK_DOUT at a 2 clock hold.

As discussed earlier, a semiconductor memory device including an internal clock doubler in an embodiment of the present invention can reduce read time by doubling an internal clock period only when data are actually outputted in a read mode to maintain output data for 2 clocks.