Power supply apparatus for delay locked loop and method thereof

The present invention relates to a semiconductor device; and, more particularly, to a power supply apparatus for supplying power to a delay locked loop (DLL).

A voltage required for operating a delay locked loop (DLL), namely a DLL voltage should hold a steady voltage level independent of an external power supply voltage. It is also required that the DLL voltage should be stable regardless of noises caused by the external power supply voltage and an internal circuit of a DLL voltage supply device.

FIG. 1 is a block diagram showing a conventional DLL voltage supply device.

As shown, the conventional DLL voltage supply device includes a bandgap voltage generator 110 , a voltage level shifter 120 and a DLL 130 .

The bandgap voltage generator 110 generates a bandgap voltage V bg which is steady, i.e., not influenced by some variations such as power, voltage and temperature.

The voltage level shifter 120 increases a voltage level of the bandgap voltage V bg for raising the voltage level of the bandgap voltage V bg to the required voltage level to operate the DLL 130 . As a result, the voltage level shifter 120 outputs a DLL voltage V DLL for operating the DLL 130 .

FIG. 2 is a schematic circuit diagram showing the voltage level shifter 120 shown in FIG. 1 .

As shown, the voltage level shifter 120 includes an amplifying unit 210 , a p-channel metal oxide semiconductor (PMOS) driver 220 and a resistor unit 230 .

At initial state, the amplifying unit 210 compares the bandgap voltage V bg with a feed-back voltage V fb to determine whether or not the bandgap voltage V bg and the feed-back voltage V fb have a same voltage level.

If the bandgap voltage V bg is higher than the feed-back voltage V fb , a lower current is flown on a first n-channel metal oxide semiconductor (NMOS) transistor MN 1 than that of a second NMOS transistor MN 2 . Therefore, a voltage on a gate of a PMOS transistor MP 1 is lowered, whereby a voltage level of the feed-back voltage V fb is raised.

On the other hand, if the bandgap voltage V bg is lower than the feed-back voltage V fb , a higher current is flown on the first NMOS transistor MN 1 than that of the second NMOS transistor MN 2 . Therefore, a voltage on the gate of the PMOS transistor MP 1 is raised, whereby a voltage level of the feed-back voltage V fb is lowered.

As a result, the bandgap voltage V bg and the feed-back voltage V fb have a same voltage level during a normal operation.

Herein, the bandgap voltage V bg holds a steady voltage level even though a power supply voltage VDD is changed. On the other hand, since the feed-back voltage V fb is generated by using the DLL voltage V DLL , a voltage level of the feed-back voltage V fb is lowered if a voltage level of the DLL voltage V DLL is lowered.

The resistor unit 230 is a voltage divider for outputting the feed-back voltage V fb to the amplifying unit 210 and raises a voltage level of the feed-back voltage V fb to a voltage level of the DLL voltage V DLL . The PMOS driver 220 outputs the DLL voltage V DLL .

FIG. 3 is a linear diagram showing a relation between the power supply voltage VDD and the DLL voltage V DLL .

As shown, as a voltage level of the power supply voltage VDD is lowered, a voltage level of the DLL voltage V DLL is also lowered. Herein, when voltage levels of the power supply voltage VDD and the DLL voltage V DLL are lowered, a voltage level of the DLL voltage V DLL is always lower than that of the power supply voltage VDD by a constant voltage value.

Since the PMOS transistor MP 1 is saturated, a voltage level of the DLL voltage V DLL is lower than that of the power voltage VDD by a drain-source voltage of the PMOS transistor MP 1 , i.e., the constant voltage level.

Therefore, when a voltage level of the power supply voltage VDD is lowered, the DLL 130 can be operated abnormally because of an insufficient voltage level of the DLL voltage V DLL .

It is, therefore, an object of the present invention to provide a DLL power supply device capable of keeping a DLL voltage level equal to a power supply voltage level when the DLL voltage level becomes lower than a minimum voltage level required for a DLL to operate stably.

In accordance with an aspect of the present invention, there is provided a DLL voltage supply device for use in a semiconductor memory device including: a bandgap voltage generating means for generating a bandgap voltage by using an external power supply voltage; a voltage level shifter for increasing a voltage level of the bandgap voltage in order to output an increased bandgap voltage as a DLL voltage; and a voltage level keep means for outputting the external power supply voltage as the DLL voltage if the increased bandgap voltage is lower than a predetermined voltage level.

In accordance with another aspect of the present invention, there is provided a method of supplying power to a DLL included in a semiconductor memory device including a step of: generating a bandgap voltage which is steady and is not influenced by external conditions by using an external power supply voltage; shifting the bandgap voltage to a first voltage and outputting the first voltage as a DLL voltage when the external power supply voltage is higher than a predetermined voltage level; and outputting the external power supply voltage as the DLL voltage when the external power supply voltage is lower than the predetermined voltage level.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a conventional DLL voltage supply device;

FIG. 2 is a schematic circuit diagram showing a voltage level shifter shown in FIG. 1 ;

FIG. 3 is a linear diagram showing a relation between a power supply voltage and a DLL voltage;

FIG. 4 is a schematic circuit diagram showing a DLL voltage generating unit included in a DLL power supply device in accordance with a preferred embodiment of the present invention; and

FIG. 5 is a linear diagram showing an operation of a second DLL voltage generating unit shown in FIG. 4 .

Hereinafter, a power supply device for a DLL in accordance with the present invention will be described in detail referring to the accompanying drawings.

FIG. 4 is a schematic circuit diagram showing a DLL voltage generating unit included in a DLL power supply device in accordance with a preferred embodiment of the present invention.

As shown, the DLL voltage generating unit includes a voltage level shifter 410 and a voltage level protection unit 420 .

The voltage level shifter 410 includes an amplifying unit 210 , a first p-channel metal oxide semiconductor (PMOS) driver 220 and a resistor unit 230 .

At initial state, the amplifying unit 210 compares a bandgap voltage V bg with a feed-back voltage V fb to determine whether or not the bandgap voltage V bg and the feed-back voltage V fb have a same voltage level.

If the bandgap voltage V bg is higher than the feed-back voltage V fb , a lower current is flown on a first n-channel metal oxide semiconductor (NMOS) transistor MN 1 than that of a second NMOS transistor MN 2 . Therefore, a voltage on a gate of a PMOS transistor MP 1 is lowered, whereby a voltage level of the feed-back voltage V fb is raised.

On the other hand, if the bandgap voltage V bg is lower than the feed-back voltage V fb , a higher current is flown on the first NMOS transistor MN 1 than that of the second NMOS transistor MN 2 . Therefore, a voltage on the gate of the PMOS transistor MP 1 is raised, whereby a voltage level of the feed-back voltage V fb is lowered.

As a result, the bandgap voltage V bg and the feed-back voltage V fb have a same voltage level during a normal operation.

Herein, the bandgap voltage V bg holds a steady voltage level even though a power supply voltage VDD is changed. On the other hand, since the feed-back voltage V fb is generated by using the DLL voltage V DLL , a voltage level of the feed-back voltage V fb is lowered if a voltage level of the DLL voltage V DLL is lowered.

The resistor unit 230 is a voltage divider for outputting the feed-back voltage V fb to the amplifying unit 210 and raises a voltage level of the feed-back voltage V fb to a voltage level of the DLL voltage V DLL . The PMOS driver 220 outputs the DLL voltage V DLL .

The voltage level protection unit 420 includes a comparing unit 421 , an inverting unit 422 and a second PMOS driver 423 .

The comparing unit 421 detects a voltage difference between the bandgap voltage V bg and the feed-back voltage V fb in order to amplify the voltage difference. Herein, the bandgap voltage V bg and the feed-back voltage V fb can have a minute voltage difference due to some variations during a manufacturing process. Therefore, the comparing unit 421 has a small amplification gain.

However, if a power supply voltage VDD becomes lower than a predetermined voltage level, the feed-back voltage V fb becomes lower than the bandgap voltage V bg by a large amount of a voltage value, i.e., they have a wide voltage difference.

Because of the wide voltage difference between the feed-back voltage V fb and the bandgap voltage V bg , an output signal of the comparing unit 421 has a higher voltage level than that of a logic high voltage. Herein, the logic high voltage is a required maximum voltage for an output signal of the inverting unit 422 to be in a logic low level.

The comparing unit 421 is designed so that its output signal can have a lower voltage level than that of a logic low voltage during an initial state. Herein, the logic low voltage is a required minimum voltage for the output signal of the inverting unit 422 to be in a logic high level.

Meanwhile, if the output signal of the inverting unit 422 is in a logic low level when the power supply voltage VDD is lower than the predetermined voltage level, a PMOS transistor included in the PMOS driver is operated in a linear region. Therefore, the PMOS transistor is turned on connecting the DLL voltage V DLL to the power supply voltage VDD. As a result, the power supply voltage VDD is outputted as the DLL voltage V DLL .

Herein, for equalizing the DLL voltage to the power supply voltage VDD, a resistance of the PMOS transistor is required to be very small, and, thus a size of the PMOS transistor is required to be large.

The operation of the DLL voltage generating unit is described below referring to FIG. 4 .

As shown in FIG. 4 , outputs of the first DLL voltage generating unit 410 and the second DLL voltage generating unit 420 are connected each other.

When the power supply voltage VDD is higher than the predetermined voltage level, the first DLL voltage generating unit 410 normally outputs the DLL voltage V DLL as described above. At this time, the output of the inverting unit 422 is in a logic high level, and, thus the PMOS transistor included in the PMOS driver 423 is turned off. Therefore, the second DLL voltage generating unit 420 does not outputs the DLL voltage V DLL while the power supply voltage VDD is higher than the predetermined voltage level.

If the power supply voltage VDD is lower than the predetermined voltage level, the output signal of the inverting unit 422 is in a logic low level, and, thus the PMOS transistor is turned-on connecting the power supply voltage VDD to the DLL voltage V DLL . Therefore, the power supply voltage VDD is outputted as the DLL voltage V DLL .

FIG. 5 is a linear diagram showing the operation of the second DLL voltage generating unit 420 .

As shown, as a voltage level of the power supply voltage VDD is lowered, the DLL voltage V DLL is lowered holding a same voltage level as that of the power supply voltage VDD.

Therefore, even though the power supply voltage VDD is lowered, the DLL voltage V DLL is not lowered than the power supply voltage VDD since the power supply voltage VDD is outputted as the DLL voltage V DLL , whereby a DLL included in a semiconductor memory device can be operated stably.

The present application contains subject matter related to Korean patent application No. 2003-76267, filed in the Korean Patent Office on Oct. 30, 2003, the entire contents of which being incorporated herein by reference.

While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.