Temperature compensated self-refresh (TCSR) circuit having a temperature sensor limiter

The present invention relates to a TCSR (Temperature Compensated Self-refresh) for a semiconductor memory; and, more particularly, to a TCSR having a sensor limiter capable of preventing a refresh cycle from being dropped below a certain degree by providing a predetermined limit in a self-refresh cycle at an ultra low temperature.

Generally, in a portable semiconductor memory apparatus, it is important to decrease a self-refresh current.

In a method for decreasing a self-refresh current, there are a partial array self-refresh (PASR), and a temperature compensated self-refresh (TCSR). In the above conventional PASR and RCSR, a user used them by programming based on EMRS.

In the TCSR, a self-refresh cycle is changed based on a temperature set by a user. Since a data retention time is extended at a low temperature, it is possible to decrease a current consumption by extending a self-refresh cycle.

In the TCSR, a user does not set a temperature outside, but a temperature sensor is provided in the interior of a memory chip, thus automatically adjusting a refresh cycle based on a temperature. The above construction is referred to as an on-die TCSR.

Here, the temperature sensor is operated in such a manner that a current flowing in a diode is changed based on a temperature. Since the current flowing through a diode is low at a low temperature, a refresh cycle is set to be long.

However, in the conventional art, there is a problem that a refresh cycle is limitlessly extended as the temperature is getting closer to a low degree.

For example, the current flowing in a temperature sensor is too low at a low temperature such as 25 degrees below zero, and the cycle of a refresh cycle signal is extended to a degree of 65 μs, and the extended cycle is used as a basic cycle in a self-refresh circuit. In the above state, when a refresh is performed with respect to the whole memory chip parts at a basic cycle in the self-refresh circuit, the total refresh time is about 1 to 2 seconds. Therefore, a memory cell fails to maintain data during a refresh time period, thus losing data.

It is, therefore, an object of the present invention to provide a temperature compensated self-refresh (TCSR) circuit having a temperature sensor limiter that overcomes the problems encountered in the conventional art.

It is another object of the present invention to provide a temperature compensated self-refresh (TCSR) circuit having a temperature sensor limiter capable of preventing a refresh cycle from being dropped below a certain cycle using a temperature sensor limiter when the temperature is decreased below a certain degree.

To achieve the above objects, there is provided a temperature-compensated self-refresh circuit (TCSR) having a temperature sensor limiter comprising a voltage comparator that compares a reference voltage with a temperature voltage, a delay unit that delays a signal from the voltage comparator, a controller that is controlled by a temperature limit signal and a temperature sensor enable signal and outputs a temperature sensor control signal and outputs a temperature-compensated refresh cycle signal using a signal from the delay unit, a temperature sensor that is controlled by the temperature sensor control signal and outputs a temperature voltage based on the temperature using a diode, and a temperature sensor limiter that is reset by the refresh cycle signal and outputs a temperature sensor limit signal that the refresh basic cycle signal is divided when the temperature sensor is not used.

The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a TCSR (Temperature Compensated Self-Refresh) according to the present invention;

FIG. 2 is a detailed circuit diagram illustrating a voltage comparator in the TCSR of FIG. 1 according to the present invention;

FIG. 3 is a detailed circuit diagram of a delay unit in the TCSR of FIG. 1 according to the present invention;

FIG. 4 is a detailed circuit diagram illustrating a controller in the TCSR of FIG. 1 according to the present invention;

FIG. 5 is a detailed circuit diagram illustrating a temperature sensor in the TCSR of FIG. 1 according to the present invention; and

FIG. 6 is a detailed block diagram illustrating a temperature sensor limiter in the TCSR of FIG. 1 according to the present invention.

Hereinafter, a semiconductor device in accordance with the present invention will be described in detail referring to the accompanying drawings.

FIG. 1 is a block diagram of a TCSR according to the present invention. Here, the TCSR according to the present invention includes a voltage comparator 10 that compares a reference voltage REF with a temperature voltage NA from a temperature sensor 40 , a delay unit 20 that delays a signal COM from the voltage comparator 10 , a controller 30 that is controlled by a temperature sensor limit signal TMOSCRSTB and a temperature sensor enable signal TMON and outputs a temperature control signal CON and outputs a temperature-compensated refresh signal TMOSC using a signal DCOM from the delay unit 20 , a temperature sensor 40 that is controlled by a temperature sensor control signal CON from the controller 30 and outputs a temperature voltage NA based on a temperature, and a sensor limiter 50 that outputs a temperature sensor limit signal TMOSCRSTB using a refresh basic cycle signal SLOSCVBP used in a basic cycle generator of a self-refresh when the temperature sensor 40 is not used and a temperature-compensated refresh signal TMOSC.

FIG. 2 is a detailed circuit diagram of a voltage comparator 10 in the TCSR of FIG. 1 according to the present invention.

The voltage comparator 10 includes a reference voltage generator 11 that divides a power voltage VDD and generates a reference voltage REF, and a comparator 12 that compares a reference voltage REF with a temperature voltage NA from the temperature sensor 40 .

The reference voltage generator 11 includes two NMOS transistors NM 1 and NM 2 resistor-connected between a power voltage VDD and a ground voltage VSS in series. A reference voltage REF is outputted from a common node of the NMOS transistors NM 1 and NM 2 .

The comparator 12 includes PMOS transistors PM 1 and PM 2 connected in a current mirror type, NMOS transistors NM 3 and NM 4 in which a reference voltage REF and a temperature voltage NA are applied to each gate of the same, and the sources of the same are commonly connected with each other, and the drains of the same are connected with the drains of the PMOS transistors PM 1 and PM 2 , respectively, and a NMOS transistor NM 5 in which a drain of the same is connected with a common source of the NMOS transistors NM 3 and NM 4 , and a source of the same is connected with a ground voltage VSS. Here, capacitors C 1 and C 2 are connected with the gates of the NMOS transistors NM 3 and NM 3 , respectively.

FIG. 3 is a detailed circuit diagram of a delay unit 20 of the TCSR of FIG. 1 according to the present invention.

As shown therein, the delay unit 20 includes inverters INV 1 , INV 2 and INV 3 connected between an input terminal and an output terminal in series, and capacitors C 3 , C 4 and C 5 connected with each output terminal of the inverters INV 1 , INV 2 , and INV 3 .

Here, the controller 30 includes a NAND gate ND 1 that NANDs a temperature sensor enable signal TMON, a temperature sensor limit signal TMOSCRSTB and a signal DCOM from the delay unit 20 , respectively, an inverter INV 4 for inverting a signal from the NAND gate ND 1 and outputting a temperature sensor control signal CON, and an inverter INV 5 for inverting a signal from the inverter INV 4 and outputting a temperature-compensated refresh cycle signal TMOSC.

FIG. 5 is a detailed circuit diagram of a temperature sensor 40 of the TCSR of FIG. 1 according to the present invention.

As shown therein, the temperature sensor 40 includes PMOS transistors PM 3 and PM 4 and NMOS transistor NM 6 that are controlled by a temperature sensor control signal CON, and NMOS transistors NM 7 and NM 8 that are diode-connected between the output terminal NA and the NMOS transistor NM 6 in series. Here, the drain of the PMOS transistor PM 4 is connected with a common node of the diode-connected NMOS transistors NM 7 and NM 8 .

FIG. 6 is a detailed block diagram of a temperature sensor limiter 50 in the TCSR of FIG. 1 according to the present invention.

As shown therein, the temperature sensor limiter 50 includes a divider 51 that divides a refresh basic cycle signal SLOSCVBP used for a basic cycle generator of a self-refresh circuit when a temperature sensor 40 controlled by a temperature-compensated refresh cycle signal TMOSC is not used, a pulse generator 52 that generates a pulse using a signal from the divider 51 , and a pulse width adjusting unit 53 that outputs a temperature sensor limit signal TMOSCRSTB by adjusting a pulse width of a pulse from the pulse generator 52 . In the above embodiment of the present invention, the dividing ratio of the divider 51 was 8-divides. In another embodiment of the present invention, the dividing ratio may be changed based on a design of the system.

The present invention is basically directed to a method of forcibly generating a refresh cycle signal using a temperature sensor limit signal TMOSCRSTB that is a pulse signal having a certain cycle in the case that a temperature-compensated refresh cycle signal TMOSC is not generated within a cycle of a pulse signal.

Here, the temperature sensor limit signal TMOSCRSTB is a pulse signal having a constant cycle obtained by dividing a refresh basic cycle signal SLOSCVBP used for a self-refresh basic cycle generator.

At this time, when the temperature sensor limit signal TMOSCRSTB becomes a low pulse, the refresh cycle signal TMOSC becomes a high pulse.

In addition, when a refresh cycle signal TMOSC is generated, a temperature sensor limit signal TMOSCRSTB is not generated by resetting the divider 51 of the temperature sensor limiter 50 using a refresh cycle signal TMOSC.

The operations of the TCSR according to the present invention will be described in more detail with reference to FIGS. 1 to 6 .

The voltage comparator 10 compares a reference voltage REF with an electric potential NA by a voltage drop generating by a diode current of the temperature sensor 40 . If the reference voltage REF is larger, an output signal COM becomes a high level. Here, in the reference voltage REF, the power voltage VDD is divided based on a resistance ratio of two NMOS transistors NM 1 and NM 2 having a resistance role of the reference voltage generator 11 . For example, if the sizes of two NMOS transistors NM 1 and NM 2 are same, the reference voltage REF has a half value of the power voltage VDD.

The signal COM from the voltage comparator 10 is delayed by the delay unit 20 for obtaining a charging and discharging time of the capacitors C 1 and C 2 used in the voltage comparator 10 .

The controller 30 generates a signal CON used for controlling the temperature sensor 40 in response with a signal TMON enabling the temperature sensor 40 . In the case that the signal is a low level, a temperature-compensated refresh cycle signal TMOSC is not generated, and the signal remains a high level.

The temperature sensor 40 is a temperature sensor using a diode. The current flowing in a MOS diode has a certain function of the temperature. At this time, the current degree is decreased, as the temperature is decreased when the gate source voltage VGS is within about 3 volts.

Therefore, the output node NA becomes a high level when an enable signal TMON is a low level, thus charging the capacitor C 1 of the voltage comparator 10 .

When the enable signal TMON is a high level, the PMOS transistors PM 3 and PM 4 are turned off, so that the capacitor C 1 is discharged. At this time, the voltage drop is determined based on the current flowing in the NMOS diode NM 7 . Namely, at a high temperature, since the current flowing in the NMOS diode NM 7 is high, the voltage drop of the output node NA occurs fast. At a low temperature, since the current flowing in the NMOS diode NM 7 is low, the voltage drop of the output node NA occurs slowly.

When the electric potential of the output node NA of the temperature sensor 40 is lower than the reference voltage REF, the output COM of the voltage comparator 10 is a high level, and the PMOS transistors PM 3 and PM 4 of the temperature sensor are turned on, and the refresh cycle signal TMOSC becomes a high level.

When the PMOS transistors PM 3 and PM 4 of the temperature sensor 40 are turned on, and the output node NA becomes a high level, the capacitor C 1 of the voltage comparator 10 is charged, and a signal COM from the voltage comparator 10 becomes a low level, and the PMOS transistors PM 3 and PM 4 of the temperature sensor 40 are turned off, so that the refresh cycle signal TMOSC becomes a low level again.

The above operations are repeatedly performed. The refresh cycle signal TMOSC is changed to a pulse signal having a cycle determined based on the degree of the current flowing through the NMOS diode NM 7 of the temperature sensor 40 .

At this time, at a low temperature, even when the electric potential of the output node NA is not enough dropped because the degree of the current flowing in the NMOS diode NM 7 of the temperature sensor 40 is low, the temperature sensor 40 is reset after a certain time period is passed, this generating a refresh cycle signal TMOSC.

Namely, when a temperature sensor limit signal TMOSCRSTB that is a pulse signal having a constant cycle applied to the controller 30 is a low pulse, even when the electric potential NA of the output node of the temperature sensor 40 is higher than the reference voltage REF, the refresh cycle signal TMOSC becomes a high level, and the PMOS transistors PM 3 and PM 4 of the temperature sensor 40 are turned on, and the output node NA becomes a high level.

Here, the refresh basic cycle signal SLOSVBP used in a basic cycle generator of the self-refresh is divided and used as a temperature sensor limit signal PMOSCRSTB when the temperature sensor 40 is not used.

Namely, the refresh basic cycle signal SLOSVBP having a cycle of about 3˜4 μs is divided into 8 parts, thus generating a temperature sensor limit signal TMOSCRSTB having a cycle of about 25˜30 μs.

At this time, when the refresh cycle signal TMOSC occurs again, the divider 51 of the temperature sensor limiter 50 is reset, and the temperature sensor limit signal TMOSCRSTB does not occur any more.

As described above, in the temperature-compensated self-refresh circuit using a temperature sensor limiter according to the present invention, it is possible to prevent any loss of data that may occur as the refresh cycle is extended below a certain cycle at an ultra low temperature.

The present application contains subject matter related to Korean patent application No. 2003-69499, filed in the Korean Patent Office on Oct. 7, 2004, the entire contents of which being incorporated herein by reference.

While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.