Apparatus and method for performing parallel test on integrated circuit devices

This application claims priority from Korean Patent Application No. 2003-47415, filed on Jul. 11, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety for all purposes.

1. Field of the Invention

This disclosure relates to a test apparatus of an integrated circuit, and more particularly, to a parallel test apparatus and method of the integrated circuit capable of injecting a high test current.

2. Description of the Related Art

Generally, an integrated circuit device (hereinafter IC) is manufactured through multiple processes. Afterwards, a test process is performed to check whether the IC works properly and has any defects in its parts.

There are two types of test apparatus that can be used to perform the test process. One type is a single test apparatus that tests a single device under test (DUT) at one time and another type is a parallel test apparatus that tests several DUTs at the same time. The parallel test apparatus, which is very useful in mass production, is disclosed in U.S. patent application Ser. No. 6,480,978, entitled “Parallel Testing of Integrated Circuit Devices Using Cross-DUT and Within-DUT Comparisons” and Japanese Patent Publication No. 2001-176293, entitled “Test Method For Semiconductor Memory, And Test Device”.

FIG. 1 is a block diagram schematically illustrating a general apparatus to perform a parallel test on a plurality of devices under test (DUTs).

As illustrated in FIG. 1 , four DUTs (DUT 1 ˜DUT 4 ) are connected to a test circuit unit 10 . The DUT 1 through DUT 4 may each have two power pins (VDD, VDDQ), and the test circuit unit 10 may include a power supply providing a test current to the DUT 1 through the DUT 4 , a memory set (not shown) storing a test data, and a compare unit (not shown) comparing data stored in the memory set and test devices from the DUT 1 through the DUT 4 and outputting whether the data is normal or abnormal.

The test circuit unit 10 includes a first through a third power source VS 1 , VS 2 , and VS 3 . The VDDs of DUT 1 and DUT 2 are connected to the first power source VS 1 , the VDDs of DUT 3 and DUT 4 are connected to the second power source VS 2 , and the VDDQs of DUT 1 through DUT 4 are connected to the third power source VS 3 . Thus, DUT 1 through DUT 4 are connected to the test circuit 10 in a parallel manner.

In a parallel test apparatus having the above structure, if a predetermined voltage V is applied from the first through the third power source VS 1 , VS 2 , and VS 3 in the test circuit unit 10 , a test-performing current flows to the respective test devices of the DUT 1 through the DUT 4 .

The VDDs of DUT 1 and DUT 2 are commonly connected to the first power source VS 1 , and thus the current of the first power source VS 1 is distributed to each VDD of DUT 1 and DUT 2 . For instance, if an 800 mA current is generated in the first power source VS 1 , a 400 mA current flows into each VDD of DUT 1 and DUT 2 . This applies to the VDDs of DUT 3 and DUT 4 , each having half of the current generated in the second power source VS 2 .

However, in a case where a high integrated memory device such as a double data rate RAM (DDR), a test current of 400 mA or more per unit test device is required. Thus, if a set of DUTs shares one power source, the test current provided is divided to each DUT. The amount of the test current divided depends on the number of DUTs. Therefore, it is difficult to provide the high test current to each DUT. In this case, test efficiency and product reliability is decreased because the test may be improperly performed in the devices requiring the high test current. In addition, production cost is increased since a new instrument including the strong power supply should be added to obtain the high test current.

Embodiments of the invention address these and other disadvantages of the conventional art.

Some embodiments of the invention provide a test apparatus to test a plurality of devices under test (DUTs), the parallel test apparatus includes a plurality of power sources providing a test current to a plurality of DUTs, switching devices connected to the respective DUTs and power sources for selectively providing the test current, and at least one control unit to control an operation of the switching device. In the test apparatus, a set of DUTs from the plurality of DUTs is connected to one power source in a parallel manner, and the test current is provided only to one DUT out of the plurality of DUTs connected in a parallel manner according to the operation of the switching device.

The control unit outputs a first signal that turns each of the switching devices on and a second signal that selectively turns one of the switching devices connected to the respective power sources on at the same time. The DUTs include first and second power pins and the switching device is installed between the first power pin and the corresponding power source.

The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a block diagram schematically illustrating a general apparatus that performs a parallel test for a plurality of devices under test (DUTs).

FIG. 2 is a block diagram schematically illustrating a parallel test apparatus according to some embodiments of the invention.

FIG. 3 is a circuit diagram illustrating an example control unit for the parallel test apparatus of FIG. 2 .

FIG. 4 is a flow chart illustrating an operating method of a parallel test apparatus according to some embodiments of the invention.

The invention now will be described more fully with reference to the attached drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the forms of elements are exaggerated for clarity. To facilitate understanding, identical reference numerals have been used where possible to designate identical elements that are common to the figures.

Referring to FIG. 2 , a plurality of test devices, for instance, the four devices under test (DUTs), DUT 1 ˜DUT 4 are connected to a test circuit unit 150 . DUT 1 through DUT 4 each include two power pins VDD and VDDQ may each be an integrated circuit (IC) chip such as a memory device having a memory area.

The test circuit unit 150 is a parallel tester that tests a plurality of DUTs at the same time and may include a power supply 160 , a memory set 170 , and a controller 180 . The power supply 160 provides a test current to each DUT and may be formed of a first through a third power source VS 1 , VS 2 , and VS 3 .

The memory set 170 is a store unit in which data is stored when the DUT works properly.

The controller 180 may be formed of a first and second control unit 182 and 184 , and a compare unit 186 for comparing the data stored in the memory set 170 to the data in DUT 1 through DUT 4 .

The VDDs of DUT 1 and DUT 2 are commonly connected to the first power source VS 1 , the VDDs of DUT 3 and DUT 4 are commonly connected to the second power source VS 2 , and the VDDQs of DUT 1 through the DUT 4 are commonly connected to the third power source VS 3 . Accordingly, the three power sources VS 1 , VS 2 , and VS 3 provide a voltage and a current to the eight power pins. Thus, DUT 1 through DUT 4 are connected in parallel to the test circuit unit 150 .

In addition, a first switching device 210 is connected between the VDD of DUT 1 and the first power source VS 1 and a second switching device 220 is connected between the VDD of DUT 2 and the first power source VS 1 . Furthermore, a third switching device 230 is connected between the VDD of DUT 3 and the second power source VS 2 and a fourth switching device 240 is connected between the VDD of DUT 4 and the second power source VS 2 .

The switching devices 210 , 220 , 230 , and 240 may be relays. The first and third switching device 210 and 230 are selectively turned on/off by the first control unit 182 of the controller 180 , and the second and fourth switching device 220 and 240 are selectively turned on/off by the second control unit 184 of the controller 180 . Moreover, these switching devices 210 , 220 , 230 , and 240 may be designed to be turned on when a high signal is applied from the control unit 182 and 184 of the controller 180 and to be turned off when a low signal is applied from the control unit 182 and 184 of the controller 180 .

For example, the first control unit 182 , the first switching device 210 , and the DUT 1 may be formed as shown in FIG. 3 . As illustrated in FIG. 3 , the first control unit 182 is comprised of a bipolar transistor 185 . A selective signal SEL is input in a base B of the bipolar transistor 185 and a drive voltage V, for instance 5V, is applied in a collector C, and an emitter E is grounded. The base B and collector C are connected to a voltage drop resistance R, respectively. The first switching device 210 , or the relay and the DUT 1 are connected to the collector C, i.e., an output of the bipolar transistor 185 .

The first control unit and relay having the above structure is designed to transmit the current of the first power source VS 1 to the DUT 1 through a process that when a high voltage, for instance, 5V, is applied as the selective signal SEL, the voltage between the collector and emitter VCE becomes, for instance, 0.2V, and the switching device (or the relay) is turned on. Thus, the first control unit and relay are designed to transmit the current of the first power supply VS 1 to the DUT 1 .

In the meantime, if a low voltage, for example, 0V, is applied as the selective signal SEL, the collector-emitter voltage VCE becomes, for example 5V, and thus the first control unit and the relay are designed not to transmit the current of the first power supply VS 1 to the DUT 1 .

A method of operating the parallel test apparatus having the above structure according to some embodiments of the invention will be explained below with respect to FIG. 4 .

First, if a high signal is applied as the selective signal SEL of the first and second control unit 182 and 184 of the controller 180 , the first through fourth switching devices 210 , 220 , 230 , and 240 are all turned on (process SI) and the test current are provided to each test device from DUT 1 through DUT 4 (process S 2 ). The current generated from the first power source VS 1 is distributed to the VDDs of DUT 1 and DUT 2 and the current generated from the second power source VS 2 is divided to the VDDs of DUT 3 and DUT 4 , respectively. In addition, the current generated from the third power source VS 3 is allocated to the VDDQs of DUT 1 through DUT 4 . That is, if the first through the fourth switching devices 210 , 220 , 230 , and 240 are all turned on, half of the current that can be generated from the first and second power source VS 1 and VS 2 is provided, respectively. For instance, if a maximum 800 mA current can be generated from the first and second power supplies VS 1 and VS 2 , 400 mA current is provided to the VDDs of DUT 1 through DUT 4 when the first and fourth switching devices 210 , 220 , 230 , and 240 are turned on.

Furthermore, if the high signal as the selective signal SEL of the first control unit 182 is applied and a low signal as the selective signal SEL of the second control unit 184 is applied, the first and the third switching device 210 and 230 are turned on (process S 3 ) and the second and the fourth switching device 220 and 240 are turned off. Then, one DUT is only connected to one power supply, and thus the maximum test current that can be generated from the first and second power source VS 1 and VS 2 is applied to DUT 1 and DUT 3 connected to the first and third switching device 210 and 230 (process S 4 ). That is, if the maximum generable current from the first and second power sources VS 1 and VS 2 is 800 mA, an 800 mA current is provided to the VDDs of DUT 1 and DUT 3 , respectively. By this process, components that require the high current during test can easily be detected.

Moreover, if the high signal as the selective signal SEL is applied to the second control unit 184 and the low signal as the selective signal SEL is applied to the first control unit 182 , the second and fourth switching device 220 and 240 are turned on (process S 5 ) and the first and third switching devices 210 and 230 are turned off. Accordingly, the maximum generable test current from the first and second power sources VS 1 and VS 2 is applied to DUT 2 and DUT 4 connected to the second and fourth switching devices 220 and 240 (process S 6 ). That is, if the maximum generable current from the first and second power sources VS 1 and VS 2 is 800 mA, an 800 mA current is provided to the VDDs of DUT 2 and DUT 4 , respectively. In this process, the first and second control units 182 and 184 control two relays that are connected to mutually different power supply, and thus a test time can be reduced.

The invention is not limited to the embodiments described above. Although the embodiments described above have four DUTs and three power sources, the number of DUTs and power sources can be different, but the test result will be the same. What follows are exemplary, non-limiting descriptions of embodiments of the invention.

According to some embodiments of the invention, there is provided a parallel test apparatus to test the four devices under test (DUTs) from DUT 1 to DUT 4 each including first and second power pins, a parallel test apparatus to test the four devices under test (DUTs) from DUT 1 to DUT 4 respectively including first and second power pins, the apparatus including a first power source commonly connected to the first pins of DUT 1 and DUT 2 and providing a test current to the first pins, a second power source commonly connected to the first pins of the DUT 3 and DUT 4 and providing the test current to the first pins, a third power source commonly connected to the second pins of DUT 1 through DUT 4 and providing the test current to the second pins, switching devices selectively providing a test signal to one DUT connected to one of the power sources, and a control unit controlling an operation of the switching devices.

The switching devices include a first switching device installed between the first pin of DUT 1 and the first power source, a second switching device installed between the first pin of DUT 2 and the first power source, a third switching device installed between the first pin of DUT 3 and the second power source, and a fourth switching device installed between the first pin of DUT 4 and the second power source. The first through the fourth switching devices may be relays.

The control unit includes a first control unit operating the first and third switching device and a second control unit operating the second and fourth switching device.

According to other embodiments of the invention, there is provided a method of operating a parallel test apparatus having four devices under test (DUTs) including first and second power pins that are respectively connected to first and third power sources in a parallel manner, switching devices installed between the first pin of DUTs and the power sources, and first and second control units that control the switching devices, the method including providing a test current respectively distributed to the power pins of DUT 1 through DUT 4 by turning on all of the first through fourth switching devices, providing a maximum generable test current from the respective power sources to the first pins of DUT 1 and DUT 3 by turning on the first and third switching devices, and providing the maximum generable test current from the respective power sources to the second pins of DUT 2 and DUT 4 by turning on the second and fourth switching devices.

As described above, a plurality of DUTs are connected to the power supply (or power source) in the test circuit unit in a parallel manner and the switching devices, for example, the relays, are installed between the respective DUTs and power sources so that the maximum current of the power sources can be provided to all the unit DUTs.

Accordingly, test efficiency and product reliability can be enhanced by selectively providing the maximum generable current from the power sources, when performing the test requiring the high test current.

Furthermore, production cost is lowered by utilizing the existing instrument and supplying the high test current to a plurality of DUTs without an additional instrument.

Also, a test time is shortened since the two relays connected to the different power sources are designed to be simultaneously turned on/off.

While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.