Four phase charge pump operable without phase overlap with improved efficiency

This invention relates generally to electric circuits that generate a voltage larger than a supply voltage from which they operate by the switching of charge along serial capacitive cells, known as charge pumps.

A well known charge pump is the Dickson charge pump, which is shown in FIG. 1 . As described by Louie Pylarinos of the University of Toronto in “Charge Pumps: An Overview”, the circuit has two pumping clocks which are anti-phased and have a voltage amplitude of Vφ or {overscore (Vφ)}. Serial diodes or diode connected NMOSFETS, D 1 –D 4 , operate as self-timed switches characterized by a forward biased voltage, Vt, which is the threshold voltage of each diode. Each diode has a stray capacitance, Cs, associated therewith. The charge pump operates by pumping charge along the diode chain as capacitors C 1 –C 4 are successively charged and discharged during each clock cycle. For example, when Vφ goes high, diode D 1 conducts and the voltage at its anode, V 1 , is boosted by voltage Vφ and transferred to node V 2 less a voltage drop, Vt, associated with diode D 1 . Then when Vφ goes low, and {overscore (Vφ)} goes high, the charge at node V 2 is transferred to node V 3 less a voltage drop, Vt, associated with diode V 2 . After N stages, it is seen that the output voltage is

V out =V in +N ·( V φ −V d )− V d   (1)

The stray capacitance, Cs, can be taken into account by noticing that it reduces the transferred clock voltage, V φ , by a factor

C C + C s .

Thus, the actual output voltage becomes

Until now is has been assumed that no load was connected to the output of the charge pump. In the presence of such a load which draws a current, lout, the output voltage is reduced by an amount

N · I out ( C + C s ) · f osc ,

where fosc is the operating frequency of the charge pump. The output voltage now becomes

V out = V in + N · ( C C + C s · V ϕ - V d - I out ( C + C s ) · f osc ) - V d ( 3 )

From this equation it becomes apparent that the voltage multiplication will occur only if

C C + C s · V ϕ - V d - I out ( C + C s ) · f osc > 0 ( 4 )

Following Dickson, eq (3) can be written as

V out = Vo - I out · R s ⁢ ⁢ where ( 5 ) Vo = V in - V d + N · ( C C + C s · V ϕ - V d ) ⁢ ⁢ and ( 6 ) R s = N C + C s · f osc ( 7 )

Equation (3) leads to an equivalent circuit of the charge pump as shown in FIG. 2 .

Limitations of the Dickson charge pump when implemented with NMOS transistors or diode connected transistors lies in the trapped charge associated with each node due to the threshold voltage, V t , of each NMOS diode. While increasing capacitor charge reduces effective series resistance, R s , there is a practical limitation of capacitor size in an integrated circuit. While clock frequency, f osc , reduces series resistance, the charge must be able to be transferred from node to node within a cycle, otherwise increasing frequency will not improve pump performance.

A more efficient charge pump is provided by altering the Dickson charge pump in accordance with the present invention.

To facilitate charge transfer from one node to the next node, a parallel transistor is provided with each transfer diode whereby residual trapped charge of each node is transferred by the transistor. This requires a transistor clock within each cycle of the diode clock.

Clock frequency can be increased by providing with each parallel tansistor a pre-charge diode to pre-charge the gate of the parallel transistor after the input node charge is raised but before the charge transfer. This facilitates the conductance of the transistor with each transistor cycle.

During pre-charge, the pre-charge diode guarantees pre-charge of gate T 1 , the parallel transistor, without the need for clock phase overlap. A recovery transistor couples the gate of the parallel transistor to the input node to return transistor bias voltage to source voltage in the recovery period where the input node again goes low and the output node is high. Unlike known four phase charge pumps which require overlap of the pumping clocks, the charge pump in accordance with the invention can operate with 50/50 clock pulses having no overlap.

The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.

FIG. 1 illustrates a prior art Dickson charge pump.

FIG. 2 illustrates an equivalent circuit of the Dickson charge pump.

FIG. 3 is a schematic of a charge pump in accordance with one embodiment of the invention.

FIG. 4 illustrates clocks for operating the charge pump of FIG. 3 .

FIG. 3 is a schematic of a charge pump in accordance with one embodiment of the invention in which the cells of the conventional Dickson charge pump are modified to facilitate charge transfer and to accommodate a higher clock frequency or f osc . FIG. 3 shows two adjacent cells, such as diodes D 1 and D 2 of the Dickson charge pump of FIG. 1 , for transferring charge from node V 1 to node V 2 . Each cell is modified by providing a MOS transistor T 1 or T 2 in parallel with diode D 1 or diode D 2 which facilitate the transfer of residual trapped charge at each node. A recovery transistor TR is connected between the gate of transistor T 1 and node V 1 with the gate of transistor TR controlled by the voltage on node V 2 . When charge is transferred from node V 1 to node V 2 , the increased voltage at node V 2 causes transistor TR to conduct and bring the voltage on the gate of transistor T 1 to the voltage level of node V 1 . After clock φ 3 is removed, the conductance of transistor T 1 is terminated.

FIG. 4 illustrates the four phase clock operation of the charge pump of FIG. 3 . Charge transfer from node V 1 to node V 2 must occur during clock cycle φ 1 when charge coupled through capacitor C 0 raises the charge of node V 1 and forward biases diode D 1 which partially transfers the charge to node V 2 .

Transistor T 1 is in parallel with diode D 1 and conducts in response to clock φ 3 which is shorter than clock φ 1 and lies within clock cycle φ 1 . Thus, when φ 1 goes high, diode D 1 conducts but the current is limited because of the high V t of the diode. After a short delay, to allow pre-charge from V 1 to the gate of T 1 , clock φ 3 pumps node VC high and transistor T 1 conducts fully and transfers the remaining trapped charge at node V 1 to node V 2 , with node V 1 and node V 2 equalized. This operation is repeated for diode D 2 and transistor T 2 when clock φ 2 is high for stage 2 .

After charge is transferred from node V 1 to node V 2 in the first half cycle (Phi 1 =1, Phi 2 =0, Phi 3 =1, Phi 4 =0), Phi 3 goes from 1 to 0 bring down the gate of T 1 back to the pre-charge level before charge is transferred. T 1 is weakly on at this point or T 1 could be completely off depending upon pump operations. In the second half cycle (Phil 1 =0, Phil 2 =1), V 2 is coupled up by Phi 2 , V 1 is coupled down by Phil 1 , transistor TR is turned on (V 2 −V 1 −V t >0) and brings the voltage on the gate of transistor T 1 to the voltage level of node V 1 . Since the voltages of T 1 gate and source are the same, T 1 is completely shut off to prevent any backward leakage.

To facilitate the conductance of transistor T 1 in response to clock φ 3 , a pre-charge diode DPC is connected between node V 1 and the gate of transistor T 1 to apply V 1 minus V t on the gate of transistor T 1 before charge transfer. Then, any rise of clock φ 3 will cause the immediate conduction of transistor T 1 and accelerate the transfer of residual charge through transistor T 1 .

During pre-charge, the pre-charge diode guarantees pre-charge of gate T 1 , the parallel transistor, without the need for clock phase overlap. Before recovery, since Phi 3 goes low before Phi 1 /Phi 2 clocks switch, gate of T 1 is returned to pre-charge level, which could be slightly higher (initial ramp up phase) or lower (after initial ramp up phase) than after V 1 node fully transfers charge to V 2 , and T 1 could be slightly on or off. In recovery phase, V 2 is coupled high and V 1 is coupled low, and if it is 50/50 transition, the gate of T 1 is a very low capacitive node compared with that of V 1 , V 2 nodes. The gate of TR is at V 2 voltage, which is much higher than gate of T 1 , and the charge on gate of T 1 can be quickly discharged. Even if T 1 could be slightly turned on during the recovery phase, since its gate is discharged to source quickly, it is in weak conduction state, the amount of charge that could potentially leak backward from V 2 to V 1 is a very small percentage of charge transferred. If the recovery phase and clock phases are overlapped, it is more like normal four phase charge pump recovery. By using 50/50 clock phases in recovery, no overlap of clocks is required, the clock can run at faster frequencies and the gain of high frequency is much more significant when compared with any potential loss of charge by leakage during recovery transition.

As noted above, turn on and turn off of transistor T 1 is facilitated by the guaranteed pre-charge of the gate of transistor T 1 to the voltage on node V 1 minus V t prior to turn on, and the equalizing of voltage at the gate of transistor T 1 and the voltage at V 1 in recovery. This guaranteed pre-charging and recovery permits maximum charge transfer forward and minimum charge leakage backward. Moreover, the charge pump can operate with 50% cross over of clocks, or overlap of overlap clocks φ 1 and φ 2 , which is unlike prior art four phase charge pumps which require φ 1 and φ 2 overlap to do both pre-charge and discharge of gate equivalent T 1 transistor. Because charge can be fully transferred by boosted T 1 transistor, without V t drop, capacitance can be reduced per stage to have the same efficiency since no V t drops. The equivalent resistance of T 1 is much smaller due to boosted gate voltage, and the RC delay per stage to fully transfer charge is much smaller compared with the normal Dickson charge pump. Clock frequency can be in creased due to the smaller RC delay, and faster clock frequency can allow even smaller capacitance per stage to be used to meet the same performance. Accordingly, the charge pump in accordance with the invention permits greater efficiency in charge transfer with the same size capacitors as in the prior art Dickson charge pump.

While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention, and is not to be construed limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.