Method of generating protected standard delay format file

1. Field of the Invention

This invention generally relates to a standard delay format (SDF) file, and more particularly, to a method of generating a protected SDF file.

2. Description of Related Art

As the semiconductor manufacturing technology advances, the integrated circuit (IC) becomes the most important electronic devices for all equipment. To simplify the IC design process, a variety of computer aided design (CAD) tools have been developed to aid the designer to design the IC.

FIG. 1 is a typical IC design flow chart. Referring to FIG. 1 , the IC designer will use the high-level language such as Vernlog or VHDL to describe the function of the IC and create the RTL file 110 . The RTL file 110 is then inputted to the synthesizer 120 and is converted into the netlist 140 in the cell level based on the library 130 provided by the semiconductor foundry. The netlist 140 includes the cells for providing the function of the IC and describes the interconnection between those cells for the layout.

To simulate and verify the function of the IC before the IC are manufactured, the IC designers will use the delay calculator 150 based on the netlist 140 and the timing library 160 to generate the SDF file 150 for the simulator 190 to verify. The SDF file 170 generally includes the cell delay description and the interconnect delay description. The cell delay description describes the signal transmission delay data on the cell I/O path. The interconnect delay description describes the signal transmission delay data of the interconnection between the cells. These signal transmission delay data are estimated values before the layout is complete. After the layout is complete, the precise signal transmission delay data can be calculated by referring the extracted RC data 145 from the RC extractor. The extracted RC data 145 is the physical resistor and capacitor data extracted by the RC extractor. Then the simulator 190 outputs the simulation result based on the netlist 140 , the SDF file 170 and the simulation model 180 .

As shown above, the netlist and the SDF file include the data regarding the cells and the interconnection between the cells. If those files are not protected, an unauthorized person can obtain the complete IC design by reverse-engineering. Generally, the netlist can be generated as the binary format for protection. However, the SDF file is represented by ASCII format and cannot be effectively protected.

The present invention is directed to a method of generating a protected SDF file without affecting the simulation result by the simulator.

The present invention is directed to a method of generating a protected standard delay format file, suitable for converting a standard delay format file (e.g., IEEE 1497 SDF file) to a protected standard delay format file. According to an embodiment of the present invention, first, a delay description of the standard delay format file is read. Next, whether or not the delay description is an interconnect delay description is determined, and if the delay description is an interconnect delay description, a delay data of the delay description is integrated into a cell delay description of a cell connected to an interconnect corresponding to the delay description bases on the type of the interconnect.

In an embodiment of the present invention, when the interconnect is an one-to-one interconnect, the delay data of the delay description is integrated into a cell delay description of a driving cell or a driven cell connected to the one-to-one interconnect.

In an embodiment of the present invention, when the interconnect is an multi-to-one interconnect, the delay data of the delay description is integrated into a cell delay description for a driving cell connected to the interconnect.

In an embodiment of the present invention, when the interconnect is an one-to-multi interconnect, the delay data of the delay description is integrated into a cell delay description for a driven cell connected to the interconnect. After integrating the delay data of the delay description into the cell delay description for the driven cell connected to the interconnect, a timing check value of the driven cell is adjusted according to the delay data of the delay description.

In the light of the above, a portion of the interconnect delay description in the SDF file is integrated into the related cell delay description so that the SDF file generated, according to an embodiment of the present invention, can be effectively protected. In addition, regarding the signal path, the delay is still the same. Hence, applying the method of generating a protected file, according to an embodiment of the present invention, will not affect the simulation result.

The above is a brief description of some deficiencies in the prior art and advantages of the present invention. Other features, advantages and embodiments of the invention will be apparent to those skilled in the art from the following description, accompanying drawings and appended claims.

FIG. 1 is a typical IC design flow chart.

FIG. 2 is a flowchart illustrating a method of generating a protected SDF file in accordance with an embodiment of the present invention.

FIG. 3 shows interconnects between a portion of cells in an IC design.

FIG. 4 is a flowchart illustrating a method of generating a protected SDF file in accordance with an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a method of generating a protected SDF file in accordance with an embodiment of the present invention. The SDF file, such as IEEE 1497 SDF file 210 , is inputted into the SDF protector 220 . The SDF protector 220 converts the SDF file 210 to the protected SDF file 230 to prevent an unauthorized person getting access to IC design by reverse-engineering.

FIG. 3 shows interconnects between a portion of cells in an IC design. The SDF file of the IC design in FIG. 3 includes the delay description as follows:

Wherein the delay description including “INTERCONNECT” represents the interconnect delay description. The delay description including “IOPATH”represents the cell delay description of the delay data of different cell 1 /O paths.

In FIG. 3 , the interconnect L 3 between the terminal z of the cell C 1 and the terminal i 1 of the cell C 2 is a one-to-one interconnect. The cell C 1 with respect to L 3 is a driving cell for outputting signal. The cell C 2 is a driven cell for receiving the signal. To the one-to-one interconnect, one can choose to integrate the interconnect delay data into the cell delay description of the driving cell C 1 or the driven cell C 2 connected to the one-to-one interconnect. However, if one chooses to integrate the interconnect delay data into the driven cell C 2 and if the cell C 2 is a sequential logic gate, it will affect the timing check value such as the setup time, the holding time, the recovery time, and the removal time of the cell C 2 . Hence, it requires adjustment of the timing check value of the cell C 2 based on the delay data of the interconnect delay description. Therefore, it would be a better choice to integrate the interconnect delay data into the driving cell C 1 .

In addition, the interconnects L 1 and L 2 from the terminal z of the cell P 1 to the terminal of the cell C 1 and the terminal i 2 of the cell C 2 is a one-to-multi interconnect. To the one-to-multi interconnect, when one chooses to integrate the interconnect delay data into the cell delay description of the cell in the previous stage, if the delays between the interconnects L 1 and L 2 are different, the issue of impreciseness will result. Hence, it would be better to integrate the interconnect delay data into the cell delay description of the cell in the subsequent stage and thus to integrate the interconnect delay data into the cell delay description (IOPATH i z) of the cell C 1 and into the cell delay description (IOPATH i 2 z) of the cell C 2 respectively. Further, it requires adjustment of the timing check value (such as the setup time, the holding time, the recovery time, and the removal time) of the cells C 1 and C 2 . The interconnect delay time should be added to the setup time and the recovery time to prevent the timing check result from being affected. The interconnect delay time should be subtracted from the holding time and the removal time to prevent the timing check result from being affected.

In addition to the above two interconnects, the possible interconnect can be the multi-to-one interconnect and the multi-to-multi interconnect. To the multi-to-one interconnect, there would be no impreciseness issue when choosing to integrate the interconnect delay data into the cell delay description of the cell in the previous stage. Therefore, it is acceptable to integrate the interconnect delay data into the cell delay description of the cell in the previous stage. To the multi-to-multi interconnect, there would always be an impreciseness issue regardless of whether to integrate the interconnect delay data into the cell delay description of the cell in the previous stage or in the subsequent stage. Hence, one can choose the interconnect with a shortest delay, integrate the shortest delay into the cell delay description of the cell in the previous stage or in the subsequent stage, and subtract the shortest delay from the delay of the other interconnects, in order to reduce one interconnect delay description.

According to the principle described above, the delay of the interconnects L 1 (between the terminal z of cell P 1 and the terminal i of cell C 1 ) and L 2 (between the terminal z of cell P 1 and the terminal i 2 of cell C 2 ) can be integrated into the cell delay description (IOPATH i z) of the cell C 1 and the cell delay description (IOPATH i 2 z)of the cell C 2 . The delay of the interconnects L 3 (between the terminal z of cell C 1 and the terminal i 1 of cell C 2 ) can be integrated into the cell delay description (IOPATH i z) of the cell C 1 . Hence, the integrated delay description based on the above example is as follows:

Because the above SDF file lack a portion of interconnect data, it is difficult to obtain the IC design by reverse-engineering. Hence, the IC design can be protected.

FIG. 4 is a flow chart illustrating a method of generating a protected SDF file in accordance with an embodiment of the present invention. In step S 410 , the delay description of the SDF file is read. In step S 420 , whether the SDF file still contains any delay description is determined. If it is determined that the SDF does not contain any delay description, it means that the protected SDF file has been generated. Otherwise, the method proceeds to step S 430 , in which whether the delay description is a one-to-one interconnect delay description or a multi-to-one interconnect delay description is determined.

If the interconnect delay description is determine to be a one-to-one interconnect delay description or a multi-to-one interconnect delay description, i.e., the interconnect is connected to a driving cell and a driven cell or connected to a plurality of driving cells and a driven cell, the method proceeds to step S 440 , in which the delay data of the interconnect delay description is integrated into the cell delay description of the driving cell.

If the delay description is determined to be neither a one-to-one interconnect delay description nor a multi-to-one interconnect delay description, the method proceeds to step S 450 , in which whether the delay description is a one-to-multi interconnect delay description is determined. If it is determined that the delay description is a one-to-multi interconnect, i.e., the interconnect is connected to a driving cell and a plurality of driven cells, the method proceeds to step S 460 in which the delay data of the interconnect delay description is integrated into the cell delay description of the driven cell. Thereafter, in step S 470 , a timing check value of the driven cell is adjusted based on the delay data of the delay description. The interconnect delay time should be added to the setup time and the recovery time to prevent the timing check result from being affected. The interconnect delay time should be subtracted from the holding time and the removal time to prevent the timing check result from being affected.

The above description provides a full and complete description of the preferred embodiments of the present invention. Various modifications, alternate construction, and equivalent may be made by those skilled in the art without changing the scope or spirit of the invention. Accordingly, the above description and illustrations should not be construed as limiting the scope of the invention which is defined by the following claims.