Differential master/slave CML latch

1. Field of the Invention

The present invention relates generally to a differential master/slave latch suitable for use in CMOS phase and frequency detector (PFD) circuits used in the locking of phase locked loops (PLL) and delay locked loops (DLL). This invention relates more specifically to a differential master/slave CML latch.

2. Description of the Related Art

High speed phase locked loops (PLL) are used in modern communication systems for many purposes, including clock generation and data recovery and retiming. Typically, the input signal for the reference input of a PLL is a differential signal where the crossing of the true and complement signals represents the clock transition. However, phase and frequency detector circuits (PFD) used for clock multiplication and generation are typically single-ended circuits. When a differential reference signal is provided to a PFD, either a differential to single phase conversion is done or only one phase of the differential signal is used for the PFD circuit.

It is well known that differential CMOS circuits, especially current mode logic circuits (CML), are generally faster and generate lower noise than single-ended CMOS circuits, but since PFD circuits are single-ended circuits they cannot take advantage of the benefits of differential signaling.

With reference to FIG. 1 , a known PFD architecture is composed of two single-ended, edge triggered D-flip-flops 1 and 3 with asynchronous reset and one AND gate 5 . There exists a complementary but similar architecture using an OR gate. D-flip-flops 1 and 3 are conventionally implemented with CMOS logic circuits, although other implementations with other single-ended logic families using NFETs and PFETS in non-complementary configurations are known.

It is an object of the present invention is to provide a master/slave latch having a differential architecture so that its operation can be performed at the highest possible frequency and with low noise generation.

It is a further object of the present invention to provide differential master/slave latch having an CML architecture.

The above objects are achieved in a phase and frequency detector (PFD) that is fully differential, and is preferably implemented in current mode logic (CML) for high speed operation with low noise generation and higher common mode noise tolerance than voltage based circuits. The PFD of the present invention preferably operates on both a true and complement reference signal (i.e. a reference clock) and true and complement local clock signals simultaneously. To achieve this objective, the present invention provides a fully differential AND gate and two fully differential master/slave latches, or flip-flops.

Preferably, the fully differential AND gate is implemented using a multi-function differential logic gate capable of selectively operation in one of two modes. In a first mode, the multi-function differential logic gate implements simultaneous AND and NAND logic operation. In a second mode, the multi-function differential logic gate implements simultaneous OR and NOR logic operations. Preferably, the multi-function differential logic gate has four inputs grouped into two pairs of logic inputs, with each pair including a logic true and logic complement form of a signal. By electing which of the four inputs are paired together, the multi-function differential logic gate may be made to provide an AND/NAND operation or an OR/NOR operation. Further preferably, the multi-function differential logic gate architecture is suitable for implementation in a CML configuration.

The present invention further preferably provides a fully differential master/slave latch, or flip-flop, circuit. Each flip-flop accepts the true and complement form of an input signal, the true and complement of a clock signal, the true and complement form of a reset signal, and a bias signal for CML support, and provides both true and complement outputs. The flip-flop is divided into a first stage and second stage, with both stages latching input data and tracking input data on opposite phases of the input clock signal. When either stage is tracking input data, their corresponding internal latch is reset and the tracked data is forwarded to their respective true and complement output nodes. When either stage is latching-in and holding data, the latched data is forwarded to their true and complement output nodes while their inputs are disabled. In this manner, when the first stage is tracking input data and forwarding the tracked data to the input of the second stage, the inputs of the second stage are disabled so as to ignore the tracked data from the first stage while the second stage's latched data is forwarded to its output nodes.

Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.

FIG. 1 is a block diagram of a typical phase and frequency detector.

FIG. 2 is a block diagram of a fully differential phase and frequency detector in accord with the present invention.

FIG. 3 is a block diagram of a multi-function differential logic gate in accord with the present invention.

FIG. 4 is a logic diagram of the multi-function differential logic gate of FIG. 3 .

FIG. 5 is a device level diagram of a CML implementation of the multi-function differential logic gate of FIG. 3 .

FIG. 6 is a simplified block diagram of a differential D-flip-flop in accord with the present invention.

FIG. 7 is a more detailed view of the D-flip-flop of FIG. 6 .

FIG. 8 is a device level implementation of a CML implementation of the differential D-flip-flop of FIG. 7 .

FIG. 9 is a graph showing simulation results of the operation of the circuit of FIG. 2 .

Preferred embodiments of the present invention are described below with reference to the accompanying figures.

With reference to FIG. 2 , a fully differential phase and frequency detector, PFD, 20 in accord with the present invention utilizes a fully differential AND gate 21 , and two fully differential D-flip-flops 23 and 25 . In the present embodiment, a fully differential reference clock (i.e. true signal Reference Clock_In and complement signal Reference Clock_In_C) is compared with a fully differential local clock (i.e. true signal Local Clock_In and complement signal Local Clock_In_C). D-flip-flops 23 and 25 also have fully differential UP/UP_C and DOWN/DOWN_C outputs, which are coupled to drive a fully differential charge pump. Such a charge pump is well know, and disclosed, for example, in IEEE JSSC 35:6 p852, which is hereby incorporated in its entirety by reference. Preferably, the differential PFD 20 is implemented in current mode logic, CML, as explained in more detail below, but other differential logic technologies such as low voltage differential signaling, LVDS, may be used.

In general, differential logic devices require two inputs per data logic signal, i.e. a true logic version of a data logic signal and a complement logic version of the data logic signal. Therefore, differential AND gate 21 requires four logic signal inputs (InTrue 1 , InComp 1 , InTrue 2 , and InComp 2 ) to implement the logic operation of a traditional two-input, single-ended AND gate. Furthermore, since the presently preferred embodiment utilizes a CML implementation, differential AND gate 21 also receives a bias signal BIAS to establish its internal operating point, as explained below. Inputs InTrue 1 and InTrue 2 receive true logic signals similar to a two-input, single-ended AND gate, but inputs InComp 1 and InComp 2 receive the logic complements of InTrue 1 and InTrue 2 , respectively. That is, InComp 1 is the logic compliment of InTrue 1 , as indicated by a circle C 1 at input InComp 1 , and circle C 2 indicates that input InComp 2 is the logic compliment of input InTrue 2 .

Differential AND gate 21 also has two outputs, a true output OutT and a complement output OutC, which is the logic compliment of OutT and is visually indicated by circle C 3 . OutT outputs the logic AND operation of true inputs InTrue 1 and InTrue 2 , and consequently OutC outputs the logic NAND operation of true inputs InTrue 1 and InTrue 2 .

Differential D-flip-flops 23 and 25 have similar inputs, and operate similarly. Both have a true logic input D and a complement logic input D_C, a true clock input CLOCK and a complement clock input CLOCK_C, a true reset input RESET and a complement reset input RESET_C, a true output node OUTPUT and a complement output node OUTPUT_C. As stated above, the present differential PFD is preferably implemented as a current mode logic circuit, and thus D-flip-flops 23 and 25 further receive input BIAS, which controls the operating point of a respective, internal current source more fully explained below. Also, logic high CML level (UP LEVEL) signals are applied to the D inputs of D-flip-flops 23 and 25 and logic low CML level (DOWN LEVEL) signals are applied to the complement inputs D_C of D-flip-flops 23 and 25 .

In operation, each differential D-flip-flop latches in its true D and complement D_C data inputs at the rising edge of its true clock input CLOCK, and simultaneously transfers the latched true and complement data to true output node OUTPUT and complement output node OUTPUT_C, respectively. Equivalently, D-flip-flops 23 and 25 may latch in their true D and complement D_C inputs at the falling edge of their complement clock inputs CLOCK_C, and simultaneously transfer the latched data to their respective output nodes OUTPUT and OUTPUT_C. D-flip-flops 23 and 25 function as described above as long as their input RESET is low and complement input RESET_C is high. If input RESET is raised high and input RESET_C is consequently brought low, then the D-flip-flop will reset its true output OUTPUT to a logic low and set its complement output OUTPUT_C to a logic high irrespective of the state of all other inputs.

It is to be understood that although this is a differential circuit, the rising edge of a signal may be defined as the rising of the signal voltage above its complement signal voltage. Or in other words, the difference between true and complement signal going from negative to positive. The falling edge may be defined as the falling of a signal voltage below its complement signal voltage. Or in other words, the difference between true and complement signal going from positive to negative. Since the present embodiment is implemented in CML logic, transitions between logic high and logic low levels of the true and complement signals do not correspond to voltage swings from a first power rail to a second power rail. Rather, logic transition may correspond to transitions between a first voltage level, such as the first power rail, for example, to an intermediate voltage level determined by its bias current, pull-up resistor, and the first power rail.

Differential AND gate 21 is preferably implemented using a multi-function differential logic gate 21 ′, as shown is FIG. 3 . Differential logic gate 21 ′ has four inputs A–D and two outputs O 1 and O 2 . Depending on how inputs A–D are used, differential logic gate 21 ′ may be made to function as a differential AND gate or a differential OR gate. Preferably, inputs A–D are divided into two differential signal groups, each having two inputs. Each differential signal group consists of a true signal and its logic complement. Either input in each group may be designated the true signal, and the other input in the group is thus defined as its logic complement. By assuring that one signal in each group receives a true signal and the other receives its logic complement, the logical function of differential logic gate 21 ′ may be switched from that of a differential AND gate to that of a differential OR gate without requiring any alterations to the internal structure of multi-function, differential logic gate 21 ′.

In the present example, inputs A and B constitute one signal group and inputs C and D constitute a second signal group. If input A is designated the true input in the first group and input C is designate the true input in the second group, then first output O 1 will be designated the true output producing the logical function A AND_C and second output O 2 will be designated the complement output producing the logical function A NAND_C. However, if input B is designated the true input in the first group and input D is designate the true input in the second group, then second output O 2 will be designated the true output producing a logical function B OR D and first output O 1 will be designated the complement output producing a logical function B NOR D.

With reference to FIG. 4 , a logic level implementation of multi-function differential logic gate 21 ′ includes a single-ended NAND gate 31 and a single-ended NOR gate 33 . The present implementation assumes, as in the above discussion, that inputs A and B are form the first signal group and inputs C and D form the second input group. Thus, input A is coupled to a first input of NAND gate 31 and input B is coupled to a first input of NOR gate 33 . Similarly, input C is coupled to the second input of NAND gate 31 and input D is coupled to the second input of NOR gate 33 . The output of NOR gate 33 is coupled to first output O 1 and the output of NAND gate 31 is coupled to second output O 2 .

If one assumes that multi-function differential logic gate 21 ′ is to be implemented as a differential AND gate, then inputs A and C are designated the true inputs and inputs B and D are designated the complement inputs. Basically, this means that inputs A and C are used as the customary inputs of a single-ended AND gate, and inputs B and D must receive logic complements of inputs A and C, respectively. Thus, when input A receives a logic high, input B must receive a logic low, and when input A receives a logic low, then input B must receive a logic high. Also, when input C receives a logic high, input D must receive a logic low, and when input C receives a logic low, input D must receive a logic high. For example, if inputs A and C both receive logic high signals, meaning that inputs B and D both receive logic low signals, then the output of NAND 31 will be low and the output of NOR gate 33 will be high, which produce the expected logic levels at outputs O 1 and O 2 for a differential AND gate. The truth table for this operation is summarized below, where inputs A and C, and their complements B and D are grouped to separately for ease of explanation.

On the other hand, if one assumes that multi-function differential logic gate 21 ′ is to be implemented as a differential OR gate, then inputs B and D are designated the true inputs and inputs A and C are designated the complement inputs. Therefore, inputs B and D are used as the customary inputs of a single-ended OR gate, and inputs A and C receive logic complements of inputs B and D, respectively. Thus, when input B receives a logic high, input A must receive a logic low, and when input B receives a logic low, then input A must receive a logic high. Also, when input D receives a logic high, input C must receive a logic low, and when input D receives a logic low, input C must receive a logic high. The truth table for this operation is summarized below, where inputs B and D, and their complements A and C are grouped separately for ease of explanation.

A transistor level, current mode logic (CML) implementation of the structure of FIG. 4 is shown in FIG. 5 . Transistor 41 functions as a current source controlled by signal BIAS, and establishes the operating point for multi-function, differential logic gate 21 ′. That is, transistor 41 is biased by a DC signal BIAS into saturation to form a constant current source. The current through transistor 41 is shunted through either of load resistors 51 or 53 depending on the values of inputs A and C and their corresponding logic complements B and D.

As it is known in the art, CML logic circuits operate by steering current along different paths from one power rail 40 , to a second power rail 50 . The direction taken by the current path determines the logic level of a signal. When the direction of a current path is changed, typically at least one node will drop in potential to a CML logic low level while another will rise to a CML logic high level. Unlike voltage based circuits, CML logic levels do not swing their outputs from first to second power rails. Rather, CML circuits typically swing their outputs from a first power rail to an intermediate voltage determined by the bias current, pull-up resistor, and first power rail. Nonetheless, by identifying the direction of the shift in potential of two nodes, one can determine the direction of the current path and thereby the logic level being conveyed. Since logic levels are determined by identifying the direction of a current path, as opposed to the rising and lowering of a single node potential to predefined voltage levels (as is done in more traditional, single-ended, voltage based circuits), current mode logic can transfer information at higher speeds with lower noise generation and higher common mode noise tolerance than voltage based circuits.

Resistor 51 and series connected transistors 43 and 45 implement a NAND function, such as NAND gate 31 of FIG. 4 . If either of inputs A or C is at a logic low, then the current path from node n 2 to second power rail 50 will be cut-off and resistor 51 will raise node n 2 , and by direct extension raise output O 2 , toward the higher power rail 40 to a CML logic high level. The actual voltage level on O 2 is determined by the amount of load current drawn through resistor 51 . Simultaneously at least one of inputs B or D, which receive the logic complements of inputs A and C, will have a logic high and establish a current path from node n 1 through either of transistor pairs 47 / 47 ′ or 49 / 49 ′ to the second power rail 50 , i.e. ground, through current source 41 . As a result, the current from node n 1 is steered through node n 3 and current source 41 toward ground 50 , and node n 1 is brought to a CML logic low voltage level. This low voltage value is determined by the voltage divider of resistor 53 and the resistances of active transistors in the pull-down path, 47 / 47 ′ and 41 or 49 / 49 ′ and 41 .

Conversely, if both of inputs A and C are at a logic high, meaning that both of inputs B and D are at logic low, then transistors 43 and 45 will be ON while both of transistor pairs 47 / 47 ′ and 49 / 49 ′ would be OFF. Therefore, the current path at node n 3 will be steered away from node n 1 to node n 2 , and establish a logic low at node n 2 and output O 2 . Consequently, node nil is pulled high by resistor 53 and thereby places a logic high on node nil and output O 1 .

Since both transistors in each of series connected transistor pairs 47 / 47 ′ and 49 / 49 ′ are coupled together to their respective control input, B or D, it is to be understood that both transistors in each pair function in unison. Two transistors per input B and D are preferred in order to more easily maintain a load balance with transistors 43 and 45 , and thereby ensure that the low level of O 1 is the same as the low level of O 2 . However, each transistor pair could be replaced with a single large transistor whose impedance balances that of transistors 43 and 45 .

Resistor 53 along with transistor pairs 47 / 47 ′ and 49 / 49 ′ implement a NOR function similar to NOR gate 33 of FIG. 4 . If either of inputs B or D is at a logic high, then a current path from node n 1 to ground 50 via node n 3 and current source 41 will be established, and output O 1 will be brought to a logic low. Simultaneously, at least one of inputs A or C will have received a logic low (the logic complement), and thus cut-off the current path from node n 2 to ground 50 . Therefore, resistor 51 will raise node n 2 , and consequently output O 2 , to a logic high level. However, if both of input B and D are at a logic low and both of inputs A and C are at a logic high, then transistor pairs 47 / 47 ′ and 49 / 49 ′ will be turned OFF while transistors 43 and 45 will be turned ON. Consequently, the current path from node n 1 to ground 50 will be cut-off while the current path from node n 2 to ground 50 is established. As a result, resistor 53 will raise node n 1 toward the higher power potential 40 while node n 2 is lowered toward ground 50 . This places a logic high on output O 1 and a logic low on output O 2 , as expected.

With reference to FIG. 6 , a CML implementation of differential D-flip-flop 23 is divided into a first stage STG 1 and a second stage STG 2 . For ease of explanation, stages STG 1 and STG 2 are shown separated by a vertical dotted line 60 . It is to be understood that differential D-flip-flop 25 is substantially similar to D-flip-flop 23 , and the present explanation of D-flip-flop 23 is therefore equally applicable to D-flip-flop 25 .

First stage STG 1 and second stage STG 2 latch in, and hold, data during opposite phases of the true clock's cycle. Preferably, first stage STG 1 tracks input data during the low phase of true clock signal CLOCK, latches in the tracked input data on the rising edge of signal CLOCK and holds the latched data during the logic high phase of the signal CLOCK. Also preferably, second stage STG 2 latches in the held data from stage STG 1 at the falling edge of true clock signal CLOCK, holds and outputs its latched data during the low phase of signal CLOCK, and tracks and transfers to its output latched data from STG 1 during the high phase of signal CLOCK. It is to be understood that this is purely a preference and that the response of the first STG 1 and second STG 2 stages to the high and low phases of the true clock signal's cycle may be reversed without deviating from the present invention.

As explained above in reference to FIG. 2 , D-flip-flop 23 latches in input data on the rising edge of true clock signal CLOCK and simultaneously outputs valid data. Also, D-flip-flop 23 preferably tracks input data at input nodes D and D_C while complementary clock signal CLOCK_C is high (and true clock signal CLOCK is therefore low), and tri-states its inputs D and D_C (i.e. stops tracking input data signals at nodes D and D_C) when complementary clock signal CLOCK_C is low (meaning that true clock signal CLOCK has risen high and has therefore latched in any previously tracked data at inputs D and D_C).

In reference to first stage STG 1 , true input D and complementary input D_C are applied to respective input amplifiers INPT 1 and INPT 2 . Each input amplifier, INPT 1 and INPT 2 , is turned off, or tri-stated, in response to a control line 61 . When an input amplifier is enabled, i.e. not turned off or tri-stated, it will output an amplified representation of an applied input signal. In the present case, input amplifiers INPT 1 and INPT 2 are preferably inverting amplifiers and thus produce an inverted representation of data signals applied at their respective inputs, D and D_C. It is to be understood that inverting input amplifiers INPT 1 and INPT 2 may be digital inverters, or NOT gates, in which case their outputs will be digital signals whose values are the logical inverse of their input signals.

It is further preferred that control line 61 be the grounding line of inverting input amplifiers INPT 1 and INPT 2 . In this manner, input amplifiers INPT 1 and INPT 2 may be enabled and disabled by respectively coupling and decoupling control line 61 to, and from, current source M 7 and ground 50 . Current source M 7 is preferably implemented as a transistor under the control of signal BIAS for establishing the operating point for first stage STG 1 of D-flip-flop 23 . By using grounding line 61 as a control input for input amplifiers INPT 1 and INPT 2 , the enabling and disabling of input amplifiers INPT 1 and INPT 2 can be easily controlled by complementary clock signal CLOCK_C, which selectively couples and decouples line 61 to and from current source M 7 and ground 50 by use of a first switch SW 1 . It is to be understood that switch SW 1 may be a transmission gate or any type of current switching device, such as a single-transistor current pass device.

Pull-up resistors, or load resistors, R 1 and R 2 are coupled to the respective outputs 67 and 69 of input amplifiers INPT 1 and INPT 2 . It is to be understood that input inverters INPT 1 and INPT 2 are sized such that when they are enabled, they are capable of pulling high or pulling low their respective outputs 67 and 69 irrespective of the pull-up tendency of respective pull-up resistors R 1 and R 2 . That is, the size of pull-up resistors R 1 and R 2 and the current draining strengths of input amplifiers INPT 1 and INPT 2 are chosen such that pull-up resistors R 1 and R 2 do not pose too high a burden on the ability of input amplifiers INPT 1 and INPT 2 to pull low their respective outputs 67 and 69 . However, when input amplifiers INPT 1 and INPT 2 are disabled, i.e. tri-stated, pull-up resistors R 1 and R 2 are effective for pulling high output nodes 67 and 69 , unless they are pulled low by another device as explained below.

The outputs of input amplifiers INPT 1 and INPT 2 are coupled to two cross-coupled inverting amplifiers XINV 1 and XINV 2 , which comprise a latching circuit. Specifically, output 67 from input inverter INPT 1 is coupled to the input of cross-coupled inverting amplifier XINV 1 and to the output of cross-coupled inverting amplifier XINV 2 . Similarly, output 69 from input inverter INPT 2 is coupled to the input of XINV 2 and to the output of XINV 1 . It is to be understood that inverting amplifiers XINV 1 and XINV 2 may be logic inverters. Preferably, inverting amplifiers XINV 1 and XINV 2 are selectively enabled and disabled (i.e. tri-stated) by means of control line 71 . Like in the case of input amplifiers INPT 1 and INPT 2 , it is preferred that control line 71 be a grounding path for inverting amplifiers XINV 1 and XINV 2 , and the enabling and disabling of XINV 1 and XINV 2 is accomplished by the coupling and decoupling of grounding line 71 to and from current source M 7 and ground 50 . In the present case, grounding line 71 must pass through two stitches, SW 2 and SW 4 , to reach current source M 7 and ground 50 . Thus, XINV 1 and XINV 2 are enabled and capable of latching in data only when both switches SW 2 and SW 4 are closed, i.e. actuated.

Switch SW 2 is controlled by complement signal RESET_C, which is high when D-flip-flop 23 is not being reset. Thus, complement signal RESET_C is normally high during normal operation of D-flip-flop 23 , and switch SW 2 is closed when D-flip-flop is not being reset.

Switch SW 4 is controlled by the true clock signal, CLOCK. Therefore, control line 71 is coupled to ground 50 (and latching inverting amplifiers XINV 1 and XINV 2 are enabled) when signal CLOCK is high and D-flip-flop 23 is not being reset. Therefore during normal use, XINV 1 and XINV 2 actively latch in any data applied at their inputs via lines 67 and 69 when signal CLOCK is transitions to a high state, and are disabled when signal CLOCK is low.

When signal CLOCK is low, latching amplifiers XINV 1 and XINV 2 are disabled and lose any previously latched data. During this time, complementary signal CLOCK_C is high causing input amplifiers INPT 1 and INPT 2 to be enabled and track any input data at their respective input nodes D and D_C. Since INPT 1 and INPT 2 are enabled, they actively output and apply data to disabled inverters XINV 1 and XINV 2 along lines 67 and 69 , which are also the outputs of STG 1 coupled to the inputs of STG 2 . When complementary signal CLOCK_C goes low, thereby disabling input inverters INPT 1 and INPT 2 , true signal CLOCK goes high and enables XINV 1 and XINV 2 permitting them to latch in the previously tracked data. The enabling of XINV 1 and XINV 2 causes them to latch in any data at their input lines 67 and 69 . This data is held, and transferred across dotted line 60 to the inputs of the second stage STG 2 .

The outputs of XINV 1 and INPT 2 , at line 69 , are further selectively coupled to SW 4 via switch SW 3 , which is responsive to the true reset signal, RESET. True signal RESET is typically low and is raised high only to reset the data latched in XINV 1 and XINV 2 to known values. If true signal RESET is asserted, i.e. brought high, while signal CLOCK is low, it will not have much effect on the data contents of XINV 1 and XINV 2 since inverters XINV 1 and XINV 2 will already have been disabled by the opening of switch SW 4 due to signal CLOCK being low. During this period, complementary clock signal CLOCK_C is high and input amplifiers INPT 1 and INPT 2 actively track any data at inputs D and D_C. However, second stage STG 2 responds to signal RESET to assure that outputs OUTPUT and OUTPUT_C are set to known reset levels irrespective of the state of CLOCK/CLOCK_C, as is explained below.

If true signal RESET is asserted while signal CLOCK is high, a current path will be established from line 69 to ground 50 through switches SW 3 and SW 4 and through transistor M 7 . Furthermore, since signal RESET is high, complementary signal RESET_C will be low meaning that inverting amplifiers XINV 1 and XINV 2 will be tri-stated while input amplifiers INPT 1 and INPT 2 are also tri-stated by the low level of signal CLOCK_C. As a result, line 69 can be quickly pulled down to a known logic low level by the current path from line 69 through SW 3 , SW 4 and transistor M 7 , while line 67 can be quickly pulled high to a known logic high level by pull-up resistor R 1 . When signal RESET is de-asserted (i.e. brought low) and signal RESET_C goes high and enables the latching action of the XINV 1 and XINV 2 , the known logic low of line 69 and the known high of line 67 will be latched in (assuming that signal CLOCK is high).

Since the true and complement signals applied to input node D and D_C, respectively, were inverted by input amplifiers INPT 1 and INPT 2 , respectively, the outputs of the first stage STG 1 are crossed as they pass dotted line 60 to second stage STG 2 . This assures that true input D′ of the second stage STG 2 receives the latched true data signal, and that complement input D_C′ of STG 2 receives the complement data signal. By so doing, the structure of the second stage STG 2 may be maintain substantially similar to that of the first stage STG 1 , with the exception of the application of control signals CLOCK and CLOCK_C, which are reversed to ensure that the second stage STG 2 operates in opposite phase to the first stage STG 1 . All elements in stage STG 2 similar to those of stage STG 1 are therefore identified by similar reference characters as those of STG 1 with the addition of a prime symbol [′], and are thus explained above.

In stage STG 1 , signal CLOCK is applied to switch SW 4 to control the enabling and disabling of the internal latch comprised of XINV 1 and XINV 2 , while complement signal CLOCK_C is applied to switch SW 1 to control the enabling and disabling of input data tracking components INPT 1 and INPT 2 . By contrast in STG 2 , signal CLOCK is applied to switch SW 1 ′ to control the enabling and disabling of input data tracking components INPT 1 ′ and INPT 2 ′, while complement signal CLOCK_C is applied to switch SW 4 ′ to control the enabling and disabling of the internal latch comprised of XINV 1 ′ and XINV 2 ′.

In this manner, control signals CLOCK and CLOCK_C within STG 2 are arranged such that while the first stage STG 1 is tracking data at its inputs D and D_C and has its internal latch (XINV 1 ′/XINV 2 ) disabled, the second stage STG 2 has its input tracking components (INV 1 ′/INV 2 ′) disabled and its internal latch (XINV 1 ′/XINV 2 ′) enabled. Therefore, stage STG 2 outputs latched data while stage STG 1 tracks new input data. Similarly, when the first stage STG 1 has its input tracking components disabled and its internal latch enabled to transfer its latched data to STG 2 , the second stage STG 2 has its internal latch disabled but has its input tracking components enabled to accept (and transfer to outputs OUTPUT/OUTPUT_C) the latched data from the stage STG 1 . In this manner, D-flip-flop 23 latches in data at inputs D and D_C at the rising edge of signal CLOCK and holds the latched value of the data on output nodes OUTPUT and OUTPUT_C of STG 2 .

In the above discussion, it is to be understood that switches SW 1 to SW 4 and switches SW 1 ′ to SW 4 ′ may be implemented as transmission gates or any other type of current passing control device. In the presently preferred embodiment of FIG. 7 , switches SW 1 , SW 2 , SW 3 , SW 4 , SW 1 ′, SW 2 ′, SW 3 ′, and SW 4 ′ of FIG. 6 are respectively implemented as NMOS transistors M 3 , M 21 , M 19 , M 6 , M 8 , M 13 , M 15 , and M 17 . As shown, the current path from control line 71 to transistor M 7 and ground 50 passes through two NMOS transistors, either though M 21 and M 6 or through M 19 and M 6 . However in the structure of FIG. 6 , control line 61 passed through only one switch, SW 1 , to reach transistor M 7 and ground 50 . To balance the current steering operation of STG 1 , an additional NMOS transistor M 18 with its gate coupled to the higher power rail is inserted between control line 61 and transistor M 3 . In this manner, the current path from control line 61 to transistor M 7 and ground 50 also passes through two NMOS transistors, i.e. M 18 and M 3 , and balances the current path from control line 71 to transistor M 7 and ground 50 . Similarly in STG 2 , an additional NMOS transistor M 10 with its gate coupled to the high power rail in an always ON configuration is inserted between control line 61 ′ and transistor M 8 to balance the current path from control line 71 to transistor M 9 and ground 50 .

With reference to FIG. 8 , a transistors level implementation of the structure of FIG. 7 incorporates resistors R 1 , R 2 , R 1 ′, and R 2 ′ into the construct of amplifiers INPT 1 , INPT 2 , XINV 1 , XINV 2 , INPT 1 ′, INPT 2 ′, XINV 1 ′ and XINV 2 , as explained more fully below. All elements similar to those of FIG. 7 are identified by similar reference characters and are described above.

In the present embodiment, pull-up resistor R 1 is incorporated into the construct of input amplifier INPT 1 and inverting amplifier XINV 2 . Input amplifier INPT 1 is thus comprised of transistor M 0 coupled to R 1 , with the input node of amplifier INPT 1 being the control gate electrode of M 0 and the output of INPT 1 being the drain electrode of M 0 . Similarly, inverting amplifier XINV 2 is comprised of transistor M 5 couple to R 1 , with the input of inverting amplifier XINV 2 being the control gate electrode of M 5 and the output of XINV 2 being the drain electrode of M 5 .

Pull-up resistor R 2 is incorporated into the construct of input amplifier INPT 2 and inverting amplifier XINV 1 . Input amplifier INPT 2 is thus comprised of transistor M 2 coupled to R 2 , with the input node of amplifier INPT 2 being the control gate electrode of M 2 and the output of INPT 2 being the drain electrode of M 2 . Similarly, inverting amplifier XINV 1 is comprised of transistor M 1 couple to R 2 , with the input of inverting amplifier XINV 1 being the control gate electrode of M 1 and the output of XINV 1 being the drain electrode of M 1 .

In like manner, pull-up resistor R 1 ′ is incorporated into the construct of input amplifier INPT 1 ′ and inverting amplifier XINV 2 ′. Input amplifier INPT 1 ′ is comprised of transistor M 4 coupled to R 1 ′, with the input node of amplifier INPT 1 ′ being the control gate electrode of M 4 and the output of INPT 1 ′ being the drain electrode of M 4 . Similarly, inverting amplifier XINV 2 ′ is comprised of transistor M 12 couple to R 1 ′, with the input of inverting amplifier XINV 2 ′ being the control gate electrode of M 12 and the output of XINV 2 ′ being the drain electrode of M 12 .

Lastly, pull-up resistor R 2 ′ is incorporated into the construct of input amplifier INPT 2 ′ and inverting amplifier XINV 1 ′. Input amplifier INPT 2 ′ is comprised of transistor M 11 coupled to R 2 ′, with the input node of amplifier INPT 2 ′ being the control gate electrode of M 11 and the output of INPT 2 ′ being the drain electrode of M 11 . Similarly, inverting amplifier XINV 1 ′ is comprised of transistor M 14 couple to R 2 ′, with the input of inverting amplifier XINV 1 ′ being the control gate electrode of M 14 and the output of XINV 1 ′ being the drain electrode of M 14 .

It is further noted that in this configuration another transistor M 20 in an always on configuration is needed between transistors M 19 and M 6 to achieve a balanced circuit in STG 1 , and another transistor M 16 in an always on configuration is needed between transistors M 15 and M 17 to achieve a balanced circuit in STG 2 .

As explained above, D-flip-flop 23 is composed of a master/slave pair, embodied as STG 1 and STG 2 , of differential master slave clocked latches. The external BIAS voltage provides the voltage to transistors M 7 and M 9 to generate two constant current sources, one per latch.

The first stage STG 1 , which embodies the first latch, is comprised of transistors M 0 , M 2 , M 19 , M 5 , M 1 , M 18 , M 20 , M 21 , M 3 , M 6 , and M 7 along with pull-up resistors R 1 and R 2 , and operates as the master as follows. During the up level of CLOCK_C, the values of the data input D and D_C are tracked by M 0 and M 2 respectively. This tracking sources the current for M 7 from either of resistor R 1 R 2 through either M 0 or M 2 and M 18 and M 3 . It is to be understood that resistors R 1 and R 2 may be combined into a single resistor R, and resistors R 1 ′ and R 2 ′ may also be combined into resistor R, or another single resistor. Presently, the value tracked is set into M 1 and M 5 at the rising edge of CLOCK through M 6 as long as M 21 is on. M 21 will be on if there is no reset and RESET_C is high. Any time when CLOCK is high, the assertion of RESET will break the cross-coupled memory in M 5 and M 1 since M 21 will go off and M 19 and M 20 will be on causing the data value in the first latch to reset.

The second stage STG 2 , which embodies the second latch, is comprised of transistors M 4 , M 11 , M 15 , M 12 , M 14 , M 10 , M 16 , M 13 , M 8 , M 17 and M 9 along with resistors R 1 ′ and R 2 ′, and operates as the slave as follows. The data held in the first latch (from stage STG 1 ) is tracked during the actuation of signal CLOCK by M 4 and M 11 and transferred to the outputs OUTPUT and OUTPUT_C. The value is held by M 12 and M 14 during the CLOCK_C phase of the clock as long as the RESET is not high and RESET_C is high. Note that at any time when CLOCK_C is high, RESET going high will immediately reset the outputs via M 13 and M 15 and M 16 . When CLOCK is high and CLOCK_C is low, the first latch of STG 1 is reset and its reset values immediately transferred to output nodes OUTPUT and OUTPUT_C of STG 2 . Thus whenever a reset operation occurs, the OUTPUT and OUTPUT_C values will be reset, i.e. OUTPUT will be low and OUTPUT_C high, irrespective of the state of signals CLOCK and CLOCK_C.

With reference to FIG. 9 , simulation results of the circuit of FIG. 2 when operating at 2.5 GHz input clock rates shows it to have a high speed of operation and good linearity. The relative phase differences of the two inputs are expressed in psec where 400 psec represent a complete period or a phase shift of 2π radians. The output characteristic is expressed as the difference in pulse widths between the UP and DOWN outputs in psec.

The present invention has been described in connection with various preferred embodiments thereof with reference to the accompanying drawings. However, various changes and modifications will be apparent to those skilled in the art based on the foregoing description. Such changes and modifications are intended to be included within the scope of the present invention to the extent they fall within the scope of the appended claims.