A solid-state image sensing apparatus of an aspect of this invention can appropriately correct the black level of a video signal even when a high-luminance state or spotlight exists. The apparatus includes an effective pixel unit to receive object light, and a light-shielded light-shielded pixel unit to output an optical black level equivalent signal. In addition to the output from the effective pixel unit, one of the output from the light-shielded pixel unit and a predetermined reference voltage is selectively output.

Description

17 parts

›CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-110436, filed Apr. 15, 2003, the entire contents of which are incorporated herein by reference.

›BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a solid-state image sensing apparatus which has, e.g., an effective signal photoelectric conversion unit and a light-shielded reference signal photoelectric conversion unit to output a black level equivalent signal, and corrects the signal output level of the effective signal photoelectric conversion unit on the basis of the output signal from the reference signal photoelectric conversion unit.

2. Description of the Related Art

Conventionally, in image sensing using a solid-state image sensing apparatus, the pixel output variation at the time of reset must be corrected. To do this, correlated double sampling (CDS) is executed. In addition, to make the black level of a video signal constant, an error signal (dark current component) generated by a dark current must be subtracted from the video signal. To detect the dark current component, the output signal from a light-shielded pixel (optical black [OB] signal) is referred to.

However, in sensing a scene having extremely high luminance as a whole or a scene containing a high-luminance light source such as a spotlight, the OB signal level may vary. If black level correction is done by using the varying OB signal, the video signal may be inappropriate. There is a conventional technique-related to an image sensing apparatus (Jpn. Pat. Appln. KOKAI Publication No. 2002-290841). In this prior art, OB regions are prepared at a plurality of points near the effective pixel region including light-receiving elements which are arrayed on the light-receiving surface and generate pixel signals. Pixel signals are read out from both regions, thereby preventing any partial decrease in level of the pixel signals after black level correction.

Patent reference 1 above discloses several techniques for coping with the above-described situation, though none of them can solve the problem practically.

›BRIEF SUMMARY OF THE INVENTION

The present invention has been made in consideration of the above technical problem, and has as its object to provide a solid-state image sensing apparatus which can appropriately correct the black level of a video signal even when a high-luminance state or spotlight exists.

In order to achieve the above object, according to an aspect of the present invention, there is provided a solid-state image sensing apparatus comprising an effective signal photoelectric conversion unit to receive object light, and a light-shielded reference signal photoelectric conversion unit to output an optical black level equivalent signal, wherein in addition to an output from the effective signal photoelectric conversion unit, one of an output from the reference signal photoelectric conversion unit and a predetermined reference voltage is selectively output.

Advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.

›BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING · 1 of 2

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention, and together with the general description given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

FIG. 1 is a view showing the arrangement of a solid-state image sensing apparatus according to the first embodiment of the present invention;

FIG. 2A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the first embodiment;

FIG. 2B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when-very strong light is incident, in the solid-state image sensing apparatus according to the first embodiment;

FIG. 3 is a view showing the arrangement of a solid-state image sensing apparatus according to the second embodiment of the present invention;

FIG. 4A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the second embodiment;

FIG. 4B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the second embodiment;

FIG. 5 is a view showing the arrangement of a solid-state image sensing apparatus according to the third embodiment of the present invention;

FIG. 6A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the third embodiment;

FIG. 6B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the third embodiment;

FIG. 7 is a view showing the arrangement of a solid-state image sensing apparatus according to the fourth embodiment of the present invention;

FIG. 8A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the fourth embodiment;

FIG. 8B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the fourth embodiment;

FIG. 9 is a view showing the arrangement of a solid-state image sensing apparatus according to the fifth embodiment of the present invention;

FIG. 10A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the fifth embodiment;

FIG. 10B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the fifth embodiment;

FIG. 11 is a view showing the arrangement of a solid-state image sensing apparatus according to the sixth embodiment of the present invention;

FIG. 12A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the sixth embodiment;

FIG. 12B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the sixth embodiment;

FIG. 13A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the seventh embodiment;

FIG. 13B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the seventh embodiment;

FIG. 14A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the eighth embodiment;

FIG. 14B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the eighth embodiment;

FIG. 15A is a timing chart of a read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the ninth embodiment;

FIG. 15B is a timing chart of a read operation for a reference signal different from the output signal from the light-shielded pixel unit 1 , which is used when very strong light is incident, in the solid-state image sensing apparatus according to the ninth embodiment;

FIG. 16 is a block diagram showing the arrangement of a camera according to the 10th embodiment of the present invention;

FIG. 17 is a view showing an erect object image;

FIG. 18 is a flowchart for explaining details of the first operation example of the camera according to the 10th embodiment of the present invention; and

›BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING · 2 of 2

FIG. 19 is a flowchart for explaining details of the second operation example of the camera according to the 10th embodiment of the present invention.

›DETAILED DESCRIPTION OF THE INVENTION · 1 of 12

The embodiments of the present invention will be described below with reference to the accompanying drawing.

In a solid-state image sensing apparatus according to an embodiment of the present invention, to process CDS and black clamp, a pixel signal or a reference signal (reference voltage) from light-shielded pixels in a reference signal photoelectric conversion unit (light-shielded pixel unit) can be selectively output. Under a high-luminance condition, a reference level signal is output in place of a pixel signal from the light-shielded pixels. Each embodiment will be described below in detail based on the above-described characteristic feature.

(First Embodiment)

FIG. 1 shows the arrangement of a solid-state image sensing apparatus according to the first embodiment of the present invention. This will be described.

Referring to FIG. 1 , reference symbols PIX 11 to PIX 33 denote pixels arrayed in a matrix. Of the pixels PIX 11 to PIX 33 , the pixels PIX 11 to PIX 13 form a light-shielded pixel unit 1 . The pixels PIX 21 to PIX 23 and PIX 31 to PIX 33 form an effective pixel unit 2 . The surfaces of the pixels in the light-shielded pixel unit 1 are covered with a light-shielding film such as an aluminum film.

The light-shielded pixel unit 1 functions as a unit which outputs a signal corresponding to the black level. The effective pixel unit 2 functions as a unit which receives object light and generates charges.

A vertical scanning circuit 3 sequentially scans row lines H 1 to H 3 to sequentially read out pixel signals from the light-shielded pixel unit 1 and effective pixel unit 2 . Reference symbols φV 1 to φV 3 in the vertical scanning circuit 3 denote row select signals. A noise suppressing circuit 4 suppresses noise components in pixel signals sent from the light-shielded pixel unit 1 and effective pixel unit 2 through vertical signal lines V 1 to V 3 .

Transistors M 31 to M 33 indicate horizontal select switches to select and read out pixel signals from the noise suppressing circuit 4 (these transistors will be referred to as “horizontal select switches” hereinafter). The gates of the horizontal select switches M 31 to M 33 are connected to the output terminals of a horizontal scanning circuit 5 for column select signals φH 1 to φH 3 .

The horizontal scanning circuit 5 sequentially drives the horizontal select switches M 31 to M 33 . Reference symbols φH 1 to φH 3 in the horizontal scanning circuit 5 denote column select signals. An output amplifier 6 amplifies the output signal from the noise suppressing circuit 4 , which is sent through the horizontal select switches M 31 to M 33 . Although lines other than the row lines H 1 to H 3 and vertical signal lines V 1 to V 3 are also connected to the pixels PIX 11 to PIX 33 , for descriptive convenience, they are not illustrated.

The output signal read operation of the solid-state image sensing apparatus according to the first embodiment of the present invention will be described below with reference to the timing charts shown in FIGS. 2A and 2B .

In the vertical scanning circuit 3 , the light-shielded pixel PIX 11 and the effective pixels PIX 21 and PIX 31 are selected by the row select signal φV 1 of “H” level. The pixel signals are input to the noise suppressing circuit 4 through the vertical signal lines V 1 to V 3 so that pixel signals with suppressed noise are obtained. At this time, the pixel signal components of the light-shielded pixel PIX 11 and the effective pixels PIX 21 and PIX 31 are held in CDS 1 to CDS 3 of the noise suppressing circuit 4 . After that, the horizontal scanning circuit 5 sequentially outputs the column select signals φH 1 to φH 3 of “H” level. Accordingly, the pixel signal components of the light-shielded pixel PIX 11 and the effective pixels PIX 21 and PIX 31 , which are stored in the noise suppressing circuit 4 , are read out through the horizontal select switches M 31 , M 32 , and M 33 in the time-series order and output through the output amplifier 6 . In this example, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the signal output level of the light-shielded pixel PIX 11 .

At this time, a reference signal component which is different from the pixel signal component of the light-shielded pixel PIX 11 is held in CDS 1 of the noise suppressing circuit 4 . The pixel signal components of the effective pixels PIX 21 and PIX 31 are held in CDS 2 and CDS 3 . After that, the horizontal scanning circuit 5 sequentially outputs the column select signals φH 1 to φH 3 of “H” level. Accordingly, the reference signal component and the pixel signal components of the effective pixels PIX 21 and PIX 31 , which are stored in the noise suppressing circuit 4 , are read out through the horizontal select switches M 31 , M 32 , and M 33 in the time-series order and output through the output amplifier 6 . In this example, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the reference signal component different from the pixel signal component of the light-shielded pixel PIX 11 .

›DETAILED DESCRIPTION OF THE INVENTION · 2 of 12

As described above, in the first embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal component different from the signal components of the light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened.

(Second Embodiment)

FIG. 3 shows the arrangement of a solid-state image sensing apparatus according to the second embodiment of the present invention. This will be described.

The same reference numerals as in the first embodiment ( FIG. 1 ) denote the same constituent elements in the second embodiment. Different parts will mainly be described, and a repetitive description will be omitted.

Referring to FIG. 3 , reference symbols RS 1 to RS 3 denote pixel reset lines serving as first row select lines; TR 1 to TR 3 , PD signal transfer lines serving as second row select lines; and SEL 1 to SEL 3 denote pixel output select lines serving as third row select lines. Pixel reset signals, PD signal transfer signals, and pixel output select signals sent to these lines are indicated by φRS 1 to φRS 3 , φTR 1 to φTR 3 , and φSEL 1 to φSEL 3 , respectively.

A pixel power supply line 7 supplies a power to reset MOS transistors M 211 to M 233 and amplification MOS transistors M 311 to M 333 .

Pixels PIX 11 to PIX 33 which form a light-shielded pixel unit 1 and an effective pixel unit 2 include photodiodes D 11 to D 33 , transfer MOS transistors M 111 to M 133 , the reset MOS transistors M 211 to M 233 , the amplification MOS transistors M 311 to M 333 , and select MOS transistors M 411 to M 433 , respectively. The transfer MOS transistors M 111 to M 133 cause the photodiodes D 11 to D 33 to transfer charges and read them out. The reset MOS transistors M 211 to M 233 reset the transferred charges. The amplification MOS transistors M 311 to M 333 amplify the charges in the photodiodes D 11 to D 33 . The select MOS transistors M 411 to M 433 select rows.

More specifically, the gates of the reset MOS transistors M 211 , M 221 , and M 231 are connected to the pixel reset line RS 1 . The gates of the reset MOS transistors M 212 , M 222 , and M 232 are connected to the pixel reset line RS 2 . The gates of the reset MOS transistors M 213 , M 223 , and M 233 are connected to the pixel reset line. RS 3 .

The gates of the transfer MOS transistors M 111 , M 121 , and M 131 are connected to the PD signal transfer line TR 1 . The gates of the transfer MOS transistors M 112 , M 122 , and M 132 are connected to the PD signal transfer line TR 2 . The gates of the transfer MOS transistors M 113 , M 123 , and M 133 are connected to the PD signal transfer line TR 3 .

The gates of the select MOS transistors M 411 , M 421 , and M 431 are connected to the pixel output select line SEL 1 . The gates of the select MOS transistors M 412 , M 422 , and M 432 are connected to the pixel output select line SEL 2 . The gates of the select MOS transistors M 413 , M 423 , and M 433 are connected to the pixel output select line SEL 3 .

A vertical scanning circuit 3 outputs pixel reset signals φRS 1 to φRS 3 , PD signal transfer signals φTR 1 to φTR 3 , and pixel output select signals φSEL 1 to φSEL 3 . The above-described units are driven and controlled by these signals.

Reference symbols V 1 to V 3 denote vertical signal lines to extract the output signals from the amplification MOS transistors M 311 to M 313 , M 321 to M 323 , and M 331 to M 333 . Reference symbols I 41 to I 43 denote current sources to bias the vertical signal lines V 1 to V 3 .

A noise suppressing circuit 4 includes clamp capacitors CCL 1 to CCL 3 connected to the vertical signal lines V 1 to V 3 , sample-and-hold switches MN 1 to M 13 , clamp switches M 21 to M 23 , and sample-and-hold capacitors CSH 1 to CSH 3 .

The clamp capacitors CCL 1 to CCL 3 store the reset levels of the vertical signal lines V 1 to V 3 . The sample-and-hold capacitors CSH 1 to CSH 3 store the amplification components of the vertical signal lines V 1 to V 3 .

The sample-and-hold switches M 11 to M 13 transmit the signals of the vertical signal lines V 1 to V 3 to the sample-and-hold capacitors CSH 1 to CSH 3 . The gates of the sample-and-hold switches M 11 to M 13 are connected to a sample-and-hold control line SH and driven and controlled by a sample-and-hold control signal.

Each of the clamp switches M 21 to M 23 sets the terminal potential of one of a corresponding one of the clamp capacitors CCL 1 to CCL 3 and a corresponding one of the sample-and-hold capacitors CSH 1 to CSH 3 to a reference potential supplied from a clamp voltage line 8 . The gate of the clamp switch M 21 is connected to a clamp control line CL 2 and driven and controlled by a clamp control signal φCL 2 . The gates of the clamp switches M 22 and M 23 are connected to a clamp control line CL 1 and driven and controlled by a clamp control signal φCL 1 .

The connection points between the sample-and-hold capacitors CSH 1 to CSH 3 and the clamp switches M 21 to M 23 are connected to an output amplifier 6 through horizontal select switches M 31 to M 33 . The gates of the horizontal select switches M 31 to M 33 are connected to the output terminals of a horizontal scanning circuit 5 for column select signals φH 1 to φH 3 .

The output signal read operation of the solid-state image sensing apparatus according to the second embodiment of the present invention will be described below with reference to the timing charts shown in FIGS. 4A and 4B .

›DETAILED DESCRIPTION OF THE INVENTION · 3 of 12

When light becomes incident on the photodiodes D 11 to D 33 of the pixels PIX 11 to PIX 33 , the photodiodes D 11 to D 33 generate and store optical signal charges. The stored pixel signals are sequentially read out to the vertical signal lines V 1 to V 3 for the respective rows while being vertically scanned by the vertical scanning circuit 3 .

The operation in selecting the pixels of the first row will be described.

First, the pixel output select signal φSEL 1 is set to “H” level to connect the amplification MOS transistors M 311 , M 321 , and M 331 to the vertical signal lines V 1 to V 3 and current sources I 41 to I 43 through the row select MOS transistors M 411 , M 421 , and M 431 . Before the read of optical signal charges from the photodiodes D 11 to D 31 , the pixel reset signal φRS 1 is set to “H” level to reset the gates of the amplification MOS transistors M 311 , M 321 , and M 331 to the pixel power supply through the reset MOS transistors M 211 , M 221 , and M 231 .

In addition, both a sample-and-hold control signal φSH and the clamp control signals φCL 1 and φCL 2 are set to “H” level to initialize the terminal potentials of the clamp capacitors CCL 1 to CCL 3 and sample-and-hold capacitors CSH 1 to CSH 3 to the potential of the clamp voltage line 8 through the sample-and-hold switches M 11 to M 13 and clamp switches M 21 to M 23 . Next, the pixel reset signal φRS 1 is returned to “L” level to disconnect the pixel power supply line 7 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 . At this timing, the reset signal components of the vertical signal lines V 1 to V 3 are stored in the clamp capacitors CCL 1 to CCL 3 .

With this operation, the reset signal components containing reset noise and element variations in the amplification MOS transistors M 311 , M 321 , and M 331 are stored in the clamp capacitors CCL 1 to CCL 3 . After the end of signal storage in the clamp capacitors CCL 1 to CCL 3 , the clamp control signals φCL 1 and φCL 2 are set to “L” level to set the connection points between the sample-and-hold capacitors CSH 1 to CSH 3 and the clamp switches M 21 to M 23 in a high-impedance state.

At this timing, potential variations as the voltage differences between the reset signal components and the optical signal components, which appear on the vertical signal lines V 1 to V 3 , are stored in the sample-and-hold capacitors CSH 1 to CSH 3 through the clamp capacitors CCL 1 to CCL 3 and sample-and-hold switches MN 1 to M 13 . After that, when the sample-and-hold control signal φSH is returned to “L” level, the optical signal components of all pixel cells of the light-shielded pixel PIX 11 and effective pixels PIX 21 and PIX 31 are held in the sample-and-hold capacitors CSH 1 to CSH 3 . The column select signals φH 1 to φH 3 from the horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the sample-and-hold capacitors CSH 1 to CSH 3 are read out through the horizontal select switches M 31 to M 33 and sequentially output through the output amplifier 6 .

The read of the pixel cells connected to the first row is thus completed. In the second embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the signal output level of the light-shielded pixel PIX 11 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with the row select signals from the vertical scanning circuit 3 so that the read of all pixel cells is ended.

After the end of storage in the clamp capacitors CCL 1 to CCL 3 , the clamp control signal φCL 1 is set to “L” level to set the connection points between the sample-and-hold capacitors CSH 2 and CSH 3 and the clamp switches M 22 and M 23 in a high-impedance state. On the other hand, the clamp control signal φCL 1 holds “H” level. The terminal potentials of the clamp capacitor CCL 1 and sample-and-hold capacitor CSH 1 are still fixed to the potential of the clamp voltage line 8 . After that, the PD signal transfer signal φTR 1 is set to “H” level to transfer the optical signal charges in the photodiodes D 11 to D 31 to the gates of the amplification MOS transistors M 311 , M 321 , and M 331 through the transfer MOS transistors M 111 , M 121 , and M 131 .

At this time, potential variations as the voltage differences between the reset signal components and the optical signal components, which appear on the vertical signal lines V 2 and V 3 , are stored in the sample-and-hold capacitors CSH 2 and CSH 3 through the clamp capacitors CCL 2 and CCL 3 and sample-and-hold switches M 12 and M 13 . On the other hand, the clamp control signal φCL 2 holds “H” level. The terminal potentials of the clamp capacitor CCL 1 and sample-and-hold capacitor CSH 1 are still fixed to the potential of the clamp voltage line 8 . After that, the sample-and-hold control signal φSH is returned to “L” level, and the clamp control signal φCL 2 is set to “L” level. Accordingly, the clamp voltage level as the potential of the clamp voltage line 8 is held in the sample-and-hold capacitor CSH 1 . The optical signal components of the effective pixels PIX 21 and PIX 31 are held in the sample-and-hold capacitors CSH 2 and CSH 3 .

›DETAILED DESCRIPTION OF THE INVENTION · 4 of 12

Finally, the column select signals φH 1 to φH 3 from the horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the sample-and-hold capacitors CSH 1 to CSH 3 are read out through the horizontal select switches M 31 to M 33 and sequentially output through the output amplifier 6 . The read of the pixel cells connected to the first row is thus completed.

In the second embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the clamp voltage level as the potential of the clamp voltage line 8 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with the row select signals from the vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the second embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of the light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, one control line for the noise suppressing circuit 4 is added to change the drive timing. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the increase in chip area can be minimized. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened.

(Third Embodiment)

FIG. 5 shows the arrangement of a solid-state image sensing apparatus according to the third embodiment of the present invention. This will be described.

The same reference numerals as in the second embodiment ( FIG. 3 ) denote the same constituent elements in the third embodiment. Different parts will mainly be described, and repetitive description will be omitted.

Referring to FIG. 5 , the solid-state image sensing apparatus according to the third embodiment employs a different driving method for a noise suppressing circuit 4 .

In the above-described second embodiment, all the gates of the sample-and-hold switches M 11 to M 13 are connected to the sample-and-hold control line SH. In the third embodiment, the gate of a sample-and-hold switch MN 1 is connected to a sample-and-hold control line SH 2 . The gates of sample-and-hold switches M 12 and M 13 are connected to a sample-and-hold control line SH 1 .

That is, in the third embodiment, the sample-and-hold switch M 11 is driven and controlled by a sample-and-hold control signal φSH 2 . The sample-and-hold switches M 12 and M 13 are driven and controlled by a sample-and-hold control signal φSH 1 .

In addition, in the above-described second embodiment, the gate of the clamp switch M 21 is connected to the clamp control line CL 2 , and the gates of the clamp switches M 22 and M 23 are connected to the clamp control line CL 1 . In the third embodiment, the gates of clamp switches M 21 to M 23 are connected to a clamp control line CL. That is, all the clamp switches M 21 to M 23 are driven and controlled by a clamp control signal φCL. The remaining parts are the same as in FIG. 3 .

The read operation for the output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the third embodiment of the present invention will be described first with reference to the timing chart shown in FIG. 6A . The sample-and-hold control signals φSH 1 and φSH 2 are driven at the same timing as that of the sample-and-hold control signal φSH in FIG. 4A . The clamp control signal φCL is driven at the same timing as that of the clamp control signal φCL 1 in FIG. 4A . In this case, the drive timing is the same as in FIG. 4(A) , and repetitive description will be omitted.

After the end of storage in the clamp capacitors CCL 1 to CCL 3 , the clamp control signal φCL is set to “L” level to set the connection points between sample-and-hold capacitors CSH 1 to CSH 3 and the clamp switches M 21 to M 23 in a high-impedance state. Subsequently, the sample-and-hold control signal φSH 2 is returned to “L” level to cause the sample-and-hold capacitor CSH 1 to hold the clamp voltage level as the potential of a clamp voltage line 8 .

After that, a PD signal transfer signal φTR 1 is set to “H” level to transfer optical signal charges in photodiodes D 11 to D 31 to the gates of amplification MOS transistors M 311 , M 321 , and M 331 through transfer MOS transistors M 111 , M 121 , and M 131 . After the end of transfer, the PD signal transfer signal φTR 1 is returned to “L” level to disconnect the photodiodes D 11 to D 31 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 .

At this timing, potential variations as the voltage differences between the reset signal components and the optical signal components, which appear on vertical signal lines V 2 and V 3 , are stored in the sample-and-hold capacitors CSH 2 and CSH 3 through clamp capacitors CCL 2 and CCL 3 and sample-and-hold switches M 12 and M 13 .

›DETAILED DESCRIPTION OF THE INVENTION · 5 of 12

On the other hand, the sample-and-hold capacitor CSH 1 continuously holds the clamp voltage level as the potential of the clamp voltage line 8 . After that, the sample-and-hold control signal φSH 1 is returned to “L” level. Accordingly, the clamp voltage level as the potential of the clamp voltage line 8 is held in the sample-and-hold capacitor CSH 1 . The optical signal components of effective pixels PIX 21 and PIX 31 are held in the sample-and-hold capacitors CSH 2 and CSH 3 . Finally, column select signals φH 1 to φH 3 from a horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the sample-and-hold capacitors CSH 1 to CSH 3 are read out through horizontal select switches M 31 to M 33 and sequentially output through an output amplifier 6 . The read of the pixel cells connected to the first row is thus completed.

In the third embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the clamp voltage level as the potential of the clamp voltage line 8 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with the row select signals from a vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the third embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, one control line for a noise suppressing circuit 4 is added to change the drive timing. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the increase in chip area can be minimized. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened.

(Fourth Embodiment)

FIG. 7 shows the arrangement of a solid-state image sensing apparatus according to the fourth embodiment of the present invention. This will be described.

The same reference numerals as in the second embodiment ( FIG. 3 ) denote the same constituent elements in the fourth embodiment. Different parts will mainly be described, and repetitive description will be omitted.

Referring to FIG. 7 , the solid-state image sensing apparatus according to the fourth embodiment employs a different driving method for a noise suppressing circuit 4 . More specifically, vertical signal lines V 1 to V 3 have reset signal switches M 41 to M 43 , optical signal switches M 51 to M 53 , reset signal capacitors CSHR 1 to CSHR 3 , and optical signal capacitors CSHS 1 to CSHS 3 , respectively. The reset signal capacitors CSHR 1 to CSHR 3 store the reset levels of the vertical signal lines V 1 to V 3 . The optical signal capacitors CSHS 1 to CSHS 3 store the optical signal levels of the vertical signal lines V 1 to V 3 . The gates of the reset signal switches M 41 to M 43 are connected to a reset signal sample control line SHR and driven and controlled by a reset signal sample control signal φSHR. The gate of the optical signal switch M 51 is connected to an optical signal sample control line SHS 2 and driven and controlled by an optical signal sample control signal φSHS 2 . The gates of the optical signal switches M 52 and M 53 are connected to an optical signal sample control line SHS 1 and driven and controlled by an optical signal sample control signal φSHS 1 . Horizontal select switches M 61 to M 63 and M 71 to M 73 read out signals held in the reset signal capacitors CSHR 1 to CSHR 3 and optical signal capacitors CSHS 1 to CSHS 3 . A differential circuit 9 obtains the difference between a reset component and an optical signal component. The remaining parts are the same as in FIG. 3 .

When light becomes incident on photodiodes D 11 to D 33 of pixels PIX 11 to PIX 33 , the photodiodes D 11 to D 33 generate and store optical signal charges. The stored pixel signals are sequentially read out to the vertical signal lines V 1 to V 3 for the respective rows while being vertically scanned by a vertical scanning circuit 3 .

The operation in selecting the pixels of the first row will be described.

First, a pixel output select signal φSEL 1 is set to “H” level to connect amplification MOS transistors M 311 , M 321 , and M 331 to the vertical signal lines V 1 to V 3 and current sources I 41 to I 43 through row select MOS transistors M 411 , M 421 , and M 431 . Before the read of optical signal charges from the photodiodes D 11 to D 31 , a pixel reset signal φRS 1 is set to “H” level to reset the gates of the amplification MOS transistors M 311 , M 321 , and M 331 to the pixel power supply through reset MOS transistors M 211 , M 221 , and M 231 . Next, the pixel reset signal φRS 1 is returned to “L” level to disconnect a pixel power supply line 7 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 .

Subsequently, the reset signal sample control signal φSHR is set to “H” level to store the reset signal components of the vertical signal lines V 1 to V 3 in the reset signal capacitors CSHR 1 to CSHR 3 through the reset signal switches M 41 to M 43 . After the end of storage in the reset signal capacitors CSHR 1 to CSHR 3 , the reset signal sample control signal φSHR is returned to “L” level to cause the reset signal capacitors CSHR 1 to CSHR 3 to hold the stored reset signal components.

›DETAILED DESCRIPTION OF THE INVENTION · 6 of 12

After that, a PD signal transfer signal φTR 1 is set to “H” level to transfer the optical signal charges in the photodiodes D 11 to D 31 to the gates of the amplification MOS transistors M 311 , M 321 , and M 331 through transfer MOS transistors M 111 , M 121 , and M 131 . After the end of transfer, the PD signal transfer signal φTR 1 is returned to “L” level to disconnect the photodiodes D 11 to D 31 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 .

Subsequently, the optical signal sample control signals φSHS 1 and φSHS 2 are set to “H” level to store the optical signal components of the vertical signal lines V 1 to V 3 in the optical signal capacitors CSHS 1 to CSHS 3 through the optical signal switches M 51 to M 53 . After the end of storage in the optical signal capacitors CSHS 1 to CSHS 3 , the optical signal sample control signals φSHS 1 and φSHS 2 are returned to “L” level to cause the optical signal capacitors CSHS 1 to CSHS 3 to hold the stored optical signal components. Finally, column select signals φH 1 to φH 3 from a horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the reset signal capacitors CSHR 1 to CSHR 3 and optical signal capacitors CSHS 1 to CSHS 3 are read out to the differential circuit 9 through the horizontal select switches M 61 to M 63 and M 71 to M 73 . The differential circuit 9 obtains the difference between each reset signal component and a corresponding optical signal component and sequentially outputs the difference to a sensor output line OUT.

The read of the pixel cells connected to the first row is thus completed. In the fourth embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the signal output level of the light-shielded pixel PIX 11 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with the signals from the vertical scanning circuit 3 so that the read of all pixel cells is ended.

Before the read of optical signal charges from the photodiodes D 11 to D 31 , the pixel reset signal φRS 1 is set to “H” level to reset the gates of the amplification MOS transistors M 311 , M 321 , and M 331 to the pixel power supply through the reset MOS transistors M 211 , M 221 , and M 231 .

Next, the pixel reset signal φRS 1 is returned to “L” level to disconnect the pixel power supply line 7 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 . Subsequently, the reset signal sample control signal φSHR is set to “H” level to store the reset signal components of the vertical signal lines V 1 to V 3 in the reset signal capacitors CSHR 1 to CSHR 3 through the reset signal switches M 41 to M 43 .

Simultaneously, the optical signal sample control signal φSHS 2 is set to “H” level to store the reset signal component of the vertical signal line V 1 in the optical signal capacitor CSHS 1 through the optical signal switch M 51 . After the end of storage in the reset signal capacitors CSHR 1 to CSHR 3 and storage in optical signal capacitors CSHS 1 to CSHS 3 , the reset signal sample control signal φSHR and optical signal sample control signal φSHS 2 are returned to “L” level to cause the reset signal capacitors CSHR 1 to CSHR 3 and optical signal capacitor CSHS 1 to hold the stored reset signal components.

After that, the PD signal transfer signal φTR 1 is set to “H” level to transfer the optical signal charges in the photodiodes D 11 to D 31 to the gates of the amplification MOS transistors M 311 , M 321 , and M 331 through the transfer MOS transistors M 111 , M 121 , and M 131 . After the end of transfer, the PD signal transfer signal φTR 1 is returned to “L” level to disconnect the photodiodes D 11 to D 31 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 . Subsequently, the optical signal sample control signal φSHS 1 is set to “H” level to store the optical signal components of the vertical signal lines V 2 and V 3 in the optical signal capacitors CSHS 2 and CSHS 3 through the optical signal switches M 52 and M 53 .

After the end of storage in the optical signal capacitors CSHS 2 and CSHS 3 , the optical signal sample control signal φSHS 1 is returned to “L” level to cause the optical signal capacitors CSHS 2 and CSHS 3 to hold the stored optical signal components. Finally, the column select signals φH 1 to φH 3 from the horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the reset signal capacitors CSHR 1 to CSHR 3 and optical signal capacitors CSHS 1 to CSHS 3 are read out to the differential circuit 9 through the horizontal select switches M 61 to M 63 and M 71 to M 73 . The differential circuit 9 obtains the difference between each reset signal component and a corresponding optical signal component and sequentially outputs the difference to the sensor output line OUT.

The read of the pixel cells connected to the first row is thus completed.

In the fourth embodiment, both the reset signal capacitor CSHR 1 and the optical signal capacitor CSHS 1 hold the reset signal components. For this reason, the output from the differential circuit 9 is zero. The signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the zero output from the differential circuit 9 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with the signals from the vertical scanning circuit 3 so that the read of all pixel cells is ended.

›DETAILED DESCRIPTION OF THE INVENTION · 7 of 12

As described above, in the fourth embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of the light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, one control line for the noise suppressing circuit 4 is added to change the drive timing. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the increase in chip area can be minimized. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened. In addition, any degradation in characteristic due to power supply noise, GND noise, common mode noise component, and the like can be suppressed by executing differential processing.

(Fifth Embodiment)

FIG. 9 shows the arrangement of a solid-state image sensing apparatus according to the fifth embodiment of the present invention. This will be described.

The same reference numerals as in the second embodiment ( FIG. 3 ) denote the same constituent elements in the fifth embodiment. Different parts will mainly be described, and repetitive description will be omitted.

Referring to FIG. 9 , as a characteristic feature of the solid-state image sensing apparatus according to the fifth embodiment, a light-shielded pixel power supply line 10 which supplies a power to a light-shielded pixel unit 1 is newly added independently of an effective pixel power supply line 7 which supplies a power to an effective pixel unit 2 . In the second embodiment, the gate of the clamp switch M 21 is connected to the clamp control line CL 2 , and the gates of the clamp switches M 22 and M 23 are connected to the clamp control line CL 1 . In the fifth embodiment, the gates of clamp switches M 21 to M 23 of a noise suppressing circuit 4 are connected to a clamp control line CL and driven and controlled by a clamp control signal φCL.

The read operation for the output signal from the light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the fifth embodiment of the present invention will be described first with reference to the timing chart shown in FIG. 10A . The light-shielded pixel power supply line 10 and effective pixel power supply line 7 are set to a common potential. A sample-and-hold control signal φSH is set to “H” level at the same timing as that of the sample-and-hold control signal φSH in FIG. 4A . The clamp control signal φCL is set to “H” level at the same timing as that of the clamp control signal φCL 1 in FIG. 4A . In this case, the drive timing is the same as in FIG. 4A , and repetitive description will be omitted.

First, a pixel output select signal φSEL 1 is set to “H” level to connect amplification MOS transistors M 321 and M 331 to vertical signal lines V 2 and V 3 and current sources I 42 and I 43 through row select MOS transistors M 421 and M 431 . On the other hand, a vertical signal line V 1 is fixed to GND because there is no current path flowing to a pixel current source I 41 . Before the read of optical signal charges from photodiodes D 11 to D 31 , a pixel reset signal φRS 1 is set to “H” level to reset the gates of the amplification MOS transistors M 321 and M 331 to the effective pixel power supply line 7 through reset MOS transistors M 221 and M 231 .

On the other hand, the gate potential of an amplification MOS transistor M 311 is set to the GND potential. The potential is fixed to GND because the light-shielded pixel power supply line 10 is disconnected from the vertical signal line V 1 , and there is no current path flowing to the pixel current source I 41 . In addition, the sample-and-hold control signal φSH and the clamp control signal φCL are set to “H” level to initialize the terminal potentials of clamp capacitors CCL 1 to CCL 3 and sample-and-hold capacitors CSH 1 to CSH 3 to the potential of a clamp voltage line 8 through sample-and-hold switches M 11 to M 13 and clamp switches M 21 to M 23 .

Next, the pixel reset signal φRS 1 is returned to “L” level to disconnect the effective pixel power supply line 7 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 . At this time, the reset signal components of the vertical signal lines V 2 and V 3 are stored in the clamp capacitors CCL 2 and CCL 3 . The GND component of the vertical signal line V 1 is stored in the clamp capacitor CCL 1 . With this operation, the reset signal components containing reset noise and element variations in the amplification MOS transistors M 311 , M 321 , and M 331 are stored in the clamp capacitors CCL 2 and CCL 3 . After the end of storage in the clamp capacitors CCL 1 to CCL 3 , the clamp control signal φCL is set to “L” level to set the connection points between the sample-and-hold capacitors CSH 1 to CSH 3 and the clamp switches M 21 to M 23 in a high-impedance state.

After that, a PD signal transfer signal φTR 1 is set to “H” level to transfer the optical signal charges in the photodiodes D 21 and D 31 to the gates of the amplification MOS transistors M 321 and M 331 through the transfer MOS transistors M 121 and M 131 . On the other hand, the optical signal charges in the photodiode D 11 cannot be transferred because the gate potential of the amplification MOS transistor M 311 is GND. The potential remains almost GND. After the end of transfer, the PD signal transfer signal φTR 1 is returned to “L” level again to disconnect the photodiodes D 11 to D 31 from the gates of the amplification MOS transistors M 311 , M 321 , and M 331 .

›DETAILED DESCRIPTION OF THE INVENTION · 8 of 12

After that, when the sample-and-hold control signal φSH is returned to “L” level again, the clamp voltage level as the potential of the clamp voltage line 8 is held in the sample-and-hold capacitor CSH 1 , and the optical signal components of effective pixels PIX 21 and PIX 31 are held in the sample-and-hold capacitors CSH 2 and CSH 3 . Finally, column select signals φH 1 to φH 3 from a horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the sample-and-hold capacitors CSH 1 to CSH 3 are read out through horizontal select switches M 31 to M 33 and sequentially output through an output amplifier 6 . The read of the pixel cells connected to the first row is thus completed.

In the fifth embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the clamp voltage level as the potential of the clamp voltage line 8 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with row select signals from a vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the fifth embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, a pixel power supply for the light-shielded pixel unit 1 is newly added to change the drive timing. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the increase in chip area can be minimized. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels. For this reason, the time necessary for the read on the entire screen can be shortened.

(Sixth Embodiment)

FIG. 11 shows the arrangement of a solid-state image sensing apparatus according to the sixth embodiment of the present invention. This will be described.

The same reference numerals as in the fifth embodiment ( FIG. 9 ) denote the same constituent elements in the sixth embodiment. Different parts will mainly be described, and repetitive description will be omitted.

The solid-state image sensing apparatus according to the sixth embodiment is based on the arrangement shown in FIG. 9 but has a noise suppressing circuit 4 having a different structure. The structure of the noise suppressing circuit 4 is basically the same as in FIG. 7 except the following points.

In the above-described structure shown in FIG. 7 , the gate of the photodetection switch M 51 is connected to the optical signal sample control line SHS 2 and driven and controlled by the optical signal sample control signal φSHS 2 . The gates of the photodetection switches M 52 and M 53 are connected to the optical signal sample control line SHS 1 and driven and controlled by the optical signal sample control signal φSHS 1 . In the sixth embodiment, the gates of photodetection switches M 51 to M 53 are connected to an optical signal sample control line SHS and driven and controlled by an optical signal sample control signal φSHS. The remaining parts are the same as in FIGS. 7 and 9 , and detailed description thereof will be omitted.

The read operation for the output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the sixth embodiment of the present invention will be described first with reference to the timing chart shown in FIG. 12A . A light-shielded pixel power supply line 10 and an effective pixel power supply line 7 are set to a common potential. A reset signal sample control signal φSHS is set to “H” level at the same timing as that of the reset signal sample control signal φSHS 1 in FIG. 8A . In this case, the drive timing is the same as in FIG. 8A , and detailed description thereof will be omitted.

›DETAILED DESCRIPTION OF THE INVENTION · 9 of 12

Next, the pixel reset signal φRS 1 is returned to “L” level to disconnect the effective pixel power supply line 7 from the gates of the amplification MOS transistors M 311 to M 331 . Subsequently, the reset signal sample control signal φSHR is set to “H” level to store the reset signal components of the vertical signal lines V 2 and V 3 in reset signal capacitors CSHR 2 and CSHR 3 through reset signal switches M 42 and M 43 and the GND component of the vertical signal line V 1 in a reset signal capacitor CSHR 1 through a reset signal switch M 41 . After the end of storage in the reset signal capacitors CSHR 1 to CSHR 3 , the reset signal sample control signal φSHR is returned to “L” level to cause the reset signal capacitors CSHR 2 and CSHR 3 to hold the stored reset signal components and the reset signal capacitor CSHR to hold the GND component.

On the other hand, the optical signal charges in the photodiode D 11 cannot be transferred because the gate potential of the amplification MOS transistor M 311 is GND. The potential remains almost GND.

After the end of transfer, the PD signal transfer signal φTR 1 is returned to “L” level to disconnect the photodiodes D 11 to D 31 from the gates of the amplification MOS transistors M 311 to M 331 . Subsequently, the optical signal sample control signal φSHS is set to “H” level to store the optical signal components of the vertical signal lines V 2 and V 3 in optical signal capacitors CSHS 2 and CSHS 3 through optical signal switches M 52 and M 53 and the GND component of the vertical signal line V 1 in an optical signal capacitor CSHS 1 through an optical signal switch M 51 . After the end of storage in the optical signal capacitors CSHS 1 to CSHS 3 , the optical signal sample control signal φSHS is returned to “L” level to cause the optical signal capacitors CSHS 2 and CSHS 3 to hold the stored optical signal components and the optical signal capacitor CSHS 1 to hold the GND component. Finally, column select signals φH 1 to φH 3 from a horizontal scanning circuit 5 are sequentially set to “H” level. Accordingly, the voltages held in the reset signal capacitors CSHR 1 to CSHR 3 and optical signal capacitors CSHS 1 to CSHS 3 are read out to a differential circuit 9 through horizontal select switches M 61 to M 63 and M 71 to M 73 .

The differential circuit 9 obtains the difference between each reset signal component and a corresponding optical signal component and sequentially outputs the difference to a sensor output line OUT.

The read of the pixel cells connected to the first row is thus completed. At this time, both the reset signal capacitor CSHR 1 and the optical signal capacitor CSHS 1 hold the GND component. For this reason, the output from the differential circuit 9 is zero.

The signal output levels of effective pixels PIX 21 and PIX 31 are corrected on the basis of the zero output from the differential circuit 9 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with signals from a vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the sixth embodiment, when very strong light such a as spotlight or sunlight is incident, a reference signal level different from the signal components of light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, one control line for the noise suppressing circuit 4 is added to change the drive timing. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the increase in chip area can be minimized. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened. In addition, any degradation in characteristic due to power supply noise, GND noise, and the like can be suppressed by executing differential processing.

(Seventh Embodiment)

A solid-state image sensing apparatus according to the seventh embodiment of the present invention has the same arrangement as in FIG. 1 described above. The same reference numerals as in FIG. 1 denote the same constituent elements in the seventh embodiment, and different operations will mainly be described below by appropriately referring to FIG. 1 .

FIG. 13A is a timing chart showing the read operation for an output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the seventh embodiment of the present invention. The drive timing is the same as in FIG. 2A , and repetitive description will be omitted.

The read operation for a reference signal different from the output from the light-shielded pixel unit 1 , which is used when very strong light such as a spotlight or sunlight is incident, in the solid-state image sensing apparatus according to the seventh embodiment of the present invention will be described next in detail with reference to the timing chart shown in FIG. 13B . The operation until CDS 1 to CDS 3 of a noise suppressing circuit 4 are caused to hold the pixel signal components of a light-shielded pixel PIX 11 and effective pixels PIX 21 and PIX 31 is the same as in FIG. 13A ( FIG. 2A ). After that, a horizontal scanning circuit 5 fixes a column select signal φH 1 to “L” level and sequentially sets column select signals φH 2 and φH 3 to “H” level. Accordingly, the reset level of an output amplifier 6 , and subsequently, the pixel signal components of the effective pixels PIX 21 and PIX 31 , which are stored in the noise suppressing circuit 4 , are read out through horizontal select switches M 32 and M 33 in the time-series order and output through the output amplifier 6 . At this time, in the seventh embodiment, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the reset level of the output amplifier 6 , which is different from the pixel signal component of the light-shielded pixel PIX 11 .

›DETAILED DESCRIPTION OF THE INVENTION · 10 of 12

As described above, in the seventh embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal component different from the signal components of the light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened.

(Eighth Embodiment)

The arrangement of a solid-state image sensing apparatus according to the eighth embodiment of the present invention is different from FIG. 9 described above in that a single power supply line 7 is commonly used as a light-shielded pixel power supply line 10 which supplies a power to a light-shielded pixel unit 1 and an effective pixel power supply line 7 which supplies power to an effective pixel unit 2 . The remaining parts are the same as in FIG. 9 . The same reference numerals as in FIG. 9 denote the same constituent elements in the eighth embodiment, and different operations will mainly be described below by appropriately referring to FIG. 9 .

FIG. 14A is a timing chart showing the read operation for the output signal from the light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the eighth embodiment of the present invention. The clamp control signal φCL is set to “H” level at the same timing as that of the clamp control signal φCL 1 in FIG. 4A . In this case, the drive timing is the same as in FIG. 4A , and repetitive description will be omitted.

The read operation for a reference signal different from the output from the light-shielded pixel unit 1 , which is used when very strong light such as a spotlight or sunlight is incident, in the solid-state image sensing apparatus according to the eighth embodiment of the present invention will be described next in detail with reference to the timing chart shown in FIG. 14B . The operation until optical signal components are stored in sample-and-hold capacitors CSH 1 to CSH 3 is the same as in FIG. 13A ( FIG. 4A ). After that, a horizontal scanning circuit 5 fixes a column select signal φH 1 to “L” level and sequentially sets column select signals φH 2 and φH 3 to “H” level. Accordingly, the reset level of an output amplifier 6 , and subsequently, the pixel signal components of effective pixels PIX 21 and PIX 31 , which are stored in a noise suppressing circuit 4 , are read out through horizontal select switches M 32 and M 33 in the time-series order and output through the output amplifier 6 . At this time, the signal output levels of the effective pixels PIX 21 and PIX 31 are corrected on the basis of the reset level of the output amplifier 6 , which is different from the pixel signal component of a light-shielded pixel PIX 11 . In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with row select signals from a vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the eighth embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, the drive timing of the horizontal scanning circuit 5 is changed. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the chip area does not increase. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels. For this reason, the time necessary for the read on the entire screen can be shortened.

(Ninth Embodiment)

The arrangement of a solid-state image sensing apparatus according to the ninth embodiment of the present invention is different from that shown in FIG. 7 described above in that the gate of an optical signal switch M 51 is connected to an optical signal sample control signal φSHS 1 . The remaining parts are the same as in FIG. 7 . The same reference numerals as in FIG. 7 denote the same constituent elements in the ninth embodiment, and different operations will mainly be described below by appropriately referring to FIG. 7 .

FIG. 15A is a timing chart showing the read operation for the output signal from a light-shielded pixel unit 1 , which is used when the incident light amount is small, in the solid-state image sensing apparatus according to the ninth embodiment of the present invention. A reset signal sample control signal φSHR is set to “H” level at the same timing as that of the reset signal sample control signal φSHR 1 in FIG. 8A . In this case, the drive timing is the same as in FIG. 8A , and repetitive description will be omitted.

›DETAILED DESCRIPTION OF THE INVENTION · 11 of 12

After that, a horizontal scanning circuit 5 fixes a column select signal φH 1 to “L” level and sequentially sets column select signals φH 2 and φH 3 to “H” level. Accordingly, the reset level of a differential circuit 9 , and subsequently, the voltages held in the reset signal capacitors CSHR 2 and CSHR 3 and optical signal capacitors CSHS 2 and CSHS 3 of a noise suppressing circuit 4 are read out to the differential circuit 9 through horizontal select switches M 62 and M 63 and M 72 and M 73 . The differential circuit 9 obtains the difference between each reset signal component and a corresponding optical signal component and sequentially outputs the difference to a sensor output line OUT. The read of the pixel cells connected to the first row is thus completed. In the ninth embodiment, the signal output levels of effective pixels PIX 21 and PIX 31 are corrected on the basis of the reset level of the differential circuit 9 .

In the same way as described above, the signals of the pixel cells connected to the second and subsequent rows are sequentially read out in accordance with signals from a vertical scanning circuit 3 so that the read of all pixel cells is ended.

As described above, in the ninth embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal level different from the signal components of light-shielded pixels PIX 11 to PIX 13 is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels PIX 11 to PIX 13 can be obtained. In addition, the drive timing of the horizontal scanning circuit 5 is changed. This change makes it possible to select whether the signal components from the light-shielded pixels PIX 11 to PIX 13 or the reference signal level is to be output. Hence, the chip area does not increase. Furthermore, it is unnecessary to output both the output levels of the light-shielded pixels PIX 11 to PIX 13 and the reference signal level different from the output data of the light-shielded pixels PIX 11 to PIX 13 . For this reason, the time necessary for the read on the entire screen can be shortened. In addition, any degradation in characteristic due to power supply noise, GND noise, and the like can be suppressed by executing differential processing.

The relationship between appended claims and the above-described first to ninth embodiments is as follows. An effective signal photoelectric conversion unit in claims corresponds to the effective pixel unit 2 . A reference signal photoelectric conversion unit corresponds to the light-shielded pixel unit 1 . A noise suppressing unit corresponds to the noise suppressing circuit 4 . A switch unit corresponds to the clamp switch. A first power supply line corresponds to the pixel power supply line 7 . A second power supply line corresponds to a light-shielded pixel power supply line 10 .

(10th Embodiment)

The 10th embodiment in which one of the solid-state image sensing apparatuses according to the above-described first to ninth embodiments is applied to a camera will be described below in detail.

FIG. 16 is a block diagram showing the arrangement of the camera according to the 10th embodiment of the present invention.

As shown in FIG. 16 , a photographing lens 30 and shutter/stop 29 are arranged on the optical path of object light. An imager 21 is arranged on the imaging plane of light that has passed through the shutter/stop 29 . The imager 21 corresponds to the solid-state image sensing apparatus according to one of the above-described first to ninth embodiments.

The output from the imager 21 is connected to the inputs of an image processing unit 23 and luminance information acquisition unit 24 through a CDS·A/D 22 . The output from the luminance information acquisition unit 24 is connected to the input of a timing generator (imager control unit) 25 through an OB/dummy switching determination unit 26 such as a CPU.

Outputs from the timing generator 25 are connected to the inputs of the imager 21 and CDS·A/D 22 . In addition, the output from an exposure control unit 27 and that from a photometry unit 28 are connected to the inputs of the OB/dummy switching determination unit 26 .

A determination unit in claims corresponds to the OB/dummy switching determination unit 26 .

In this arrangement, the shutter/stop 29 is driven and controlled by the exposure control unit 27 . An analog video signal is output from the imager 21 exposed through the photographing lens 30 and shutter/stop 29 to the CDS·A/D 22 .

The analog video signal contains a light-receiving pixel signal and a light-shielded pixel signal or reference signal level. The analog video signal is digitized by correlated double sampling and analog-to-digitized conversion by the CDS·A/D 22 . At this time, the black level is fed back and clamped in the camera by using the light-shielded pixel signal or reference signal level selectively output from the imager 21 . The output signal from the CDS·A/D 22 is subjected to 3-CCD processing, spatial frequency band correction, and YCC processing by the image processing unit 23 and output to a recording medium or monitor (not shown). The output signal from the CDS·A/D 22 is also input to the luminance information acquisition unit 24 . The luminance information acquisition unit 24 generates an evaluation value of luminance information and inputs it to the OB/dummy switching determination unit 26 . The evaluation value of luminance information is obtained in the following way. For example, on an erect object image shown in FIG. 17 , luminance level equivalent signals are added and averaged for each divided area. The maximum value of the obtained values is used as the evaluation value. Shutter speed information and stop information in exposure control are input from the exposure control unit 27 to the OB/dummy switching determination unit 26 . Object luminance information is also input to the OB/dummy switching determination unit 26 from the photometry unit 28 which measures the luminance of the object (not shown). The imager 21 receives a driving pulse and a control signal necessary for switching of light-shielded pixel signal/reference signal from the timing generator 25 . A signal representing the timing of sampling the analog video signal and a signal representing the black level clamp operation period are input from the timing generator 25 to the CDS·A/D 22 . The OB/dummy switching determination unit 26 sends an instruction signal for an operation mode including switching of light-shielded pixel signal/reference signal.

›DETAILED DESCRIPTION OF THE INVENTION · 12 of 12

The first operation example of the camera according to the 10th embodiment of the present invention will be described below in detail with reference to the flowchart shown in FIG. 18 .

When the first operation starts, the reference signal (instruction signal) is selectively output from the OB/dummy switching determination unit 26 to the timing generator 25 (step S 1 ). The exposure control unit 27 executes exposure control (step S 2 ). The timing generator 25 is operated to cause the imager 21 to output an analog video signal of one frame. The CDS·A/D 22 digitizes the analog video signal (step S 3 ). The luminance information acquisition unit 24 generates an evaluation value of luminance information in the above-described way (step S 4 ). The OB/dummy switching determination unit 26 determines in the above-described way whether a high-luminance area exists (step S 5 ). If YES in step S 5 , the reference signal is selectively output from the OB/dummy switching determination unit 26 to the timing generator 25 (step S 6 ). If NO in step S 5 , the light-shielded pixel signal is selectively output from the OB/dummy switching determination unit 26 to the timing generator 25 (step S 7 ). The exposure control unit 27 executes exposure control (step S 8 ). The timing generator 25 is operated to cause the imager 21 to output an analog video signal of one frame. The CDS·A/D 22 digitizes the video signal (step S 9 ). The image processing unit 23 executes image processing (step S 10 ). The above operation is executed for each frame.

The first operation is thus ended.

The second operation example of the camera according to the 10th embodiment of the present invention will be described next in detail with reference to the flowchart shown in FIG. 19 .

When the second operation starts, the photometry unit 28 acquires object luminance information on the basis of a photographing instruction from an operation unit (not shown) (step S 11 ). The OB/dummy switching determination unit 26 determines whether a high-luminance area exists (step S 12 ).

If YES in step S 12 , the reference signal is selectively output from the OB/dummy switching determination unit 26 to the timing generator 25 (step S 13 ). If NO in step S 12 , the light-shielded pixel signal is selectively output from the OB/dummy switching determination unit 26 to the timing generator 25 (step S 14 ).

The exposure control unit 27 executes exposure control (step S 15 ). The timing generator 25 is operated to cause the imager 21 to output a video signal of one frame. The CDS·A/D 22 digitizes the video signal (step S 16 ). The image processing unit 23 executes image processing (step S 17 ). The above operation is executed for each frame. The second operation is thus ended.

As described above, in the 10th embodiment, when very strong light such as a spotlight or sunlight is incident, a reference signal different from a light-shielded pixel signal is output. With this arrangement, an image which is not influenced by a black level variation observed in the light-shielded pixels can be obtained. In addition, the time necessary for the read on the entire screen can be shortened. Furthermore, any degradation in characteristic due to power supply noise or GND noise can be suppressed by executing differential processing. In addition, satisfactory video signal processing and iris control are implemented.

The first to tenth embodiments of the present invention have been described above. The present invention is not limited to these embodiments, and various changes and modifications can be made without departing from the spirit and scope of the present invention. For example, a plurality of light-shielded pixel units may be arranged in a plurality of rows. In this case, since the influence of fixed pattern noise can further be reduced, the reliability of the reference signal level for correction further increases.

According to the present invention, a solid-state image sensing apparatus which can appropriately correct the black level of a video signal even when a high-luminance state or spotlight exists can be provided.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details, representative devices, and illustrated examples shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

Claims as granted

9 claims

Classifications

8 codes

IPC · International Patent Classification

Section H — Electricity

H04N25/65
H04N25/00
H01L31/0203
H01L27/00
H01L27/146
H01L31/0232

USPC · US Patent Classification

250/208.1348/241

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Thanh X. Luu

art unit 2878 · TC 2800

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