Driving circuit for DC/DC converter

The present invention relates to a power supply system and more particularly to a driving circuit for DC/DC converter.

A high-side and low-side driver is widely applied to drive the switch-bridge of bridge type converters, such as active clamp forward converter, half-bridge converter and full-bridge converter. FIG. 1 shows a conventional configuration of an active clamp forward converter with a driving IC. In this converter, a low-side switch S 1 (main switch) is employed in the primary side of the transformer T, and an active clamp branch is connected in parallel with the primary winding of the transformer T. The active clamp branch includes a high-side switch (active switch) S 2 and a clamping capacitor C 11 connected in series. The low-side switch S 1 and the high-side switch S 2 operating in complementary form a switch-bridge, and a high-side and low-side driving IC 1 is employed to drive the switch-bridge.

At present, the high-side driver and the low-side driver are usually integrated into one chip. The most popular design is shown in FIG. 2 . In the driver IC 1 of this prior art, two input signals Hin, Lin are needed. One input signal (Lin) is a PWM signal to trigger the low-side driving circuit 3 , and the other one (Hin) is the inverting signal of the PWM signal to trigger the high-side driving circuit 2 . Two high voltage rated switches M 1 and M 2 are employed to achieve the voltage level shifting of the high-side driver 1 , which is controlled by the inverting signal of the PWM signal. Several disadvantages occur due to the employment of the high voltage rated switches M 1 and M 2 . Firstly, switching loss of these switches is significant especially at a high switching frequency. Secondly, the switches M 1 and M 2 are packaged into the driver IC, which increases the complicacy of the manufacturing. Thirdly, these high voltage rated switches increase the cost of the driver. Additionally, in order to drive the high-side switch S 2 and the low-side switch S 1 better, a dead-time setting circuit is needed to generate two complementary signals with optimized dead time. It is known that the ability of the source current and the sink current is an important factor to evaluate a driving circuit. In most of the driver ICs, the ability of the source current and sink current is limited, which will slow the turning on and turning off speed of the switch component in a larger power converter and will decrease the efficiency of the converter. Therefore, an additional buffer circuit is needed.

The present invention provides a low-cost high-side and low-side driver, which overcomes the disadvantages of the prior arts. It can be implemented by simple discrete circuits and can be integrated into one chip.

It is an object of the present invention to drive a high-side switch and a low-side switch in a DC/DC converter with one PWM input signal.

It is another object of the present invention to shift the voltage level for the high-side driver by a simple circuit.,

It is further an object of the present invention to achieve an adjustable dead time setting function to avoid the potential cross conduction problem between the high-side and low-side switches.

It is further another an object of the present invention to have a large source and a sink current ability to increase the switching speed of the low-side switch and the high-side switch.

It is additional an object of the present invention to achieve a driving circuit for DC/DC converter with a simple structure and very low cost driving method.

According to the objects of the present invention, a high-side and low-side driving circuit for DC/DC converter is proposed. This driving circuit includes a voltage level shifting capacitor, a time delay circuit, a low side driving buffer, and a high side driving buffer.

The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings, in which:

FIG. 1 shows a conventional high-side and low-side driving IC applied to an active clamp forward DC/DC converter according to the prior art;

FIG. 2 shows the most popular design with high-side and low-side driver according to the prior art;

FIG. 3 shows a block diagram of a high-side and low-side driving circuit applied to an active clamp forward converter in accordance with a preferred embodiment of the present invention;

FIG. 4 shows a schematic circuit of a leading edge delay circuit that is one embodiment of the dead-time set circuit implemented in the present invention;

FIG. 5A shows a schematic circuit of a high-side driving circuit with an embodiment of the present invention to drive the high-side switch;

FIG. 5B shows a schematic circuit of a high-side driving circuit with another embodiment of the present invention to drive the high-side switch;

FIG. 6 shows a schematic circuit of a whole high-side and low-side driver applied to an active clamp forward DC/DC converter in accordance with an embodiment of the present invention;

FIG. 7 shows a schematic circuit of a whole high-side and low-side driver applied to an active clamp forward DC/DC converter in accordance with another embodiment of the present invention;

FIG. 8 shows a block diagram of a high-side and low-side driving circuit applied to an active clamp flyback converter in accordance with another embodiment of the present invention;

FIG. 9 shows a block diagram of a high-side and low-side driving circuit applied to an active clamp forward-flyback converter in accordance with another embodiment of the present invention;

FIG. 10 shows a block diagram of a high-side and low-side driving circuit applied to a boost converter in accordance with another embodiment of the present invention; and

FIG. 11 shows a block diagram of a high-side and low-side driving circuit applied to a boost half bridge converter in accordance with another embodiment of the present invention.

The present invention will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of preferred embodiments of this invention are presented herein for purpose of illustration and description only; it is not intended to be exhaustive or to be limited to the precise form disclosed.

This driving circuit of the present invention is used for driving a switch-bridge of a DC-DC converter, which can be an active clamp forward converter, an active clamp flyback converter, an active clamp forward-flyback converter, a boost converter, or a boost half-bridge converter. The switch-bridge of the DC-DC converter is composed of a main switch (a low-side switch) and an active switch (a high-side switch) connected in series. The active switch operates in complementary to the main switch. Hereafter, for example, a driving circuit applied to an active clamp forward converter will be illustrated in detail.

Referring to FIG. 3 , a block diagram of a high-side and low-side driving circuit of the present invention applied to an active clamp forward DC/DC converter is illustrated. In this converter, a low-side switch S 1 is connected in series to the primary winding of a transformer T, and an active clamp branch is connected in parallel with the primary winding of the transformer T. The active clamp branch consists of a high-side switch S 2 and a clamping capacitor C 11 connected in series. A driving circuit 11 has three ports. The first port is a driving signal input port 1 for receiving a PWM signal. The second port is a low side driving output port 2 which is connected to the low-side switch S 1 . The third port is a high side driving output port 3 which is connected to the high-side switch S 2 . The driving circuit 11 has two branches. One branch is a series circuit composed of a leading edge delay circuit and a buffer A for the low side between Port 1 and Port 2 , and the other branch is a series circuit composed of a voltage level shifting capacitor C 1 and a buffer B for the high side between Port 1 and Port 3 . The low-side switch S 1 and the high-side switch S 2 operate in complementary.

The fundamental driving principles of the driving circuit can be described as follows:

It is impartial to assume that the PWM signal keeps in a high level voltage, and the low-side switch S 1 is turned on and the high-side switch S 2 is turned off at one moment. When the PWM signal drops to a low level, the signal is delivered to the buffer A immediately through the delay circuit, and the low-side switch S 1 is turned off by the buffer A. The output capacitor of the low-side switch S 1 is charged by the magnetizing current, and the voltage across the low-side switch S 1 rises rapidly. This signal of voltage rising reflects to the buffer B immediately and then triggers the high-side driver to turn on the switch S 2 .

When the PWM signal turns to a high level, the capacitor C 1 delivers this signal to the buffer B and triggers the buffer B to turn off the high-side switch S 2 immediately. To avoid the potential cross conduction between switch S 1 and S 2 , the PWM signal is delayed with a short time by delay circuit and then triggers the buffer A to turn on the switch S 1 after turning off of the switch S 2 .

FIG. 4 shows a detailed configuration of a leading edge delay circuit that is one embodiment of the dead-time set circuit used in the driving circuit of the present invention. Port 1 is an input terminal connected to the PWM signal, Port 4 is connected to a voltage source VCC, and Port 5 is connected to the ground. A PNP transistor Q 1 includes an emitter terminal connected to the PWM signal, a collector terminal connected to the output of the delay circuit, and a base terminal connected to the voltage source through a resistor R 10 and connected to the ground through a resistor R 11 . A capacitor C 10 is coupled between the base terminal and the emitter terminal of the transistor Q 1 . A diode D 10 includes an anode terminal connected to the collector terminal of the transistor Q 1 , and a cathode terminal connected to the emitter terminal of the transistor Q 1 .

While the PWM signal is low, the transistor Q 1 is kept in an OFF state, since a positive voltage is coupled across C 10 and applied between the emitter terminal and the base terminal of the transistor Q 1 . When the PWM signal turns to a high level, the capacitor C 10 is discharged through the resistor R 10 and resistor R 11 . The transistor Q 1 turns on until the voltage across the capacitor C 10 discharges from positive to negative. Therefore, a short time of turning on delay is obtained between the output terminal and the input terminal of the delay circuit. The delay time can be set by the capacitance of the capacitor C 10 and the resistance R 10 and R 11 . When the PWM signal drops to a low level, the signal is delivered through the diode D 10 directly. There is no delay function for turning off time.

FIG. 5A shows a detailed configuration of the high-side driving circuit used in the present invention, which is composed of the capacitor C 1 and the buffer B circuit. The capacitor C 1 achieves the voltage level shifter function. One terminal of the capacitor C 1 is connected to the PWM input signal, and the other terminal of the capacitor C 1 is connected to the buffer B circuit. Port 6 of the buffer B circuit is connected to the source of the switch S 2 . A boost trap circuit including diode D 31 and D 34 which are connected in series with a capacitor C 31 is coupled between the voltage source VCC and Port 6 . A PNP transistor Q 5 is applied with a collector terminal connected to the first terminal of the capacitor C 31 , a base terminal connected to the collector terminal through a resistor R 31 , and an emitter terminal connected to the gate terminal of the high-side switch. Another NPN transistor Q 6 includes a base terminal connected to the capacitor C 1 through a current limited resistor R 32 , a collector terminal connected to the base terminal of the transistor Q 5 , and an emitter terminal connected to the port 6 . The diodes D 32 and D 33 are inversely paralleled between the base terminal and the emitter terminal of the transistors Q 5 and Q 6 , respectively. These components form the fundamental high-side driving circuit. When the switch S 2 is in an OFF state, a resistor R 33 connected between Port 12 and the cathode terminal of the boost trap diode D 31 provides a constant bias current to the transistor Q 6 .

When the voltage of PWM is low and the switch S 1 is in an OFF state, a high voltage occurs in Port 6 , which keeps the transistor Q 6 in an OFF state due to the conduction of the diode D 33 . The gate to source voltage of the switch S 2 can be built up through the transistor Q 5 , which turns the switch S 2 on. When the PWM signal turns from low to high, this signal is delivered to the base terminal of the transistor Q 6 through the capacitor C 1 and the resistor R 32 , and the transistor Q 6 is turned on immediately. The gate capacitor of the switch S 2 is discharged through the diode D 32 and the transistor Q 6 soon, and the transistor Q 5 and the switch S 2 are turned off. When the switch S 1 is turned on, the transistor Q 6 keeps in an ON state with a bias current from Vcc to the base terminal of the transistor Q 6 through the diode D 31 , the resistor R 33 and R 32 , the transistor Q 6 and the switch S 1 . The switch S 2 keeps in an OFF state with its gate voltage clamped at a low level. The voltage of the capacitor C 1 is discharged to a low voltage through the resistor R 32 , the transistor Q 6 and the switch S 1 . Moreover, the capacitor C 1 and the resistor R 32 is a RC snubber for the switch S 2 .

FIG. 5B shows the schematic circuit of the high-side driving circuit in accordance with another embodiment of the present invention to drive the switch S 2 . Comparing with the high-side driving circuit shown in FIG. 5A , the only difference is the charge circuit for the switch S 2 . The resistor R 31 and the diode D 32 are removed. The transistor Q 5 is replaced with a PNP transistor, which includes an emitter terminal connected to the first terminal of the capacitor C 31 , a base terminal connected to the emitter terminal through a diode D 36 , and a collector terminal connected to the gate of the switch S 2 . Port 7 is the drain terminal of the high-side switch S 2 . Diodes D 38 and D 37 are connected in series and between the cathode terminal of the diode D 31 and Port 7 . A capacitor C 32 is connected between the base terminal of the transistor Q 5 and the cathode terminal of the diode D 38 .

When the PWM signal is high and the low-side switch S 1 is in an ON state, the voltage across the capacitor C 32 is zero and the diode D 37 is in an OFF state with a reversed voltage. During this interval, the transistor Q 5 is OFF and the transistor Q 6 is ON. When the PWM signal turns to a low level, the low-side switch S 1 is turned off, and the voltage of Port 6 rises. When the voltage of port 6 is the same with that of Port 7 , the diode D 37 conducts, the transistor Q 5 is turned on with a base current through the capacitor C 32 and the diode D 37 , and the switch S 2 is turned on. After the gate-to-source voltage of the switch S 2 and the voltage of the capacitor C 32 are charged to Vcc, the transistor Q 5 is turned off immediately, and the gate-to-source voltage of the switch S 2 is kept in Vcc. When the PWM signal turns to a highlevel, the switch S 1 is turned on and the capacitor C 32 is discharged to zero through the diode D 38 and the diode D 36 . Other operations are the same as those in the floating driver shown in FIG. 5A . This floating driver provides the zero voltage switching conduction for the switch S 2 .

FIG. 6 shows the circuit diagram of the whole high-side and low-side driving circuit in accordance with an embodiment of the present invention applied to the active clamp forward DC/DC converter. The circuit described in FIG. 6 originates from the circuit shown in FIG. 2 . The block delay time circuit is replaced with the previous leading edge delay circuit described in FIG. 4 . The block of buffer A is replaced with the transistor Q 3 and Q 4 , and the block of buffer B is replaced with the previous circuit described in FIG. 5A .

FIG. 7 shows the schematic circuit of a high-side and low-side driving circuit in accordance with another embodiment of the present invention applied to the active clamp forward DC/DC converter. Comparing to FIG. 6 , the driving circuit of FIG. 7 is a simplified circuit structure by removing the transistor Q 3 and adding a resistor R 51 paralleled with the base-emitter of the transistor Q 4 . In additional, the anode terminal of the diode D 10 should be connected to the base terminal of the transistor Q 4 . When the PWM signal turns to a high level, the switch S 1 is driven by the PWM signal through the transistor Q 1 with a time delay. When the PWM signal turns to a low level, the gate capacitor of the switch S 1 is discharged through the transistor Q 4 .

Those skilled in the pertinent art will understand, however, that the driving circuit of the present invention may be implemented in other switch-bridge topologies of other DC-DC converters. FIG. 8 shows a block diagram of a high-side and low-side driving circuit applied to an active clamp flyback converter. FIG. 9 shows a block diagram of a high-side and low-side driving circuit applied to an active clamp forward-flyback converter. FIG. 10 shows a block diagram of a high-side and low-side driving circuit applied to a boost converter. FIG. 11 shows a block diagram of a high-side and low-side driving circuit applied to a boost half bridge converter in accordance with another embodiment of the present invention. Such variations do not depart from the gist of the invention and are not described in detail herein.

While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.