Phase-change memory and method having restore function

1. Field of the Invention

The present invention relates to phase-change memory devices, and more particularly, the present invention relates to a phase-change memory and method which include the state restoration of a phase-change cell.

2. Description of the Related Art

Phase change memory cell devices rely on phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The differing resistance values exhibited by the two phases are used to distinguish logic values of the memory cells. That is, an amorphous state exhibits a relatively high resistance, and a crystalline state exhibits a relatively low resistance.

Reference is made to FIG. 1 , which schematically illustrates the phase transition of a phase change cell. The phase change cell is made up of top and bottom electrodes 101 and 102 , a resistive heater 103 such as BEC, and a volume of phase change material 104 such as a chalcogenide alloy. The phase of a portion of the phase change material 104 is set by Joule heating of the material according to an amount of current passed through the resistive heater 103 via a transistor 105 . To obtain an amorphous state (referred to as a “RESET” state), a relatively high write current pulse (“RESET pulse”) is passed through the phase change cell to melt a portion of the material 104 for a short period of time. The current is removed and the cell cools rapidly to below the melting point, which results in the portion of the material 104 having an amorphous phase. The melting point of chalcogenide, for example, is approximately 610° C. To obtain a crystalline state (referred to as a “SET” state), a lower current write pulse (“SET pulse”) is applied to the phase change cell for a longer period of time to heat the material 104 to below its melting point. This causes the amorphous portion of the material to re-crystallize to a crystalline phase that is maintained once the current is removed and the cell is rapidly cooled. For example, the re-crystallization temperature of chalcogenide is approximately 450° C.

FIG. 2 illustrates the change in temperature over time of a chalcogenide phase change cell material during the SET and RESET operations. As shown, the material is made amorphous during a rapid cooling (e.g., a few nanosecond) after being heated to above the melting temperature Tm. Crystallization occurs by heating the material below the melting point Tm and above the crystallization temperature Tx for a longer period of time (e.g., 50 nanoseconds or less).

FIG. 3 is a graph showing the V-I characteristics of a phase change memory cell. Again, the example shown illustrates the case of a chalcogenide alloy phase change material. In this example, the SET current region of 1.0 to 1.5 mA is for writing a crystalline state of the memory cell, and the RESET current region of 1.5 to 2.5 mA is for writing an amorphous state of the memory cell. As is apparent from FIG. 3 , during a read operation, the differing resistance values of the amorphous and crystalline states can be readily distinguished by application of a low read voltage (e.g., less than 0.5 volts) below a given threshold voltage Vt. The threshold voltage Vt is the voltage above which the current of the cell material becomes the same for both the amorphous and crystalline states.

In a conventional phase-change random access memory (PRAM), the phase change cell operates as a non-volatile memory. That is, sufficiently high write currents are applied to maintain the amorphous and crystalline states of the phase-change material.

In the conventional amorphous write operation (i.e., the RESET operation), the phase change process of the phase change material is characterized by sequential nucleus formation and growth steps. The growth steps result in a large ratio between the RESET resistance and the SET resistance. For example, the RESET resistance may be several tens to hundreds times larger than the SET resistance. This advantageously provides a relatively large sensing margin and data retention time. Unfortunately, however, a high write current is needed to achieve both nucleus formation and growth, and the overall power consumption is large.

It would therefore be desirable to provide a phase-change memory device, such as a PRAM, which exhibits reduced power consumption.

According to one aspect of the present invention, a phase-change memory device which includes a phase-change memory cell including a volume of material which is programmable between amorphous and crystalline states, and a write current source which selectively applies a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state. The phase-change memory device further includes a restore circuit which selectively applies the first write current pulse to the phase-change memory cell to restore an amorphous state of the phase-change memory cell.

According to another aspect of the present invention, a phase-change memory device is provided which includes a phase-change memory cell including a volume of material which is programmable between amorphous and crystalline states. The phase-change memory device also includes a write current source which operates in a low-power mode to selectively apply a first write current pulse to program the phase-change memory cell into the amorphous state and a second write current pulse to program the phase-change memory cell into the crystalline state, and which operates in a high-power mode to selectively apply a third write current pulse to program the phase-change memory cell into the amorphous state and a fourth write current pulse to program the phase-change memory cell into the crystalline state. The phase-change memory device further includes a restore circuit which is operative in the low-power mode to selectively apply the first current pulse to the phase-change memory cell to restore an amorphous state of the phase-change memory cell.

According to still another aspect of the present invention, a phase-change memory device is provided which is operable in a non-volatile mode and a volatile mode. The phase-change memory device includes a phase-change memory cell including a volume of material which is programmable between amorphous and crystalline states, and a restore circuit which restores at least an amorphous state of the phase-change memory cell in the volatile mode.

According to yet another aspect of the present invention, a phase-change memory device is provided which includes a data line, a plurality of I/O lines, a plurality of bit lines, a plurality of word lines, and a plurality of phase-change memory cells at intersections of the word lines and bit lines, where each of the phase-change memory cells including a volume of material which is programmable between amorphous and crystalline states. The phase-change memory device also includes a write current source which outputs first and second write current pulses to the bit lines according to a voltage of the data line, the first write current pulse for programming the phase-change memory cells into the amorphous state and the second write current pulse for programming the phase-change memory cell into the crystalline state. The phase-change memory device further includes a plurality of sense amplifiers, respectively connected to the bit lines and the I/O lines, which read respective states of the phase-change memory cells, and a restore circuit, connected to the I/O lines and to the data line, which controls the voltage of the data line to restore at least an amorphous state of the phase-change memory cells.

According to another aspect of the present invention, a method of programming a phase-change memory cell is provided which includes selectively applying first and second write current pulses to a phase-change memory cell, the first write current pulse for programming the phase-change memory cells into an amorphous state and the second write current pulse for programming the phase-change memory cell into a crystalline state. The method also includes detecting a state of the phase-change memory cell, and conducting a first restore operation by again applying the first write current pulse to the phase-change memory cell when the phase-change memory cell is detected as the amorphous state.

The above and other aspects and features of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a phase-change memory cell for explaining the transition between SET and RESET states;

FIG. 2 illustrates the change in temperature over time of a chalcogenide phase change cell material during SET and RESET operations;

FIG. 3 is a graph showing the V-I characteristics of a phase change memory cell;

FIG. 4 is a circuit diagram of a twin cell circuit scheme which may be adopted in the phase-change memory device of an embodiment of the present invention;

FIG. 5 is a flow chart of a volatile memory mode according to an embodiment of the present invention;

FIG. 6 is a circuit diagram of a phase-change memory device of an embodiment of the present invention;

FIG. 7 is a block diagram of a current source of a phase-change memory device of an embodiment of the present invention; and

FIGS. 8(A) and 8(B) are graphs showing the V-I characteristics of a phase change memory cell in a non-volatile mode and a volatile mode, respectively, according to an embodiment of the present invention.

The present invention will now be described in detail below with reference to several preferred but non-limiting embodiments.

As discussed previously, the conventional phase-change memory is a non-volatile device, and the phase change transition to the amorphous state includes sequential nucleus formation and growth steps. In contrast, the present invention is at least partially characterized by operating in a volatile memory mode (or a low-power mode) in which the transition to the amorphous state includes nucleus formation only. Further, in the volatile mode, both amorphous write and the crystalline write take place a much lower write currents than the conventional device. Power consumption is substantially reduced. Also, while the resultant resistance ratio between the amorphous and crystalline states is reduced, it is still sufficient to read data.

As examples only, TABLE 1 below shows the write currents for the volatile and non-volatile modes of the present invention in the case of a chalcogenide phase change cell material.

As shown in example of TABLE 1, the write current amperages in the volatile mode are substantially less than those in the non-volatile mode. Further, in both modes, the amorphous (RESET) write current pulse has an amperage which is greater than that of the crystalline (SET) write current pulse, and the amorphous write current pulse has a pulse width which is less than that of the crystalline write current pulse.

In the volatile mode, however, it is not necessary for the amperage of the RESET write pulse to exceed that of the SET pulse. For example, the RESET pulse and SET pulse can have the same amperage, but different pulse widths and/or different quenching times.

It should also be noted that the phrase “amorphous state” as used herein has a relative connotation meaning either that more of the material is amorphous than in the crystalline state, or that the material is amorphous to a higher degree than in the crystalline state. In either case, it is not necessary for the material or a portion of the material to be mostly or predominately amorphous, particularly in the context of the volatile mode. Rather, the low write currents in the volatile mode need only to be capable of altering the crystalline structure to create a sufficient resistance ratio between the amorphous and crystalline states.

Since only nucleus formation is carried out in the amorphous write process, the data retention is shortened. However, according to the present invention, the short data retention time is compensated for by periodically restoring at least the amorphous states of the phase-change cells.

FIG. 4 is a circuit diagram of a twin cell circuit scheme which may be adopted in the phase-change memory device of an embodiment of the present invention. In this configuration, one bit is physically realized by a combination of two cells written to have opposite logic states, i.e., a low resistance crystalline state and a high resistance amorphous state. The use of two cells per bit enlarges the device operation window and prevents failures caused by resistance distribution.

In FIG. 4 , one bit is stored in phase-change cells PCELLi 1 and PCELLi 2 , and another bit is stored in phase-change cells PCELLj 1 and PCELLj 2 . The phase-change cell PCELLi 1 and a transistor PTRi 1 are connected in series between a reference voltage (e.g., ground) and a bit line BL, and the phase-change cell PCELLi 2 and a transistor PTRi 2 are connected in series between the reference voltage and an inverted bit line /BL. Likewise, the phase-change cell PCELLj 1 and a transistor PTRj 1 are connected in series between the reference voltage and the bit line BL, and the phase-change cell PCELLj 2 and a transistor PTRj 2 are connected in series between the reference voltage and the inverted bit line /BL. The gates of transistors PTRi 1 and PTRi 2 are connected to a word line Wli, and the gates of transistors PTRj 1 and PTRj 2 are connected to another word line Wlj.

A current source ISET 1 and a current source ISET 2 supply respective SET current pulses to the bit lines BL and /BL. Control transistors CTR and /CTR are serially connected to one end of the bit lines BL and /BL, respectively, and are supplied with a RESET current pulse from a current source IRESET. Clamping circuits 210 and 220 are connected to the other end of the bit lines BL and /BL, respectively, and a sense amplifier S/A is connected to the clamping circuits 210 and 220 .

The write operation of the twin cell circuit of FIG. 4 will now be described. It is assumed here that a logic value of “1” is to be written into the first combination of cells PCELLi 1 and PCELLi 2 . In this case, word line Wli is set to HIGH, and data signals D and /D are HIGH and LOW, respectively. As such, transistors PTRi 1 , PTRi 2 , and CTR are all turned ON, while transistor /CTR is OFF.

Since transistor /CTR is OFF, only the SET current pulse ISET 2 is passed through the PCELLi 2 and the transistor PTRi 2 . The SET current pulse ISET 2 places the PCELLi 2 into a SET (crystalline) state. The SET state is a low resistive state which may be considered to have a logic value “0”.

On the other hand, since the transistor CTR is ON, the RESET current pulse IRESET is additionally passed through the PCELLi 1 and transistor PTRi 1 . Although not shown in FIG. 4 , the current pulse ISET 1 is controlled by and synchronized with the RESET current pulse IRESET, such that a pulse width and timing of ISET 1 is the same as those of IRESET. IRESET and ISET 1 are therefore combined to place the phase-change cell to place the PCELLi 1 into a RESET (amorphous) state. The RESET state is a high resistive state which may be considered to have a logic value “1”.

In a read operation, the clamping circuits 210 and 220 limit a voltage on the bit lines BL and /BL to less than the threshold voltage to minimize any perturbation during reading. In this state, assuming again that WLi is HIGH, the low resistance of the PCELLi 2 will cause the current on the bit line /BL to be low, while the high resistance of the PCELLi 1 will cause the current on the bit line BL to be high. These currents of the respective bit lines BL and /BL are compared at the sense amplifier S/A to discriminate the logic value of the first combination of phase-change cells PCELLi 1 and PCELLi 2 .

FIG. 5 is a flow chart for explaining a volatile mode of operation of a phase-change memory according to an embodiment of the present invention. In a first step 310 , the data stored in the phase-change (PRAM) cell is read. For example, in the configuration of FIG. 4 , the currents of the respective bit lines BL and /BL are compared at the sense amplifier S/A to discriminate the logic value of the of phase-change cells PCELLi 1 and PCELLi 2 . Then, in a second step 320 , the read data is transferred externally and used to restore the state of the read PRAM cell. For example, in the configuration of FIG. 4 , the read data is applied as the data signals D and /D to rewrite the same data in the previously read cells PCELLi 1 and PCELLi 2 .

The restoration of the state of the read phase-change cell can occur upon each reading of the phase-change cell. Alternately, the restoration can occur at each of regular intervals, for example, intervals of one hour or more.

FIG. 6 illustrates a phase-change memory device according to an embodiment of the present invention. As shown, the phase-change memory device includes a current source 440 , a data circuit 420 , bit line pairs BL 1 , /BL 1 . . . BLm, BLm, a phase-change memory array block 410 , a read circuit 430 , local I/O lines LIO and /LIO, an I/O sense amplifier 450 , a transfer switch SWTR, and global I/O lines GIO and /GIO.

The data circuit 420 includes a plurality of transistor pairs CTR 1 , /CTR 1 . . . CTRm, /CTRm. Each of the transistors CTR 1 . . . CTRm is connected in series between a IRESET current output of the current source 440 and the bit lines BL 1 . . . BLm, and each of the transistors /CTR 1 . . . /CTRm is connected in series between the IRESET current output of the current source 440 and the bit lines /BL 1 . . . /BLm. The data circuit 420 also includes transistors RTR 1 and RTR 2 having gates commonly connected to a read-write control signal RWCTRL. Transistor RTR 1 is connected between data line /D and global I/O line GIO, and transistor RTR 1 is connected between data line D and global I/O line /GIO.

The phase change memory array block 410 includes a plurality of phase-change memory cell pairs at the intersections of the word lines WL 1 . . . WLn and the bit line pairs BL 1 , /BL 1 . . . BLm, /BLm. Each of the memory cells pairs are connected as shown in previously described FIG. 4 .

The read circuit 430 includes a plurality of sensing circuits STM 1 . . . STMm respectively connected between the bit line pairs BL 1 , /BL 1 . . . BLm, /BLm and the local I/O lines LIO, /LIO. The sensing circuits STM 1 . . . STMm include respective sense amplifiers S/A 1 . . . S/Am, and respective transistor pairs TTR 11 , TTR 12 . . . TTRm 1 , TTRm 2 . The gates of the transistor pairs are commonly connect to respective control signals CD 1 . . . CDm. Also, although not shown, the read circuit 430 may include a plurality of clamping circuits connected to the bit lines BL 1 , /BL 1 . . . BLm, /BLm (see FIG. 4 ).

Finally, the I/O sense amplifier 450 and a transfer switch SWTR are connected in series between the local I/O lines LIO, /LIO and the global I/O lines GIO, /GIO.

The write operation of the phase-change memory device of FIG. 6 will now be described with respect to the bit lines BL 1 , /BL 1 . It is assumed here that a logic value of “1” is to be written into phase-change cells of the bit lines BL 1 , /BL 1 of selected word lines among the word line WL 1 . . . WLn. In this case, the selected word lines are set to HIGH, and data signals D and /D are HIGH and LOW, respectively. As such, transistors CTR 1 is turned ON, while transistor /CTR 1 is OFF.

Since transistor /CTR 1 is OFF, only the SET current pulse ISET 2 is passed through the memory cells of the selected word lines via bit line /BL 1 . The SET current pulse ISET 2 places the memory cells of bit line /BL 1 into a SET (crystalline) state. The SET state is a low resistive state which may be considered to have a logic value “0”.

On the other hand, since the transistor CTR 1 is ON, both the RESET current pulse IRESET and the SET current pulse ISET 2 are passed through the selected memory cells of bit line BL 1 . Although not shown in FIG. 6 , the current pulse ISET 1 is controlled by and synchronized with the RESET current pulse IRESET, such that a pulse width and timing of ISET 1 is the same as those of IRESET. IRESET and ISET 1 are therefore combined to place the phase-change cell to place the PCELLi 1 into a RESET (amorphous) state. The RESET state is a high resistive state which may be considered to have a logic value “1”.

As shown in the block diagram of FIG. 7 , the current source 440 may include a high drive current source 701 and a low drive current source 702 . The high drive current source 701 outputs IRESET, and the low drive current source 702 outputs ISET 1 and ISET 2 . The values and pulse width of IRESET, ISET 1 and ISET 2 will depend on whether the circuit is operating in a non-volatile or volatile mode. Also, the values and pulse width of ISET 1 and ISET 2 further depend on whether an amorphous or crystalline write is being executed. TABLE 2 below shows examples in the case where the memory array block includes chalcogenide phase-change memory cell.

A read operation of the circuit of FIG. 6 may be carried out in the same manner as discussed above in connection with FIG. 4 .

FIG. 8(A) is a graph showing the V-I characteristics of a phase change memory cell in the non-volatile mode, and FIG. 8(B) is a graph showing the V-I characteristics of a phase change memory cell in the volatile mode. Again, the example shown illustrates the case of a chalcogenide alloy phase change material. As shown in FIG. 8(A) , the non-volatile mode exhibits a large resistance ratio between Rset and Rreset in the case where a read voltage is less than 0.5 volts. At higher voltages at and above a threshold voltage Vt, the resistance Rdyn of the two states becomes the same. On the other hand, as shown in FIG. 8(B) , the threshold voltage Vt of the volatile mode is less than that of the non-volatile mode. Also, the volatile mode exhibits a smaller resistance ratio between Rset and Rreset. Nonetheless, this resistance ratio is still sufficient for sensing purposes, especially when the twin cell scheme such as that shown in FIG. 4 is adopted.

Referring to FIG. 6 , data of selected memory cells of bit lines /BL 1 . . . /BLm are applied to local I/O line LIO under control of column selection signals CD 1 . . . CDm. Also in this example, data of selected memory cells of bit lines BL 1 . . . BLm are applied to local I/O line /LIO under control of the column selection signals CD 1 . . . CDm. The data is transferred to the global I/O lines GIO and /GIO via the I/O sense amplifier 450 and the transfer switch SWTR under control of a signal BAS.

As discussed previously, the volatile mode of operation is characterized by a relative short retention time of the data stored in the phase-change memory cells, particularly in the amorphous state. Accordingly, the embodiment of FIG. 6 includes circuitry for restoring the stored data in the volatile mode. That is, under control of the RWCTRL signal, the global I/O lines are selectively connected to the data lines D and /D via the transistors RTR 1 and RTR 2 . In this state, the read data appearing on the global lines GIO and /GIO is written into the memory cell array in the same manner as discussed above in connection with normally written data. In the case where the circuit is operating in a non-volatile mode, the RWCTRL signal is LOW, thereby isolating the data lines D and /D from the global I/O lines GIO and /GIO. In the case where the circuit is operating in a volatile mode, the RWCTRL signal is HIGH, thereby connected the data lines D and /D from the global I/O lines GIO and /GIO. In this manner, data is restored in the volatile mode.

It is noted that the data lines D and /D can instead be connected to the local I/O lines LIO and /LIO in the volatile mode.

As noted previously, the restore operation in the volatile mode can be executed upon each read of the data stored in the memory array 410 . Alternately, the restore operation can be executed at regular intervals, for example, of one hour or more.

In the drawings and specification, there have been disclosed typical preferred embodiments of this invention and, although specific examples are set forth, they are used in a generic and descriptive sense only and not for purposes of limitation. It should therefore be understood the scope of the present invention is to be construed by the appended claims, and not by the exemplary embodiments.