Apparatus and method for sensing current in a power transistor

The invention is related to power transistors, and, in particular, to an apparatus and method for sensing current in a power transistor.

Current limiting circuits are employed as protection in many applications, such as power regulators, voltage sources, and current sources. Most current limit/protection circuits sense a load current associated with a power transistor for the particular application. Typically, a sense resistor is series-coupled to the load for sensing the load current. However, configuring a sense resistor in series with the load may result in power loss, heat dissipation, and other undesirable conditions.

Other current limiting circuits mirror current flowing through a power MOSFET with a mirror MOSFET. Also, circuitry is employed to substantially reduce the effect of channel modulation on the mirrored current by keeping the power and mirror MOSFETs' drain-source voltages relatively equal. However, extensive current mirroring can introduce undesirable poles into an open loop frequency response of a current limiting circuit. Also, the accuracy of this circuit can be diminished by component mismatch.

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, in which:

FIG. 1 illustrates a block diagram of an embodiment of a circuit for sensing current in a power regulation circuit; and

FIG. 2 shows an embodiment of the circuit of FIG. 1 that is arranged for sensing current in a switching power regulation circuit, arranged in accordance with aspects of the present invention.

Various embodiments of the present invention will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed invention.

Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, and the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The phrase “in one embodiment,” as used herein does not necessarily refer to the same embodiment, although it may. The term “coupled” means either a direct electrical connection between the items connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other signal.

Briefly stated, the invention is related to a circuit for regulating a sensed current in a power transistor. The circuit is configured to sense whether the drain current of the power transistor has reached a limit current I limit . A sense transistor is arranged in an m:1 current mirror relationship with the power transistor. Additionally, a current sink that is coupled to the drain of the sense current is also configured to sink a current equal to I limit /m. Further, a comparison circuit is configured to compare the drain voltages of the power and sense transistors.

In one embodiment, if the drain current of the power transistor is less than I limit , a current sink pulls down the drain of the sense transistor, so that the drain voltage of the sense transistor is less than the drain voltage of the power transistor. However, if the level of the drain current of the power transistor reaches I limit , then Vds of the sense transistor would reach Vds of the power transistor, and the comparator would trip. The drain current of power transistor could be expressed as follows:

Id=KW 2/ L 2( Vgs−Vt )(1+ λVds 2 )

And the drain current of the power transistor mirror could be expressed as

d=KW 1/ L 1( Vgs−Vt )(1+ λVds 1 ),

where mW1/L1=W2/L2 is respectively width and length of M 1 and M 2 and m is mirroring factor. K, Vt, λ are process dependent physical parameters of MOSFET transistors. Vgs−gate source voltage applied to M 1 , M 2 and Vds 1 , Vds 2 are respectively M 1 's and M 2 's drain source voltages, where at the trip point Vds 1 =Vds 2 . In this way, the current comparison is performed when drain-source voltages of both transistors power and its mirror are equal to each other. Thus, the channel modulation effect can be virtually eliminated without invoking a special circuit to equalize drain-source voltages.

In another embodiment, two switches are arranged to be open when switching currents flowing through the power transistor and sense transistors are each substantially zero. By opening the switches when these switching currents are each substantially zero, a false output (trip) of the comparison circuit can be prevented. Also, when the switches are closed, this circuit can operate in the same way as first described.

FIG. 1 illustrates a block diagram of circuit 100 which may be used for current limitation in a continuous power regulator, or other circuits that employ a power transistor, and the like. Circuit 100 at least includes control circuit 110 , load circuit 120 , comparator circuit 130 , current sink 140 , and transistors M 1 and M 2 .

Transistor M 1 may be a power transistor, such as a power MOSFET, and the like. Also, transistor M 1 may provide current I 1 at a drain of transistor M 1 . Load circuit 120 may receive current I 1 .

Additionally, transistors M 1 and M 2 may be configured in an m:1 current mirror arrangement. Transistor M 2 may provide current I 2 at a drain of transistor M 2 .

Comparator circuit 130 may compare a voltage associated with the drain of transistor M 1 (V 1 ) to another voltage associated with the drain of transistor M 2 (V 2 ). Further, comparator circuit 130 may provide a limit signal (Lim) in response to a comparison. Circuit 100 may be arranged such that comparator circuit 100 trips if current I 1 reaches a limit current (I limit ).

Current sink 140 may be configured to sink a current equal to I limit /m. If I 1 is less than I limit , current sink 140 may pull down voltage V 2 so that voltage V 2 is less than voltage V 1 . However, if the drain current of the power transistor reaches I limit , then V 2 may reach V 1 . If this event occurs, comparator circuit 130 may trip and provide the limit signal (Lim).

Transistors M 1 and M 2 may be arranged to receive a signal (GateDrv) at their respective gates. Control circuit 110 may provide signal GateDrv. Also, if comparator circuit 130 trips, control circuit 110 may adjust signal GateDrv such that current I 1 is kept less than I limit . In one embodiment, control circuit 110 is configured to adjust signal GateDrv to turn transistors M 1 and M 2 off if comparator circuit 130 trips. In another embodiment, control circuit 110 is configured to reduce a voltage associated with signal GateDrv to reduce current I 1 if comparator circuit 130 trips.

Control circuit 110 may provide current limiting control, as previously described, and may also provide additional functionality, as explained in greater detail with reference to FIG. 2 below.

FIG. 2 shows an embodiment of a circuit ( 200 ) that is substantially similar to circuit 100 , except that circuit 200 is further arranged for sensing current in a switching power regulator circuit, and the like. Components in circuit 200 may operate in a substantially similar manner as similarly-named components in circuit 100 , albeit different in some ways. Circuit 200 may include additional components such as switches S 1 and S 2 .

In circuit 200 , currents I 1 and I 2 may be current pulse signals. Also, load circuit 220 may include switched capacitors, switched inductors, and the like.

Although not shown in FIG. 2 , control circuit 220 may include an error amplifier, feedback control responsive to a reference voltage (VREF), feedback voltage (Vfdbk) associated with load circuit 220 , and drivers for driving the gates of transistors M 1 and M 2 . These “not shown” components may be arranged to operate in a manner that is substantially similar to their typical use in a switching power regulator circuit.

Switches S 1 and S 2 may be configured to open and close in response to a clock signal (CLK) that is provided by control circuit 210 . In one embodiment, switches S 1 and S 2 are arranged to be open when currents I 1 and I 2 are each substantially zero. Because, if switches S 1 and S 2 were closed when currents I 1 and I 2 are each substantially zero, comparator circuit 230 could trip even though I 1 had not yet reached I limit . Thus, by instead opening switches S 1 and S 2 when currents I 1 and I 2 are each substantially zero, a false output (trip) of comparator circuit 230 can be prevented.

The above specification, examples and data provide a description of the manufacture and use of the composition of the invention. Since many embodiments of the invention can be made without departing from the spirit and scope of the invention, the invention also resides in the claims hereinafter appended.