Split gate drive scheme to improve reliable voltage operation range

The present application claims priority to commonly assigned U.S. Provisional Patent Application No. 60/492,403, filed on Aug. 4, 2003, entitled “A Driver Scheme for Improved Reliability of High Efficiency, High Current Switched Regulator,” which is hereby incorporated by reference in its entirety.

This invention relates to power regulators such as DC/DC converters.

Direct current to direct current (DC/DC) converters generally include an upper driver portion and a lower driver portion to deliver current to a load via an external inductor and an external capacitor.

For example, FIG. 1 shows a DC/DC converter system 100 in a step-down configuration known as a “buck” configuration. A pulse width modulator (PWM) controller 110 controls an upper driver incorporating a PMOS transistor 120 and a lower driver incorporating an NMOS transistor 130 . Transistors 120 and 130 are commonly implemented using power transistors. A load 140 may be coupled with the output of transistor 120 and transistor 130 via an inductor 150 and a capacitor 160 . System 100 also includes parasitic inductances L 1 and L 2 , which may be caused by the inductance of the packaging, printed circuit board traces, finite equivalent series inductance (ESL) of an external decoupling capacitor such as capacitor 180 , or other factors. In operation, PWM controller 110 turns transistor 120 and transistor 130 on and off alternately, so current flows through current path I 1 , and current path I 2 alternately.

The configuration shown in FIG. 1 may not be optimal for high current applications, since PMOS power transistors generally have a relatively large on-state drain/source resistance R DS-on . For example, R DS-on for a PMOS power transistor is generally about two to three times higher than the R DS-on value of a comparably sized NMOS power transistor. To achieve a comparable value of R DS-on , the size of the PMOS power transistor would need to be increased. However, larger devices experience an increased gate switching loss and may lead to undesirably large die sizes.

Alternately, NMOS power transistors may be used for both the upper and lower drivers. FIG. 2A shows such an alternate implementation. A DC/DC converter system 200 includes a PWM controller 210 to control an upper driver including a top NMOS transistor 220 and a bottom NMOS transistor 230 . System 200 also includes a bootstrap pre-driver 215 and a bootstrap capacitance C BS 218 in communication with top transistor 220 .

Because of the lower value of R DS-on for NMOS transistors relative to comparable PMOS transistors, the implementation shown in FIG. 2A may provide higher efficiency performance than the implementation of FIG. 1 . However, the addition of the bootstrap pre-driver increases the complexity of the system. If NMOS transistor 220 is integrated, the on-state breakdown voltage of NMOS transistor 220 may be too low for higher current applications, or the reliable input voltage operating range may have to be decreased.

For example, FIG. 2B shows typical 5V NMOS transistor breakdown and snap back behavior for a number of values of V GS . In contrast, FIG. 2C shows typical 5V PMOS transistor breakdown behavior for the same values of V GS . An NMOS transistor can handle large V DS when its gate voltage is low or the transistor is off. As FIG. 2C illustrates, PMOS transistors are typically better able to handle on-state stress than comparable NMOS transistors.

In general, in one aspect, a power regulator includes a first driver with a first driver output and a second driver with a first driver output. The first driver may include a first switch with an output terminal in communication with the first driver output and a second switch with an output terminal in communication with the first driver output. The power dissipation of the first switch may be less than the power dissipation of the second switch. For example, the first switch and the second switch may be implemented using transistors, with the first switch having a lower power dissipation than the second switch due to its transistor type or size.

An on-state breakdown voltage of the second switch may be greater than an on-state breakdown voltage of the first switch. For example, the first switch and the second switch may be implemented using transistors, with the second switch having a greater on-state breakdown voltage than the first switch due to its transistor type or size.

In some implementations, the first switch may comprise an NMOS transistor, and the regulator may further include a bootstrap pre-driver in communication with a gate of the first transistor.

In some implementations, the regulator may include circuitry to turn off the first driver. The circuitry may be configured to turn off the first driver by controlling a first turnoff initiation time and a first slew rate of a voltage applied to a gate of the first transistor. The circuitry may further be configured to control a second turnoff initiation time and a second slew rate of a voltage applied to a gate of the second transistor.

The circuitry may be configured to control the first turnoff initiation time to be before the second turnoff initiation time. The circuitry may be configured to control the first slew rate to be greater than the second slew rate. The circuitry may be configured to control the first turnoff initiation time, the second turnoff initiation time, the first slew rate, and the second slew rate so that the first transistor is turned off prior to the second turnoff initiation time.

The regulator may be included in a direct current to direct current (DC/DC) converter. The regulator may include a filter with an input in communication with the first driver output and the second driver output. The filter may be in communication with a load.

The first driver may further include one or more additional switches, each having an output terminal in communication with the first driver output. The second driver may include one or more second driver switches each having an output terminal in communication with the second driver output. The second driver switches may include NMOS transistors. The one or more second driver switches may include a first transistor and a second transistor, the first transistor having an on-state drain source resistance lower than an on-state drain source resistance of the second transistor. The first transistor may have an on-state breakdown voltage lower than an on-state breakdown voltage of the second transistor.

In general, in another aspect, a power regulator may include a first driving means including a first driver output means. The first driving means may include a first switching means with an output means in communication with the first driver output means, and may include a second switching means with an output means in communication with the first driver output means. A power dissipation of the first switching means may be less than a power dissipation of the second switching means.

In general, in another aspect, a method may include turning off a first switch of a driver, the first switch having a lower power dissipation in the on-state than a second switch of the driver, and turning off a second switch of the driver. The first switch may include a first transistor, and turning off the first switch of the driver may comprise modifying a voltage applied to a gate of the first transistor from an on voltage at which the first transistor is on to an off voltage at which the first transistor is off.

The second switch may comprise a second transistor, and turning off the second switch of the driver may comprise modifying a voltage applied to a gate of the second transistor from an on voltage at which the second transistor is on to an off voltage at which the second transistor is off.

Modifying the voltage applied to the gate of the first transistor may be performed over a time equal to a first transistor turn off time, while modifying the voltage applied to the gate of the second transistor may be performed over a time equal to a second transistor turn off time. The second transistor turn off time may be greater than the first transistor turn off time. For example, the second transistor turn off time may be at least two times as long as the first transistor turn off time.

The method may further include turning on a different driver. Turning on the different driver may comprise turning on one or more switches included in the different driver. The one or more switches may be implemented as transistors. The method may further include turning off the different driver. In an implementation, the different driver comprises a first transistor and a second transistor, and turning off the different driver comprises turning off the first transistor prior to turning off the second transistor. The first transistor may have a lower dissipation in the on state than the second transistor. The first transistor may have a lower breakdown voltage in the on state than the second transistor.

The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.

FIG. 1 is schematic of a DC/DC converter according to the prior art.

FIG. 2A is a schematic of another DC/DC converter according to the prior art.

FIG. 2B illustrates typical 5V NMOS transistor breakdown and snap back behavior.

FIG. 2C illustrates typical 5V PMOS transistor breakdown behavior.

FIG. 3 is a schematic of a power regulator according to an implementation.

FIG. 4 is a schematic of an implementation of a DC/DC converter system incorporating both NMOS and PMOS transistors in a top switch.

FIG. 5 illustrates a method to turn off a driver of a DC/DC converter system such as the system shown in FIG. 4 .

FIG. 6 shows voltages V 1 , V 2 , V x , and current I L for a DC/DC converter such as that illustrated in FIG. 2A .

FIG. 7 shows voltages V 1 , V 2 , V x , and I for a DC/DC converter such as that shown in FIG. 1 , where a gate voltage of a transistor is increased slowly and dI/dt is still large.

FIG. 8 shows an implementation of a DC/DC converter system to reduce or eliminate over- and under-shoot.

FIG. 9 shows voltages V 1a , V 1b , V x , V 2 , and currents I 1 and I 2 for an implementation such as that shown in FIG. 8 .

FIG. 10 shows an implementation of a DC/DC converter system including more than two transistors in an upper driver portion.

Like reference symbols in the various drawings indicate like elements.

Systems and techniques described herein may allow for efficient power regulators with improved reliability.

DC/DC converters such as those shown in FIGS. 1 and 2A may have a number of limitations. For example, for integrated DC/DC converters, internal voltage bouncing (caused by over- and under-shooting of PVDD and PVSS) may lead to undesirable noise, and may over-stress the constituent transistors. Voltage bouncing may stress transistor 220 particularly, which may experience values of V DS that are greater than the input voltage by about 2 V. The excessive stress on transistor 220 may limit the reliable input voltage operation range of system 200 .

Voltage bouncing may occur primarily due to parasitic inductances such as inductance L 1 and inductance L 2 of FIG. 2A . Converter 200 of FIG. 2A may be in one of three states. In a first state, transistor 220 is on and transistor 230 is off. V x is high, the current through inductor 250 is increasing, and capacitor 280 is being charged. In a second state, transistor 220 is off and transistor 230 is on. V x is low and the current through inductor 250 is decreasing. In a third state, both transistor 220 and transistor 230 are off. The third state occurs during the transition between the first state and the second state. Time spent in the third state is often referred to as dead time.

FIG. 6 illustrates the voltage V 1 at the gate of transistor 220 , the voltage V 2 at the gate of transistor 230 , the voltage V x at the common terminal of transistors 220 and 230 , and the current through inductor 250 of FIG. 2A .

During the transition between the first state and the second state, current flow switches between current path 232 and current path 234 . PVDD and PVSS may experience over-shooting or under-shooting with respect to external power supply voltages PVIN and PGND primarily due to parasitic inductances L 1 and L 2 .

Overshoot and undershoot may occur as follows. During the first state, the current through inductor 250 is increasing to a peak current I p before transistor 220 is turning off. This current flows through parasitic inductance L 1 , and so as transistor 220 is turned off, a voltage L 1 dI 1 /dt is generated, opposing the change in the current through L 1 . Similarly, a voltage L 2 dI 2 /dt is generated opposing the change in the current through L 2 (note that before transistor 230 is turned on, the current through L 2 is conducted through the body diode of transistor 230 ).

The current changes through parasitic inductances L 1 and L 2 may occur over times on the order of a few or tens of nanoseconds, with current change rates on the order of amps per nanosecond. Thus, during the transition from the first state to the second state, PVDD may overshoot PVIN by as much as L 1 |dI 1 /dt|. Similarly, PVSS may undershoot PGND by as much as L 2 |dI 2 /dt|. As noted above, before transistor 230 is turned on, the current through L 2 is conducted through the body diode of transistor 230 , so V x may under-shoot by as much as V D +L 2 dI/dt, where V D is the body diode forward on voltage.

A number of methods may be used to reduce the bouncing voltage. Parasitic inductances L 1 and L 2 may be reduced by improving the packaging and the printed circuit board layout, and by reducing the ESL of the decoupling capacitor. However, doing so may add significant cost to the systems.

Other methods include reducing the gate drive voltage slew rate to increase the time over which the current through the parasitic inductances. changes (and thus reducing the corresponding dI/dt). However, this method may significantly increase the dead time. Referring to FIGS. 7 and 1 , if the voltage to the gate of transistor 120 is increased slowly, there is almost no effect on the current through inductance L 1 until t 2 , the point at which V x drops below PVSS (e.g., ground). Between t 2 and t 3 , the current through inductance L 1 is reduced from I p to zero and the current through inductance L 2 is increased from zero to I p . As FIG. 7 shows, reducing the gate drive voltage slew rate only affects approximately ¼ of the switching time. Thus, a relatively small reduction in dI/dt is obtained for a relatively large increase in dead time. Further, since the transistors are operated in the high R DS-on region during the dead time, the efficiency of the converter is reduced.

The current inventors recognized that power regulators incorporating multiple switches for one or more of the upper or lower drivers may provide a better solution than existing systems. For example, multiple switches may be used to reduce or eliminate the problems due to power supply overshoot and undershoot outlined above.

FIG. 3 shows a power regulator according to an embodiment. A DC/DC converter 300 includes a PWM controller 310 in communication with an upper driver 320 and a lower driver 330 . Upper driver 320 includes a first switch 322 and a second switch 324 . PWM controller 310 controls first switch 322 via a switch terminal 323 and controls second switch 324 via a switch terminal 325 . Lower driver 330 includes a switch 332 . PWM controller 310 controls switch 332 via a switch terminal 333 . PWM controller 310 controls first switch 322 , second switch 324 , and switch 332 to generate current I 1 and I 2 alternately to provide a direct current output to a load 390 via a filter 370 .

Providing multiple switches in upper driver 320 may provide a number of benefits. For example, first switch 322 may be more efficient (e.g., have a lower power dissipation) than second switch 324 , while second switch 324 may have a higher on-state breakdown voltage. System 300 may be implemented so that first switch 322 carries most of the current I 1 , but second switch 324 experiences the most significant on-state voltage stress. Thus, system 300 may be both efficient and reliable.

In some implementations, first switch 322 and second switch 324 may be implemented as power transistors. FIG. 4 shows an implementation of a DC/DC converter system 400 where a first switch of an upper driver 420 is implemented as an NMOS transistor 422 and a second switch is implemented as a PMOS transistor 424 . In some implementations, transistor 422 is larger than transistor 424 , so that during the bulk of the duty cycle of upper driver 420 , transistor 422 carries the majority of the current. The optimum sizes of transistor 422 and transistor 424 and associated R DS-on values are process dependent. In some implementations, transistor 422 may be configured to carry between about 70% and about 95% of the current, although other implementations are possible. Converter 400 includes a bootstrap pre-driver 415 and a bootstrap capacitor C BS 418 in communication with a gate 423 of transistor 422 .

Converter 400 includes a PWM controller 410 to control the duty cycle of upper driver 420 and lower driver 430 (e.g., to turn transistor 422 , transistor 424 and transistor 432 on and off at the desired times and with the desired slew rates).

As noted above, NMOS transistors may be less able to withstand voltage stress in the on state than PMOS transistors, due to a lower on-state breakdown voltage. In converters such as converter system 200 of FIG. 2A , the highest voltage stress on the upper driver occurs when the current is being switched from the upper driver to the lower driver. In an implementation, the reliability of converter system 400 may be improved by switching off upper driver 420 as illustrated in method 500 of FIG. 5 .

Prior to turning off upper driver 420 , NMOS transistor 422 (with lower R DS-on ) carries the majority of the current ( 510 ). For example, transistor 422 may carry about 90% of the current while transistor 424 carries about 10% of the current. In order to turn off upper driver 420 , NMOS transistor 422 may first be turned off relatively quickly ( 520 ). Subsequently, all current in upper driver 420 is being carried by PMOS transistor 424 ( 530 ). PMOS transistor 424 is then turned off relatively slowly ( 540 ). Turning off transistor 422 relatively quickly reduces the contribution to the dead time related to turning off transistor 422 . However, since I 1 does not change significantly when transistor 422 is turned off, voltage bouncing does not unduly stress transistor 422 in its on state.

Turning off transistor 424 relatively slowly increases the time over which the current I 1 changes. Thus, voltage bouncing is reduced. Further, since PMOS transistor 424 has an appreciably higher breakdown voltage in the on state than NMOS transistor 422 , it is better able to withstand voltage transients without breakdown.

As a result, converter 400 may be more reliable than converter 200 . However, since NMOS transistor 422 (which has a lower value of R DS-on ) carries the majority of the current during most of the duty cycle of the upper driver, the efficiency of converter 400 may not be unduly compromised.

Another implementation of a power regulator with an upper and/or lower driver including multiple switches is shown in FIG. 8 . FIG. 8 shows a DC/DC converter system 800 with an upper driver 820 including a first PMOS transistor 822 and a second PMOS transistor 824 . Note that in some implementations, both first transistor 822 and second transistor 824 may be implemented as NMOS transistors. R DS-on of first transistor 822 is less than R DS-on of second transistor 824 , where the optimal relative values of R DS-on for transistors 822 and 824 is process dependent. In an exemplary implementation, the ratio of the value of R DS-on for transistor 822 to the value of R DS-on for transistor 824 is about 1 to 9.

System 800 further includes time and slew rate controllers 812 A through 812 D (referred to generally as controllers 812 ). Controllers 812 are used to control the timing and rate of change of the voltage applied to the gates of transistors 822 , 824 , 832 , and 834 . Controllers 812 are shown separate from PWM controller 810 in FIG. 8 ; however, they may be integrated with PWM controller 810 .

Upper driver 820 and lower driver 830 may be turned off and on as described below, so that over- and under-shooting of PVDD and PVSS is reduced or eliminated. FIG. 9 shows V 1a , V 1b , V x , and I 1 from a time t o prior to turning off upper driver 820 to a time t 5 when lower driver 830 is turned on.

From t 0 to t 1 , upper driver 820 is on, with the majority of the current flowing through transistor 822 (with a lower value of R DS-on ). To turn off upper driver 820 , time and slew rate controller 812 A first turns off transistor 822 by increasing the voltage V 1a at the gate of transistor 822 as shown over a time period from t 1 to t 2 .

As FIG. 9 illustrates, V x drops to a voltage below zero volts very quickly. Controller 812 B then turns off transistor 824 slowly by increasing the voltage V 1b at the gate of transistor 824 over the time period from t 2 to t 4 .

As FIG. 9 shows, I 1 and I 2 change from I p to zero and zero to I p (respectively) over a time period from t 2 to t 3 .

The method described above may be used to effectively reduce dI/dt through the parasitic inductances (and thus reduce or eliminate over- and under-shoot problems in systems such as system 800 ) by allowing the current to change from I p to zero over the time between t 2 and t 3 . However, the method does not lead to a large increase in the dead time, since the transition time between t 1 and t 2 (the time over which V x decreases to zero) is much smaller than that achieved using available systems.

At time t 4 , lower driver 830 may be turned on. Since I 2 increases to I p prior to turning on lower driver 830 (it is conducted through the body diode of transistor 832 and/or transistor 834 ), controllers 812 C and 812 D may turn on transistors 832 and 834 at the same time. In other implementations, controllers 812 C and 812 D may turn on the transistors differently.

Transistor 832 of lower driver 830 may have a smaller value of R DS-on than transistor 834 . To turn off lower driver 830 , controller 812 C may turn off transistor 832 first and quickly, while controller 812 D may turn off transistor 834 more slowly. Finally, to turn on upper driver 820 , controllers 812 A and 812 B may turn on transistors 822 and 824 either at the same time, or may turn them on differently. Note that although controllers 812 A through 812 D are shown as separate in FIG. 8 , they need not be.

Although FIG. 8 shows transistors 822 and 824 both implemented as PMOS transistors and transistors 832 and 834 both implemented as NMOS transistors, other implementations are possible. For example, the implementation of FIG. 4 (and similar implementations) may be used to reduce or eliminate overshoot and undershoot as described above.

FIG. 10 shows an additional implementation of a system 1000 where more than two transistors may be used in an upper driver 1020 and/or a lower driver 1030 . For example, upper driver 1020 includes M transistors 1022 - 1 through 1022 -M, where transistors 1022 - 1 through 1022 -(M- 1 ) are NMOS transistors and transistor 1022 -M is a PMOS transistor. Lower driver 1030 is shown as including one NMOS transistor 1032 , although other implementations are possible.

A system such as system 1000 may be used as described above to increase the reliability of the system and to reduce or eliminate over- and under-shoot of PVDD and PVSS. For example, transistors 1022 - 1 through 1022 -(M- 1 ) may carry the bulk of the current during the time when upper driver 1020 is on. In order to turn off upper driver 1020 , transistors 1022 - 1 through 1022 -(M- 1 ) may be turned off first. Transistor 1022 -M may be subsequently turned off. In such an implementation, system 1000 may be more reliable (since PMOS transistor 1022 -M has a higher on-state breakdown voltage than NMOS transistors 1022 - 1 through 1022 -(M- 1 )), and may also be efficient (since NMOS transistors 1022 - 1 through 1022 -(M- 1 ) have a lower R DS-on than transistor 1022 -M).

System 1000 may include a time and slew rate controller 1012 (which may comprise multiple controllers or a single controller) to control when and over what time scale transistors 1022 - 1 through 1022 -M are turned on and off. In such an implementation, transistors 1022 - 1 through 1022 -M may be turned on and off to reduce or eliminate over- and under-shooting as described above with reference to FIGS. 8 and 9 . For example, to turn off upper driver 1020 , controller 1012 may turn off transistors 1022 - 1 through 1022 -(M- 1 ) quickly, then turn off transistor 1022 -M slowly. Transistors 1022 - 1 through 1022 -(M- 1 ) may be turned off in sequence, or there may be some or complete overlap in the times over which they are turned off.

A number of implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, different combinations of PMOS and NMOS transistors may be used. The power regulator systems (e.g., DC/DC converter systems) may include different numbers of transistors than those illustrated in the upper and/or lower drivers. Different types of switches may be used. For example, other types of transistors such as bipolar transistors may be used in some implementations. Accordingly, other implementations are within the scope of the following claims.