High speed switch

This application claims the benefit of U.S. Provisional Application No. 60/495,575, filed Aug. 14, 2003, the disclosure of which is hereby incorporated by reference.

1. Field of the Invention

The present invention relates to electronics. More specifically, the present invention relates to switches.

2. Description of the Related Art

Analog to digital converters are widely used for converting analog signals to corresponding digital signals for many electronic circuits. For example, a high resolution, high speed analog to digital converter (ADC) may find application in broadband communications, video circuits, radar, and electronic warfare applications. In the field of analog to digital conversion, there continue to be many driving goals, such as speed, increased number of bits (relating to dynamic range and spur-free operation), power consumption, and size. Two of the most critical specifications remain speed and dynamic range.

The fastest ADC architecture is called “flash” conversion. A flash ADC produces an N-bit digital output in one step using a comparator bank comprised of 2 N −1 parallel comparators. This architecture, however, is limited in dynamic range to about 8 bits, since the number of comparators grows rapidly as the number of bits N becomes larger. The next fastest converter technique is a subranging pipelined architecture.

Subranging ADCs typically use a low resolution flash quantizer during a first stage or “coarse pass” to convert an analog input signal into the most significant bits (MSB) of its digital value. An analog version of the MSB word, generated by a digital analog converter (DAC), is then subtracted from the input signal at a summing node to produce a residue or residual signal. The residue signal is amplified by an amplifier, and subsequently digitized by one or more additional stages or “fine passes” to produce the least significant bits of the input signal. The digital words produced by each stage are then combined by digital error correcting circuitry to produce a digital output representing the original analog input signal.

In a subranging ADC, the summing node is perhaps the most critical node in the chain. This is because an error appearing at the summing node cannot be corrected by the error correction circuit and will therefore appear as an error in the digital output. The problem that must be overcome is that when the input sample and hold (S/H) circuit begins its next sample, the quantizer and DAC have not reached equilibrium, resulting in a large voltage swing at the summing node. This causes some of the internal stages of the following amplifier to go into saturation. Once this happens, the settling time of the amplifier is lengthened considerably and the speed of conversion is significantly degraded.

A switch is typically used to isolate the amplifier from the summing node during the period when the driving circuits have not reached equilibrium. This switch must switch and settle rapidly. It must also provide isolation when off and provide linear operation when on. Prior art implementations, however, either perturb the summing node by capacitively coupling charge or affect the settling time by switching input stages within the amplifier.

Hence, there is a need in the art for an improved switch offering faster speed and greater accuracy than prior art switches.

The need in the art is addressed by the high speed switch of the present invention. The novel switch includes an input circuit having a transistor Q 1 for receiving an input signal, a first mechanism for providing a path from an output of Q 1 to an output terminal, and a second mechanism for receiving a control signal and in accordance therewith reducing the conductivity of the path during a mute mode. The first mechanism includes a first circuit for providing a first path from an output of Q 1 to a first node, and a second circuit for providing a second path connecting the first node to the output terminal. The second mechanism is adapted to apply a signal to the first node during the mute mode such that the first and second circuits are off or partially conducting. The switch also includes a circuit for clamping the first node to a first predetermined voltage during the mute mode.

FIG. 1 is a simplified block diagram of a typical subranging analog to digital converter.

FIG. 2 is a simplified schematic of a conventional system for isolating the amplifier from summing node fluctuations.

FIG. 3 is a simplified schematic of a conventional switch implementation for summing node isolation.

FIG. 4 is a simplified schematic of another conventional amplifier isolation circuit.

FIG. 5 is a simplified schematic of an illustrative embodiment of a switch designed in accordance with the teachings of the present invention.

FIG. 6 is a simplified schematic of an illustrative embodiment of a multiplexer designed in accordance with the teachings of the present invention.

FIG. 7 is a simplified schematic of an alternative illustrative embodiment of a multiplexer designed in accordance with the teachings of the present invention, showing how diode bridges can be used as the gating elements.

FIG. 8 is a simplified schematic of an alternative illustrative embodiment of a multiplexer designed in accordance with the teachings of the present invention, showing a BiCMOS implementation.

Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.

While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.

FIG. 1 is a simplified block diagram of a typical subranging analog to digital converter (ADC) 10 . The example shown is a two stage ADC 10 having a first stage or “coarse pass” 14 , and a second stage or “fine pass” 16 . A subranging ADC may have additional stages, similar to the first stage 14 , connected in series between the coarse pass 14 and the fine pass 16 . An analog input signal V I is applied to an input terminal 11 connected to a sample and hold (S/H) circuit 12 , which outputs a voltage V SH . The sampled voltage V SH is input to the first subranging stage 14 , which includes a first quantizer 20 , typically comprised of a comparator bank 22 and latches 24 , for digitizing the input signal to K bits; a digital to analog converter (DAC) 30 for generating an analog version of the K-bit word; and a summing node 32 for generating a residue signal by subtracting the output of the DAC 30 from the sampled input signal V SH , which is first converted to a current by a resistor R SH . The residue signal is then amplified by an amplifier 34 and digitized by the second stage 16 , which includes a second quantizer 40 , comprised of a comparator bank 42 and latches 44 , for generating an L-bit digital output. Error correction logic 18 combines the K-bit and L-bit words to produce an N-bit digital output representing the original analog input signal.

The amplifier 34 is typically a closed loop amplifier including an operational amplifier (op amp) 36 having gain A 1 , and two resistors R I and R F connected in a feedback configuration, with R F connected between the negative input terminal and the output terminal of the op amp 36 and R I connected between the negative input terminal and ground. The signal from the summing node 32 is applied to the positive input terminal of the op amp 36 .

As discussed above, the summing node 32 is perhaps the most critical node in the chain. In a typical implementation, when V SH and the DAC outputs are stable, the summing node voltage will be +/−64 mV for an input V I range of +/−2.048 V. The output of the amplifier 34 , which usually has a gain of 16 or more, will then be V O =+/−0.064×16=+/−1.024 V. The problem that must be overcome is that when the S/H circuit 12 begins its next sample, the comparators 22 , latches 24 and DAC 30 have not reached equilibrium. Therefore, the voltage at the summing node 32 can swing easily +/−0.4 V or so about its designed common mode quiescent point. As an example, assume the summing node voltage swings to −0.4 V. Then the output of the amplifier 34 would try to go to V O =−0.4×16=−6.4 V. This, however, is not possible since the amplifier 34 is designed to be linear over a range close to +/−1.024 V. The result of this inconsistency is that some of the internal stages of the amplifier 34 will saturate. Once this happens, the settling time of the amplifier 34 is lengthened considerably and the speed of conversion is significantly degraded. This is because when the amplifier 34 saturates, it goes open loop and the input differential pair can flip causing a large thermal gradient. This causes an unacceptably long recovery time for the loop to return to stable steady-state closed loop operation.

In implementing the DAC 30 to amplifier 34 circuit interface, steps are therefore taken to minimize the voltage swing at the summing node 32 . About the best that can be done while maintaining distortion-free operation is to limit the voltage swing to about +/−0.4 V assuming diode clamps at the summing node 32 . This is still too great a swing for the amplifier 34 to handle since the output of the amplifier 34 would be V O =0.4 V×16=6.4 V. The prior art generally attempts to isolate the amplifier 34 from the summing node 32 with switches as shown in FIG. 2 .

FIG. 2 is a simplified schematic of a conventional system for isolating the amplifier 34 from summing node fluctuations. A differential implementation is shown, with differential input signals V CM +V SH and V CM −V SH (where V CM is the common mode voltage) each connected to a summing node 32 and 32 ′, respectively, through a resistor R SH and R′ SH , respectively; and DAC outputs I DAC and Ī DAC each connected to a summing node 32 and 32 ′, respectively. Two clamping diodes D C1 and D C2 are each connected between the two summing nodes 32 and 32 ′, D C1 having an anode connected to the first summing node 32 and a cathode connected to the second summing node 32 ′, and D C2 having an a node connected to the second summing node 32 ′ and a cathode connected to the first summing node 32 .

A switch 50 , 50 ′ is added to each differential leg, between the summing node 32 , 32 ′ and the amplifier 34 . Each switch 50 includes two input terminal 52 and 54 , a first input terminal 52 connected to the summing node 32 and the second input terminal 54 connected to the common mode voltage V CM ; and an output terminal 56 connected to an input of the amplifier 34 (labels for the second switch 50 ′ are the same as for the first switch 50 , followed by a prime). The output terminal 56 of the first switch 50 is connected to the positive input terminal of a first op amp 36 of the amplifier 34 , and the output terminal 56 ′ of the second switch 50 ′ is connected to the positive input terminal of a second op amp 36 ′ of the amplifier 34 . A resistor R I connects the negative input terminals of the op amps 36 and 36 ′, a resistor R F connects the negative input terminal and output terminal of op amp 36 , and a resistor R′ F connects the negative input terminal and output terminal of op amp 36 ′.

When the S/H output V SH and DAC outputs I DAC and Ī DAC are stable, the switches 50 and 50 ′ connect to the first input terminals 52 and 52 ′, and the amplifier 34 will operate in its linear region. When it is time to enable the next sample, the switches 50 and 50 ′ are moved to the second input terminals 54 and 54 ′, isolating the inputs of the amplifier 34 from the perturbations of the summing nodes 32 and 32 ′.

This switch operation allows the amplifier 34 to always operate in its linear mode. The switches 50 and 50 ′ must switch and settle rapidly. They must also provide isolation when off and provide linear operation when on. FIG. 3 is a simplified schematic of a conventional switch implementation 50 A for this application. A single channel is shown for simplicity. The output of the DAC I DAC and the output of the S/H V SH (through a resistor R SH ) are connected to the summing node 32 . A switch 50 A is connected between the summing node 32 and the input to the amplifier 34 . In this design, the switch action is accomplished by two FET devices M S1 , and M S2 . (The switch could, of course, be implemented in some other technology and is not limited to FETs.) The transistor M S1 , is connected between the summing node 32 and the input to the amplifier 34 , and M S2 is connected between the input to the amplifier 34 and ground. A control signal V SW is applied to the base of M S1 , and its complement (generated by an inverter 60 ) is applied to the base of M S2 .

In operation, when the switch 50 A is in an ‘on’ or ‘active’ mode (as determined by the control signal V SW ), M S1 is on and MS 2 is off, and the switch 50 A connects the summing node 32 to the input of amplifier 34 (similar to the switch 50 in the first position 52 in FIG. 2 ). When the switch 50 A is in an ‘off’ or ‘mute mode, M S1 is off and M S2 is on, and the summing node 32 is isolated from the amplifier 34 (similar to the switch 50 in the second position 54 in FIG. 2 ).

The fundamental problem with this implementation is the switching voltage V SW on the gates of M S1 , and M S2 will couple to the summing node 32 because of the rather large gate to source and gate to drain capacitances. The induced glitch will take several tens of nanoseconds to settle to the accuracy required, slowing down the overall speed of the ADC. There are other switch implementations for isolating the summing node 32 from the amplifier 34 , but all tend to perturb the summing node 32 when the switch 50 goes from the mute mode to the active mode.

FIG. 4 is a simplified schematic of another conventional amplifier isolation circuit 34 A, as described in U.S. Pat. No. 4,763,107, entitled “SUBRANGING ANALOG-TO-DIGITAL CONVERTER WITH MULTIPLEXED INPUT AMPLIFIER ISOLATION CIRCUIT BETWEEN SUBTRACTION NODE AND LSB ENCODER,” the teachings of which are incorporated herein by reference. This approach adds a switch 74 inside the amplifier 34 A to switch between two input circuits 70 and 72 , the first input circuit 70 coupled to the DAC and S/H, and the other input circuit 72 coupled to ground.

The amplifier 34 A includes two input circuits 70 and 72 , and a switching circuit 74 adapted to receive a control signal V SW and in accordance therewith couple either the first input circuit 70 or the second input circuit 72 to an op amp 76 . The first input circuit 70 includes a differential input pair Q S1 and Q S2 . The base of Q S1 is connected to the output from the DAC, and the collector is coupled to a current source I S1 and the negative terminal of the op amp 76 . The base of Q S2 is connected to the output from the S/H through a resistor R I1 , and to the output terminal of the op amp 76 through a resistor R F1 , and the collector is coupled to a current source I S2 and the positive terminal of the op amp 76 . The second input circuit 72 includes a differential input pair Q S3 and Q S4 . The base of Q S3 is connected to ground, and the collector is coupled to I S1 and the negative terminal of the op amp 76 . The base of Q S4 is connected to ground through a resistor R I2 and to the output terminal of the op amp 76 through a resistor R F1 , and the collector is coupled to I S2 and the positive terminal of the op amp 76 . The switching circuit 74 includes a differential pair Q S5 and Q S6 , having emitters connected in common to a current source I S3 , and bases connected to complementary control signals V SW and {overscore (V)} SW , respectively. The collector of Q S5 is connected to the common emitters of Q S1 and Q S2 , and the collector of Q S6 is connected to the common emitters of Q S3 and Q S4 .

This approach tends to impact the settling time when switched from mute to active since the switching circuitry is located within the closed loop of the amplifier 34 A. This circuit, while keeping the op amp 76 from going into saturation, requires longer to settle because the switching is performed inside the loop. The overall loop must settle and this settling time is unacceptable and prohibitive for high speed applications.

The present invention describes a fast settling single pole double throw (SPDT) switch that provides over 60 dB isolation between the summing node and the following amplifier during the period when the driving circuits have not reached equilibrium. It also does not perturb the amplifier input node when switching either from on to off or from off to on. The switch employs bootstrapping techniques to provide excellent linearity, precision gain and stability. It is an open loop configuration, which is inherently very broadband, and has been designed specifically to switch from off to on very quickly therefore settling very rapidly. This allows the switch to be used in very high speed applications. The summing node common mode voltage is held constant by the switch for both the active (on) and mute (off) modes. Because the common mode voltage is constant, fast recovery (settling) of the following amplifier when switching from mute to active is achieved.

FIG. 5 is a simplified schematic of an illustrative embodiment of a switch 100 designed in accordance with the teachings of the present invention. The novel switch 100 includes an input circuit 102 , comprised of a transistor Q 1 biased at the emitter with a current source I 1 , and an output circuit 104 , including a transistor Q 4 biasedat the emitter with a current source I 3 . An input signal V IN (from the summing node) is applied to an input terminal 106 at the base of Q 1 , and an output signal V OUT (which is input to the amplifier) is taken at an output terminal 108 at the emitter of Q 4 .

In accordance with the teachings of the present invention, the switch 100 includes a circuit 109 for providing a first path connecting the emitter of Q 1 to the base of Q 4 , and a switching circuit 110 adapted to receive a control signal V S1 and in accordance therewith reduce the conductivity of the path to attenuate the signal input to Q 4 during the mute mode. The transistor Q 4 provides a second path connecting the output from the first path circuit 109 to the output terminal 108 , and the switching circuit 110 may also be adapted to aid in turning off or reducing the conductivity of the second path during the mute mode to further attenuate any signal that passes through the first path.

In the illustrative embodiment, the circuit 109 is a diode D 1 having an anode connected to the base of Q 4 and a cathode connected to the emitter of Q 1 , and the switching circuit 110 is a current switch comprised of a differential pair Q 2 and Q 3 , having emitters connected in common to a current source I 2 . The base of Q 2 is coupled to the control signal V S1 and the collector is coupled to the cathode of D 1 . The base of Q 3 is coupled to the control signal {overscore (V)} S1 , which is the complement of V S1 , and the collector is coupled to the anode of D 1 . The control signals V S1 and {overscore (V)} S1 are designed to turn Q 2 on and Q 3 off during the active mode, and turn Q 2 off and Q 3 on during the mute mode.

The novel switch 100 also includes a circuit 112 adapted to clamp the base of Q 4 to a predetermined voltage to turn off or reduce the conductivity of Q 4 during the mute mode. The circuit 112 includes a transistor Q 7 having a base coupled to a control signal {overscore (V)} S2 , an emitter connected to the base of Q 4 , and a collector coupled to the collector of Q 1 . The control signal {overscore (V)} S2 is a level shifted version of {overscore (V)} S1 , so it switches between the active and mute modes at the same time, but the voltage levels are chosen to turn Q 7 on and turn Q 4 off or slightly conducting during the mute mode, and turn Q 7 off and Q 4 on during the active mode.

In the embodiment of FIG. 5 , which is designed for a summing node isolation application, the output circuit 104 also includes a transistor Q 5 adapted to apply a predefined voltage to the output terminal 108 when the input circuit 102 is in the mute mode. The transistor Q 5 has a base coupled to a control signal {overscore (V)} S3 , an emitter connected to the output node 108 , and a collector coupled to the collector of Q 4 . The control signal {overscore (V)} S3 is a level shifted version of {overscore (V)} S1 , so it switches between the active and mute modes at the same time, but the voltage levels are chosen to turn Q 5 off during the active mode, and turn Q 5 on and apply a desired voltage to the output node 108 during the mute mode.

The switch 100 also includes bootstrapping circuits 116 and 118 for reducing distortions due to the Early effect (or channel length modulation) by regulating the voltages across the transistors in the signal path such that those voltages remain constant. This can be implemented using bootstrapping circuits that tie the voltage at the collector (or source/drain) of a transistor to a voltage in the signal path. In the input circuit 102 , the circuit 116 bootstraps the transistors Q 1 and Q 7 . The circuit 116 includes a transistor Q 8 having an emitter coupled to the collectors of Q 1 and Q 7 , a collector coupled to a DC power supply V CC , and a base coupled to a current source I 4 . A level shifting circuit, comprised of two diodes D 2 and D 3 in series, level shifts the voltage at the base of Q 4 to the base of Q 8 .

Similarly, the circuit 118 bootstraps the transistors Q 4 and Q 5 . The circuit 118 includes a transistor Q 6 having an emitter coupled to the collectors of Q 4 and Q 5 , a collector coupled to a DC power supply V CC , and a base coupled to a current source I 5 . A level shifting circuit, comprised of three diodes D 4 , D 5 and D 6 in series, level shifts the voltage at the output node 108 to the base of Q 6 .

Note that the illustrative bootstrapping circuits 116 and 118 shown in FIG. 5 are open loop, feedback, and feed forward configurations. The invention, however, is not limited thereto. Other bootstrapping techniques may be used without departing from the scope of the present teachings.

The circuit's operation will now be described using sample values as listed in the following table:

V CC   +5 V V BE   0.8 V (when transistor is on or conducting) V DIODE   0.8 V I1   1.0 mA I2   3.0 mA I3   3.0 mA I4   2.0 mA I5   2.0 mA V S1 −2.4 V (active) −2.8 V (mute) {overscore (V)} S1 −2.8 V (active) −2.4 V (mute) {overscore (V)} S2 −1.2 V (active) −0.4 V (mute) {overscore (V)} S3 −1.8 V (active) −1.0 V (mute)

where V BE is the base to emitter voltage across a transistor and V DIODE is the voltage drop across a diode.

For this example, assume the input V IN to the switch is in the range of −1 V+/−64 mV. To optimize settling time, the output V OUT of the switch is designed to be −1.8 V+/−64 mV. Therefore, the amplifier 34 following the switch 100 will work around a common mode (CM) voltage of −1.8 V.

First, assume the circuit 100 is in the active mode. This mode is similar to switch position 52 in FIG. 2 . In the active mode, Q 2 is on and Q 3 is off, Q 7 is off and Q 5 is off. The emitter of Q 1 is at −1.8 V+/−64 mV. The +/−64 mV represents the LSB (least significant bit) size of the DAC 30 . (This assumes K=5 for the first stage.) Since Q 2 is on, the current I 4 will flow through D 1 ; therefore, the base of Q 4 will be at −1.0 V +/−64 mV (remember that Q 7 is off). With the base of Q 4 at −1.0 V+/−64 mV, the emitter of Q 4 will be −1.8 V+/−64 mV since Q 5 is off. So the output voltage V OUT =−1.8 V+/−64 mV, where −1.8 V is the designed input common mode voltage for the following amplifier 34 .

Now switch to the mute mode. This mode is analogous to switch position 54 in FIG. 2 . Recall that, because of the delay between the DAC and the S/H output, the summing node voltage can experience large swings. If diode clamps are implemented (as shown in FIG. 2 ), the differential voltage swings will be limited to +/−0.4 V. The design goal for the mute mode is to allow the switch input voltage V IN to vary over a range of −1.0 V+/−0.4 V, while holding the switch output voltage V OUT at the desired input common mode (CM) voltage of the amplifier (−1.8 V). By holding the input to the amplifier constant at the CM voltage, the amplifier will not go into saturation, and once the switch 100 is placed in the active mode, there will be no delay in the amplifier settling time.

In the mute mode, Q 2 is off, Q 3 is on, Q 7 is on and Q 5 is on. As a result, there are two levels of isolation provided by this switch structure in the mute mode. Starting at Q 7 , with the base of Q 7 =−0.4 V, the emitter of Q 7 =−1.2 V since Q 3 is on. With the emitter of Q 1 at −1.8 V+/−64 mV, the voltage across D 1 is −0.6 V, which means that it is conducting but not fully (it is in a very high resistance part of its I/V curve). Since Q 7 is on, the emitter of Q 7 is held at −1.2 V and any variations of the input voltage are greatly attenuated. Now, looking at the output section, Q 5 is on and its emitter is clamped at −1.8 V since the mute voltage on its base is −1.0 V. This holds the output voltage V OUT at the desired CM voltage of −1.8 V. Since the base of Q 4 is −1.2 V and the emitter of Q 4 is −1.8 V, it is also slightly conducting. Since Q 5 is on, any small variations on the base of Q 4 will again be attenuated.

Looking at the signal path during the mute mode, Q 1 is always operating in its linear mode, D 1 is slightly conducting and Q 4 is slightly conducting. Partial conductivity is allowed in D 1 and Q 4 because there is still one level of isolation at Q 5 to maintain 60 dB of isolation at the output of the amplifier. The switch has approximately 60 dB of attenuation in the mute mode, far in excess of what is needed to keep the amplifier from going into saturation. The reason for allowing the components in the signal path to conduct slightly is that, when switched into the active mode, they have almost no recovery time and therefore no delay. This makes the time to settle extremely short.

In the active mode, design techniques have been implemented in this invention to further increase its linearity. Both Q 1 and Q 4 are bootstrapped to minimize the Early effect and to improve not only the linearity, gain accuracy and stability but also the operating bandwidth of the signal path. Additionally, the noise of the open loop structure in active mode is very low so that it does not degrade the SNR (signal to noise ratio) of the ADC as opposed to conventional circuits.

Thus, the present invention isolates the summing node from the input of the amplifier during the period when the driving circuits have not reached equilibrium. Even more importantly, when it switches from the mute mode to the active mode it does not perturb the summing node common mode voltages. Benefits of this invention include fast switching and settling from mute-to-active and active-to-mute modes, excellent linearity, gain accuracy and low harmonic distortion in the active mode. The circuit exhibits low noise in the active mode and has minimum delay. In the mute mode it has four areas of isolation, as it forms a series shunt-series shunt isolation path, allowing for large summing node transients without compromising isolation.

While the invention has thus been described with reference to a specific application of the SPDT switch, it should be pointed out that a more general, symmetric, SPDT switch is a direct extension of this implementation. FIG. 6 shows how the circuit can be modified to function as a two input multiplexer (MUX).

FIG. 6 is a simplified schematic of an illustrative embodiment of a multiplexer 150 designed in accordance with the teachings of the present invention. By replicating the input stage 102 of the switch 100 of FIG. 5 , as previously described, as a mirror image, and connecting it as an input to Q 5 (labeled Q 4 ′ in FIG. 6 ), the circuit 150 operates with complete symmetry.

The two input MUX 150 includes two input circuits 102 and 102 ′, and an output circuit 104 ′. The output circuit 104 ′ includes two output transistors Q 4 and Q 4 ′ having bases coupled to the outputs of the input circuits 102 and 102 ′, respectively, and emitters connected in common to a current source I 3 . The output terminal 108 is coupled to the emitters of Q 4 and Q 4 ′. The output circuit 104 ′ also includes a bootstrapping circuit 118 ′ comprised of transistors Q 6 and Q 6 ′ having emitters coupled to the collectors of Q 4 and Q 4 ′, respectively, collectors connected to V CC , and bases connected in common to a current source I 5 . A level shifting circuit comprised of three diodes D 4 , D 5 , and D 6 in series (the cathode of D 4 is connected to the output terminal 108 ) level shifts the voltage V OUT at the output terminal 108 to the bases of Q 6 and Q 6 ′.

The first input circuit 102 is identical to that shown in FIG. 5 , except the base of Q 7 is now connected to the anode of D 4 . The second input circuit 102 ′ is identical to the first circuit 102 , except a first input signal V IN1 is applied to the input terminal 106 of circuit 102 and a second input signal V IN2 is applied to the input terminal 106 ′ of circuit 102 ′, and a first set of control signals V S1 and {overscore (V)} S1 is applied to the switching circuit 110 of circuit 102 and a second set of control signals V S2 and {overscore (V)} S2 is applied to the switching circuit 110 ′ of circuit 102 ′ (for a two input MUX, V S2 ={overscore (V)} S1 and {overscore (V)} S2 =V S1 ). The components of circuit 102 ′ are labeled similar to the corresponding components of circuit 102 , followed by a prime (′).

The operation of the MUX 150 is similar to the switch 100 of FIG. 5 , except that instead of switching V OUT between V IN and the voltage defined by {overscore (V)} S3 , the MUX 150 switches V OUT between V IN1 and V IN2 . The bases of Q 7 and Q 7 ′ are now connected to the anode of D 4 . This effectively clamps the emitter of the transistor in the “off” side to equal V OUT , thereby ensuring that either Q 4 or Q 4 ′ (whichever side is turned off) is always held in the off state. The control signals at the bases of Q 2 , Q 3 and Q 2 ′, Q 3 ′ operate at current mode logic levels and therefore contribute low transient coupling to the output. The following table gives a sample switching voltage truth table:

FIG. 7 is a simplified schematic of an alternative illustrative embodiment of a multiplexer 150 A designed in accordance with the teachings of the present invention, showing how diode bridges can be used as the gating elements. The two input MUX 150 A includes two symmetrical input circuits 102 A and 102 A′, and an output circuit 104 A. The input circuit 102 A is similar to the input circuit 102 of FIG. 6 , except the diode D 1 and transistor Q 4 , which connected the output of Q 1 to the output terminal 108 , is now replaced with a diode bridge 109 A, comprised of diodes D 7 , D 8 , D 9 , and D 10 . The cathode of D 9 and anode of D 7 are connected to the emitter of Q 1 . The cathode of D 10 and anode of D 8 are connected to the output terminal 108 . The cathodes of D 7 and D 8 are connected to the collector of Q 2 . The anodes of D 9 and D 10 are connected to the emitter of Q 7 . The collector of Q 7 is connected to V CC instead of the bootstrapping circuit 116 , and the base is connected to the base of Q 6 (in the output circuit 104 A). Current sources 16 and 17 are added between V CC and the collectors of Q 3 and Q 2 , respectively.

The second input circuit 102 A′ is identical to the first circuit 102 A, except a first input signal V IN1 is applied to the input terminal 106 of circuit 102 A and a second input signal V IN2 is applied to the input terminal 106 ′ of circuit 102 A′, a control signal V S1 is applied to Q 2 of circuit 102 A and to Q 3 ′ of circuit 102 A′, and a control signal {overscore (V)} S1 is applied to Q 3 of circuit 102 A and Q 2 ′ of circuit 102 A′. The components of circuit 102 A′ are labeled similar to the corresponding components of circuit 102 A, followed by a prime (′).

The output circuit 104 A includes a transistor Q 9 having a base connected to the output terminal 108 and an emitter connected to a current source I 3 , and a bootstrapping circuit 118 A comprised of a transistor Q 6 having an emitter coupled to the collector of Q 9 , a collector coupled to V CC , and a base coupled to a current source I 5 . A level shifting circuit comprised of two diodes D 4 and D 5 in series (the cathode of D 4 connected to the emitter of Q 9 ) level shift the voltage at the emitter of Q 9 to the base of Q 6 . A diode D 11 is connected with an anode at the collector of Q 2 and a cathode at the emitter of Q 9 , and a diode D 11 ′ is connected with an anode at the collector of Q 2 ′ and a cathode at the emitter of Q 9 .

If the control signal V S1 =logic1 and {overscore (V)} S1 =logic0, then Q 2 is on and Q 3 is off, and D 11 is off, therefore I 6 flows through the diode bridge 109 A. Since the diodes of the bridge 109 A are matched diode-connected transistors, their voltage drops are matched and the voltage on the cathode of D 10 is equal to the voltage on the cathode of D 9 . Therefore, V OUT =V IN1 −V BEQ1 , where V BEQ1 is the base to emitter voltage of Q 1 . Q 7 is off since the voltages on the anode of D 9 and on the base of Q 7 are equal. The other side of the MUX (the input circuit 102 A′ for the second input signal V IN2 ) is off since Q 2 ′ is off and Q 3 ′ is on, D 11 ′ is conducting, and therefore, the diode bridge 109 A′ is zero biased. This MUX 150 A is designed for maximum bandwidth and switching speed for low level signals. The following table gives sample values for the current sources in FIG. 7 :

FIG. 8 is a simplified schematic of an alternative illustrative embodiment of a multiplexer 150 B designed in accordance with the teachings of the present invention, showing a BiCMOS implementation. The two input MUX 150 B includes two symmetrical input circuits 102 B and 102 B′, and an output circuit 104 B. As in the embodiment of FIG. 6 , the input circuit 102 B includes an input transistor Q 1 biased at the emitter by a current source I 1 and a circuit 116 for bootstrapping the voltage across Q 1 . The diode D 1 , switching circuit 110 , and output transistor Q 4 (in FIG. 6 ) are replaced with a circuit 109 B for providing a path between the emitter of Q 1 and the output terminal 108 , and adapted to receive a control signal V S1 and in accordance therewith reduce the conductivity of the path to attenuate the signal applied to the output 108 .

The circuit 109 B includes two FET transistors M 1 and M 2 connected in series. The FETs can be either PMOS or NMOS technology. In the illustrative embodiment of FIG. 8 , M 1 and M 2 are PMOS FETs, with the source of M 1 connected to the emitter of Q 1 , the drain of M 1 connected to the source of M 2 , and the drain of M 2 connected to the output terminal 108 . The gates of M 1 and M 2 are coupled to the control signal V S1 , which is adapted to turn M 1 and M 2 on when the input circuit 102 B is in the active mode, and switch M 1 and M 2 off during the mute mode. The input circuit 102 B also includes a circuit 112 B adapted to receive a control signal {overscore (V)} S1 and in accordance therewith clamp the voltage at the node between M 1 and M 2 . In this embodiment, the circuit 112 B includes an FET M 3 having a drain connected to the node between M 1 and M 2 , a gate coupled to {overscore (V)} S1 , and a source connected to the emitter of a transistor Q 10 in the output circuit 104 B.

The second input circuit 102 B′ is identical to the first circuit 102 B, except a first input signal V IN1 is applied to the input terminal 106 of circuit 102 B and a second input signal V IN2 is applied to the input terminal 106 ′ of circuit 102 B′, and a first set of control signals V S1 and {overscore (V)} S1 is applied to circuits 109 B and 112 B, respectively, of circuit 102 B and a second set of control signals V S2 and {overscore (V)} S2 is applied to circuits 109 B′ and 112 B′, respectively, of circuit 102 B′ (for a two input MUX, V S2 ={overscore (V)} S1 and {overscore (V)} S2 =V S1 ). The components of circuit 102 B′ are labeled similar to the corresponding components of circuit 102 B, followed by a prime (′).

The output circuit 104 B includes a transistor Q 9 having a base connected to the output terminal 108 and an emitter connected to a current source I 3 , and a bootstrapping circuit 118 B comprised of a transistor Q 6 having an emitter coupled to the collector of Q 9 , a collector coupled to V CC , and a base coupled to a current source I 5 . A level shifting circuit comprised of two diodes D 4 and D 5 in series (the cathode of D 4 connected to the emitter of Q 9 ) level shift the voltage at the emitter of Q 9 to the base of Q 6 . The output circuit 104 B also includes a transistor Q 10 for applying a voltage V OUT to the source of M 3 . The base of Q 10 is connected to the base of Q 6 , the collector is connected to V CC , and the emitter is connected to the source of M 3 and to a current source I 8 .

Thus, when V S1 =logic1 and {overscore (V)} S1 =logic0, M 1 and M 2 are on, M 3 is off, and V OUT =V IN1 . When V S1 =logic0 and {overscore (V)} S1 =logic1, M 1 and M 2 are off, M 3 is on, and V OUT =V IN2 . M 3 acts as a shunt element to provide improved isolation for the “off” switch. In the “off” mode, M 3 provides a bias equal to V OUT at a low impedance to the drains of M 1 and M 2 , so that the on/off or off/on transients are small across the FET drain to source voltage V DS . These FETs are bootstrapped so that the FET control signals can be made as low as possible to minimize switching transients.

It should be clear to one of ordinary skill in the art that the circuits described above could be modified to function as multiple input MUXs by adding more input sections.

Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof.

It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.

Accordingly,