Circuit and method for driving a coil-armature device

The present invention relates to coil-armature devices and, more specifically, to a circuit and method for driving a coil-armature device in an energy efficient manner.

One common type of electromechanical switch used in a variety of different fields of technology includes the basic coil-armature device, such as, for example, a solenoid. The basic coil-armature device traditionally comprises a coil of wire, usually fashioned in cylindrical form, around some form of moveable core or armature. The introduction of an electric current through the coil of wire generates an electromagnetic field, which, in turn, attracts the moveable core, drawing it into the center of the coil. The movement of the armature is typically designed to interface a variety of different types of systems, such as, for example, an electrical contact or a valve.

Traditionally, a coil-armature device is activated by introducing a large initial current through the coil, thereby generating an electromagnetic field with sufficient strength to overcome system frictions and loads in order to rapidly attract the armature into the center of the coil. Once the armature is attracted to or retracted into the coil, the coil-generated electromagnetic field is maintained in order to hold the armature in place. However, the amount of power necessary to hold the armature in place after it has been retracted into the coil is but a fraction of the original amount of power necessary to draw the armature into the coil.

Typical coil-driving circuits apply a high level of current to the coil in order to initiate retraction of the armature. However, once the armature is retracted, these typical driving circuits continue to supply a high level of current to the coil to hold the armature in place. This use of excessive current to hold the armature in place not only results in a significant waste of energy, but also significant costs associated with the design and construction of a coil-armature device that is capable of handling high levels of current for an extended duration of time, as well as the buildup of heat associated with the high current levels.

The embodiments described hereinafter were developed in light of these and other problems identified by the inventors.

Methods and circuits for driving a coil-armature device are disclosed. The circuits are configured to drive the coil-armature device to a first energy level for a period of time sufficient to retract the armature to the center of the coil, and then, to drive the coil-armature device to a second energy level subsequently. The first energy level is greater than the second energy level. The second energy level may be achieved by alternatively connecting and disconnecting a driving voltage to the coil-armature device according to a “hold” mode duty cycle. The first energy level may be achieved by connecting the driving voltage to the coil-armature device continuously for a period of time sufficient to retract the armature to the center of the coil. Alternatively, the first energy level may be achieved by alternatively connecting and disconnecting the driving voltage to the coil-armature device according to a “pull-in” mode duty cycle, which is different from the “hold” mode duty cycle.

FIG. 1 is a circuit diagram of a coil driving circuit according to one embodiment of the present invention.

FIG. 2 is a circuit diagram of a coil driving circuit according to a second embodiment of the present invention.

The present invention provides for a circuit that drives a coil with a large initial current during the “pull in” mode, where the armature is retracted, or pulled back, into the coil. The coil is then driven at a reduced current level during the “hold” mode, where the position of the armature is maintained or held in place. Beyond the obvious savings due to the use of less energy, the reduction in the average amount of power handled by the coil allows for the use of a smaller coil, which, in turn, allows for the overall size of the device to be reduced. Additionally, a reduction in the average amount of power handled by the coil-armature device also leads to a reduction in the amount of heat generated by the device.

A first exemplary embodiment of the invention will now be discussed with reference to the circuit diagram illustrated in FIG. 1 . According to FIG. 1 , coil driving circuit 10 connects to power supply V coil , as well as to ground through a first switch SW 1 . Coil L 1 , which is a type of coil-armature device, connects to and receives power from the power supply V coil . Coil L 1 also connects to first switch SW 1 through a transistor Q 1 , which functions as a second type of switch. Wired in parallel with coil L 1 is a freewheeling diode D 1 that provides a path for the coil current generated by the charge stored in coil L 1 to flow and dissipate whenever transistor Q 1 is turned off.

The gate of Q 1 communicates with switch SW 1 through a resistance R 4 . The gate of Q 1 also receives an output signal V 4 from a first NAND logic gate G 1 which functions as a controller for the transistor Q 1 . In response to voltage signal V 4 , transistor Q 1 selectively turns on and off. Specifically, when voltage signal V 4 is high, transistor Q 1 turns on, thereby establishing a current path between power supply V coil and ground and allowing coil L 1 to charge. When voltage signal V 4 is low, transistor Q 1 turns off, disrupting the current path between V coil and ground, causing coil L 1 to discharge through the path established by diode D 1 .

If the coil driving circuit 10 is being utilized with very large size coils and high levels of current, the output signal V 4 from NAND gate G 1 can first be fed into a gate driver, such as, for example, a metal oxide semiconductor field effect transistor (MOSFET) driver that is capable of working with high voltage and current levels. However, for applications that utilize more traditional size coils, such as, for example, those used in a 42 volt, 40 amp relay, then a gate driver is not necessary and output voltage V 4 can be directly fed to the gate of transistor Q 1 through a direct connection, i.e., by directly connecting point A to point B in FIG. 1 .

A second path between the power supply V coil and ground (through switch SW 1 ) is established through a resistance R 2 connected in series with a capacitor C 4 . The voltage V 6 across capacitor C 4 is provided as a first input voltage for the NAND gate G 1 . The second input voltage for NAND gate G 1 is derived from the output of a pulse width modulation (PWM) signal generator 12 capable of delivering a PWM signal with a programmable duty cycle.

In the embodiment illustrated in FIG. 1 , pulse width modulation (PWM) signal generator 12 includes a second NAND gate G 2 that is configured as an inverter by connecting the first and second inputs of NAND gate G 2 together, thereby creating one common input. A feedback loop is established by wiring a resistance R 1 between the output of gate G 2 and the common input of gate G 2 . The common input of NAND gate G 2 is also connected to ground (by means of switch SW 1 ) through a resistance R 3 and capacitance C 1 wired in parallel to one another.

Operation of the coil driving circuit 10 , as illustrated in FIG. 1 , will now be discussed in detail. Coil driving circuit 10 is activated upon closing switch SW 1 , thereby connecting the circuit 10 to ground. Upon activation of circuit 10 , the input voltage V 12 for NAND gate G 2 is low as the charge across capacitance C 1 has yet been allowed to build up. Due to the low input voltage V 12 , NAND gate G 2 generates a high output voltage V 35 . The presence of a high output voltage V 35 leads to the charging of capacitance C 1 through the feedback loop of resistance R 1 . The charge across capacitance C 1 increases until voltage V 12 reaches the upper threshold voltage of NAND gate G 2 . Upon voltage V 12 reaching this upper threshold voltage, the operating state of NAND gate G 2 changes, such that gate G 2 begins to generate a low output voltage V 35 . As a result of voltage V 35 dropping to a low value, capacitance C 1 begins to discharge through resistance R 1 and R 3 . The charge across C 1 continues to diminish until voltage V 12 reaches a lower threshold voltage of NAND gate G 2 , resulting in the above process repeating itself, with gate G 2 once again generating a high output voltage V 35 . In this manner, NAND gate G 2 , capacitance C 1 and resistances R 1 and R 3 work together to generate a pulse width modulation (PWM) signal that oscillates between a high and low voltage level, such as V coil and ground, with an oscillation frequency determined by the time constant R 1 C 1 and a duty cycle determined by the value of resistance R 3 .

Pulse width modulation (PWM) signal V 35 is provided as one of the input voltages for NAND gate G 1 . NAND gate G 1 , however, is not initially influenced by the PWM signal V 35 . Instead, upon activation of the coil driving circuit 10 , NAND gate G 1 automatically generates a high voltage output signal V 4 for a predetermined duration. This is because the other input voltage for NAND gate G 1 , specifically, voltage V 6 , is initially low due to the fact that a charge across capacitance C 4 has yet been allowed to build up. As long as input voltage V 6 remains low, and thus below an upper threshold voltage of gate G 1 , output voltage V 4 will remain high regardless of the logic level of V 35 .

Upon activation of coil driving circuit 10 , capacitance C 4 begins to accumulate charge obtained from power supply V coil through resistance R 2 . Consequently, input voltage V 6 gradually increases until it reaches the upper threshold voltage established by NAND gate G 1 . Once voltage V 6 reaches this threshold, NAND gate G 1 becomes responsive to the pulse width modulation (PWM) signal V 35 that it receives as a second input voltage. As a result, when PWM signal V 35 is high, output voltage V 4 will be low, and when PWM signal V 35 is low, output voltage V 4 will be high.

Accordingly, NAND gate G 1 is seen to operate in two different modes, including a “pull-in” mode and a “hold” mode. When coil driving circuit 10 is first activated, NAND gate G 1 enters the “pull-in” mode, generating a high voltage output signal V 4 for a predetermined duration. This high voltage output signal V 4 turns on transistor Q 1 for a predetermined duration, allowing the current flowing through coil L 1 to ramp up to a sufficiently high level capable of generating a strong enough electromagnetic field to retract, or pull in, the armature.

Upon the input voltage V 6 increasing to the threshold voltage, NAND gate G 1 enters the “hold” mode, wherein the output signal of the gate, voltage V 4 , becomes responsive to the pulse width modulation (PWM) signal V 35 . Specifically, voltage V 4 mimics the PWM signal V 35 in a direct but opposite manner, such that when voltage V 35 is low, voltage V 4 is high, and when voltage V 35 is high, voltage V 4 is low. Consequently, transistor Q 1 becomes responsive to the PWM signal V 35 , cycling on and off at a rate corresponding to the oscillation frequency of the PWM signal V 35 . The cycling on and off of transistor Q 1 leads to the current flowing through coil L 1 to ramp up and down, thereby charging coil L 1 to a power level that is sufficient to retain or hold in place the already retracted armature, but lower in value than the initial power level required to cause retraction of the armature.

The duration of the “pull-in” mode of NAND gate G 1 is determined by the rate at which voltage V 6 is allowed to increase, which, in turn, is determined by the time constant R 2 C 4 . Accordingly, the duration of the “pull-in” mode can be controlled by adjusting the sizes of resistance R 2 or capacitance C 4 .

According to the embodiment illustrated in FIG. 1 , pulse width modulation (PWM) signal generator 12 comprises a NAND gate G 2 configured as an inverter, along with capacitance C 1 and resistances R 1 and R 3 . However, according to one or more alternative embodiments of the present invention, coil driving circuit 10 can be adapted to accommodate essentially any type of circuit configuration, or electronic device, capable of generating a pulse width modulation signal that can be delivered as an input signal for NAND gate G 1 .

A second exemplary embodiment of the invention will now be discussed with reference to the circuit diagram illustrated in FIG. 2 . Similar to the previous embodiment, coil driving circuit 20 electrically communicates with power supply V coil , as well as with ground through a first switch SW 1 . Coil L 1 , representing a type of coil-armature device, connects in series with a transistor switch Q 2 , which selectively connects coil L 1 to power supply V coil . Connected in series between coil L 1 and switch SW 1 is a “current sense” resistance R 18 , which allows for the monitoring of the amount of current flowing between power supply V coil and ground, and thus through coil L 1 , when switch SW 1 is closed. Wired in parallel with the series of coil L 1 and resistance R 18 is diode D 2 , thereby creating a loop path along which the current generated by coil L 1 can flow and dissipate whenever transistor Q 2 is off.

Control of transistor Q 2 is the responsibility of comparator P 1 , whose output signal V 3 is transmitted through a resistance R 15 to the gate of transistor Q 2 . In response to voltage signal V 3 , transistor Q 2 selectively turns on and off. Specifically, transistor Q 2 is configured to turn on when V 3 is low, thereby establishing a current path between power supply V coil and ground (assuming switch SW 1 is closed) and allowing coil L 1 to charge. When voltage signal V 3 is high, transistor Q 2 turns off, disrupting the current path between V coil and ground, causing coil L 1 to discharge through the path established by resistance R 18 and diode D 2 .

If the coil driving circuit 20 is being utilized with very large size coils and high levels of current, the output signal V 3 from comparator P 1 can first be fed into a gate driver, such as, for example, a metal oxide semiconductor field effect transistor (MOSFET) driver that is capable of working with high voltage and current levels. Optional protection for the relay driver can also be provided by connecting a zener diode Z 1 and resistance R 5 in parallel between power supply V coil and the gate of transistor Q 2 , thereby limiting the amount of voltage and current that can be passed from the power supply V coil to the gate driver during the occurrence of a fault.

Comparator P 1 is configured to generate either a low or high voltage output signal V 3 depending on the relationship between a first input signal V 1 and a reference input signal Vref 1 . Specifically, when V 1 is less than Vref 1 , then output signal V 3 is low, but when V 1 exceeds Vref 1 , then output signal V 3 is high. Comparator P 1 is also configured to exhibit a hysteresis-type of characteristic, establishing a different threshold level when the input voltage V 1 is decreasing, eventually dropping below a threshold voltage that triggers the comparator P 1 to reverse the output signal V 3 back to a low value. This introduction of a hysteresis-type of action in comparator P 1 is accomplished by the presence of resistances R 9 and R 11 , both of which connect at one end to the first input of comparator P 1 that receives input voltage V 1 . The other end of resistance R 11 connects to the output of comparator P 1 , subsequent to resistance R 15 , while resistance R 9 runs down to the point where coil L 1 connects to resistance R 18 .

According to the present embodiment, input voltage V 1 is a representation of the amount of current flowing through coil L 1 . Specifically, the voltage drop across resistance R 18 is an indication of the amount of current flowing through coil L 1 . This voltage across resistance R 18 is fed through resistance R 9 to comparator P 1 , with the resultant voltage becoming the input voltage V 1 of the comparator P 1 .

The voltage to which input signal V 1 is compared to is the reference voltage Vref 1 . Voltage Vref 1 is established by a voltage divider circuit, which, in the present embodiment, comprises zener diode Z 2 , a bi-directional analog switch U 2 , and resistances R 6 , R 7 , R 8 and R 10 . The zener diode Z 2 establishes a constant voltage across the series of resistances R 7 , R 8 and R 10 , with the voltage across each of the resistances correlating to their resistance value. When coil driving circuit 20 is first activated by the closing of switch SW 1 , analog switch U 2 is in an open state such that point C and point D of the switch U 2 do not electrically communicate with one another. In this case, all three resistances R 7 , R 8 and R 10 remain in series with one another, with voltage Vref 1 being equal to the voltage drop across the latter two resistances R 8 and R 10 . After a predetermined duration of time, bi-directional analog switch U 2 closes, leading to the establishment of a short between points C and D at switch U 2 . This effectively shorts out resistance R 8 and results in voltage Vref 1 becoming equal to the voltage drop across resistance R 10 only.

The shorting of resistance R 8 through closing of switch U 2 is dependent upon a control signal V 7 that is provided to the switch U 2 by a second comparator P 2 . When coil driving circuit 20 is first activated, control signal V 7 is in a low voltage state. It is only after circuit 20 has been activated for a predetermined period of time that comparator P 2 begins to generate a high voltage output signal V 7 , thereby triggering switch U 2 to close and resistance R 8 to short out.

Operation of the coil driving circuit 20 , as illustrated in FIG. 2 , will now be discussed in greater detail. Coil driving circuit 20 is activated upon closing of switch SW 1 , thereby connecting the circuit 20 to ground. Upon activation, circuit 20 first enters a “pull-in” mode, wherein coil L 1 repetitively ramps up and down at a high current level, thereby charging coil L 1 to a first power level that is sufficient to retract an armature back into the coil. At the initial moment of activation of circuit 20 , both comparator input voltages V 1 and V 2 are in a low voltage state, V 1 being low as no substantial amount of current has yet passed through the coil L 1 , and V 2 being low as capacitance C 5 has not had sufficient enough time to build up a charge. Consequently, voltage V 2 is less than reference voltage Vref 2 , which is established as a fixed voltage drop across resistance R 14 whenever circuit 20 is activated. As a result of V 2 being less than Vref 2 , output signal V 7 remains in a low state, thereby keeping switch U 2 open and voltage Vref 1 equivalent to the accumulated voltage drop across resistors R 8 and R 10 .

With input voltage V 1 being lower in value than voltage Vref 1 , comparator P 1 generates a low voltage output signal V 3 that is provided to the gate of transistor Q 2 . Transistor Q 2 is configured to turn on in response to receiving a low gate voltage signal, and turn off in response to receiving a high gate voltage signal. Accordingly, transistor Q 2 turns on in response to the low voltage signal V 3 , thereby allowing current to flow through the coil L 1 . As current continues to build or ramp up in value in coil L 1 , the voltage drop across resistance R 18 increases. This increase in voltage across resistance R 18 leads voltage V 1 to increase in value. This buildup of voltage V 1 continues until voltage V 1 exceeds voltage Vref 1 . At this point, comparator P 1 begins to generate a high voltage level output signal V 3 , which results in transistor Q 2 turning off, thereby cutting off coil L 1 from the power supply V coil . Coil L 1 , having been allowed to ramp up to a relatively high power level, now begins to discharge as current, generated by coil L 1 , begins to dissipate as it traverses around the loop comprising resistance R 18 , diode D 2 and coil L 1 . The stored energy in the coil L 1 continues to dissipate, leading to a decrease in the voltage across resistance R 18 , and, subsequently, a decrease in voltage V 1 . Upon voltage V 1 decreasing in value below voltage Vref 1 , comparator P 1 returns to generating a low voltage output signal V 3 , which, in turn, turns transistor Q 1 back on.

The above cycle repeats a plurality of times, causing coil L 1 to ramp up and down at a high current level that provides a sufficient amount of power to retract an armature. During this time, capacitor C 5 continues to build up charge, thereby causing voltage V 2 to increase. Upon voltage level V 2 exceeding the fixed voltage Vref 2 , comparator P 2 begins to generate a high voltage level output signal V 7 . Upon receiving a high voltage level signal V 7 , analog switch U 2 closes, thereby shorting out resistance R 8 . As a consequence of resistance R 8 being effectively eliminated from the voltage divider, reference voltage Vref 1 decreases in value. Specifically, before closure of switch U 2 , reference voltage Vref 1 was equivalent to the total voltage drop across resistances R 8 and R 10 . Upon closure of switch U 2 , thereby shorting resistance R 8 , reference voltage Vref 1 decreases in value, now being equivalent to the voltage drop just across resistance R 10 .

The reduction in magnitude of reference voltage Vref 1 signals that coil driving circuit 20 has transitioned from the earlier “pull-in” mode to a “hold” mode, wherein coil L 1 is limited to charging to a second, lower power level that is insufficient to retract an armature, but sufficient to maintain, or “hold” in place, an armature that has already been retracted. Specifically, coil driving circuit 20 continues to repetitively turn transistor Q 2 on and off in response to voltage signal V 3 oscillating back and forth between a high and low voltage. The duration in which voltage signal V 3 remains in either a high voltage state or a low voltage state is dependent on the magnitude of reference voltage Vref 1 . The greater the magnitude of Vref 1 , the longer it takes for voltage V 1 to either increase to the value of Vref 1 , or decrease from the value of Vref 1 to a lower threshold voltage. Consequently, when reference voltage Vref 1 is greater in magnitude, transistor Q 2 remains on for longer periods of time, allowing coil L 1 to ramp up at a higher current level then when Vref 1 is smaller in magnitude, as is the case during the “hold” mode of circuit 20 . When reference voltage Vref 1 is decreased in magnitude, transistor Q 2 can remain on for only shorter periods of time, thereby limiting the current level to which coil L 1 can ramp up to.

Accordingly, the second embodiment of the invention, as presented above, calls for a coil driving circuit 20 that initially drives coil L 1 according to a first duty cycle that permits the coil current to ramp up and down at a high current level. This allows the coil L 1 to be charged to a first power level that is sufficient to retract an armature. After a predetermined duration of time, coil driving circuit 20 drives coil L 1 according to a second duty cycle that permits the coil current to ramp up and down at a more limited current level. This limits the charging of coil L 1 to a second, lower power level that is insufficient to retract an armature, but sufficient to maintain the position of an armature that has already been retracted.

While the invention has been specifically described in connection with certain specific embodiments thereof, it is to be understood that this is by way of illustration and not of limitation, and the scope of the appended claims should be construed as broadly as the prior art will permit.