Multi-speed delay-locked loop

The present invention relates to a delay-locked loop circuit. More specifically, the present invention relates to a delay-locked loop circuit having an extended operating range provided by user configuration control over inverter delay.

FIG. 1 is a block diagram of a portion of an integrated circuit such as a conventional field programmable gate array (FPGA) 100 , which includes delay lock loop (DLL) 101 , global clock driver 102 , global clock routing network 103 , output flip-flop 104 , and input flip-flop 105 . Other well-known elements of FPGA 100 are not illustrated in FIG. 1 for purposes of clarity. An external reference clock signal CLK_IN is routed to DLL 101 . In response to the CLK_IN signal, DLL 101 generates an output clock signal CLK_OUT, which is provided to global clock driver 102 . The output clock signal CLK_OUT is transmitted through global clock driver 102 to global clock routing network 103 . Global clock routing network 103 transmits the output clock signal CLK_OUT throughout FPGA 100 with minimum skew within the FPGA, but with a significant delay. A plurality of distributed clock signals, all exhibiting a similar delay, are provided at ends of global clock routing network 103 . One of these distributed clock signals is illustrated as the distributed clock signal, DIST_CLK. The DIST_CLK signal is used to clock data values within FPGA 100 . For example, the DIST_CLK signal is used to clock the data value D 1 into output flip-flop 104 , thereby providing an output data value D OUT , which is synchronous with the DIST_CLK signal. Similarly, the DIST_CLK signal is used to clock the data value D IN into input flip-flop 105 , thereby providing an input data value Q 1 , which is synchronous with the DIST_CLK signal.

The DIST_CLK signal is also provided to a feedback terminal of DLL 101 . In response to the DIST_CLK signal, DLL 101 introduces a delay in the output clock signal CLK_OUT. DLL 101 controls the amount of delay introduced, such that the active edges of the distributed clock signal DIST_CLK has a predetermined phase relationship (i.e., a fixed, known offset) with respect to the active edges of the input clock signal CLK_IN.

For the above-described purpose, FPGA 100 uses DLL 101 to artificially increase the delay of the internally distributed clock signal DIST_CLK. The additional delay introduced by the DLL is feedback-controlled such that the total delay (i.e., the delay introduced by DLL 101 plus the clock distribution delay) yields a pre-determined desired setup and hold time relationship between clock and data. For example, the total delay may be equal to one clock period, such that the internally distributed clock signal DIST_CLK is synchronized with the external clock signal CLK_IN.

Typically, a series cascade of inverters within DLL 101 is used to provide the necessary delay. More specifically, DLL 101 provides the necessary delay by selecting the output of the appropriate inverter in the series cascade of inverters. As an optimization, the power supply to these inverters may be regulated such that the delay is independent of temperature, supply voltage, and process variations. One example of DLL 101 is described in more detail in Xilinx Application note XAPP174, “Using Delay-Locked Loops in Spartan-II FPGAs”, Jan. 24, 2000.

FPGA 100 can be operated at different clock frequencies. In order to facilitate operation at lower clock frequencies (i.e., longer clock periods) DLL 101 must be able to introduce longer delays. DLL 101 must therefore include relatively long inverter chains in order to provide these longer delays. Consequently, low-frequency DLLs are expensive to implement because of the large number of inverters required. It would therefore be desirable to have a low-cost manner of implementing low-frequency DLLS.

Accordingly, the present invention provides a mechanism for extending the operating range of a DLL by providing a user with configuration control over the delay elements (e.g., one or more inverters) of the DLL. For example, the configuration control can be used to double the delay of each inverter, thereby doubling the maximum delay achievable. As a result, the DLL of the present invention allows an associated FPGA to operate at half the frequency of an FPGA having a DLL of the prior art.

In one embodiment, the inverter delay is increased by reducing the power supply voltage to the inverters. Alternately, the inverter delay can be increased by controlling the body bias of the transistors used to create the inverters.

In an alternate embodiment, one or more fast inverters are retained to provide fine delay control. These fast inverters permit greater synchronization accuracy when the DLL is locked, and also reduce jitter. There are sufficiently few of these fast elements to guarantee monotonicity of the introduced delay. If the delay of the primary delay chain is increased dramatically, the delay of the fast inverters may also be increased in certain embodiments.

The present invention will be more fully understood in view of the following description and drawings.

FIG. 1 is a block diagram of a conventional FPGA, including the global clock distribution network.

FIG. 2 is a block diagram of a delay locked loop (DLL) in accordance with one embodiment of the present invention.

FIG. 3 is a circuit diagram of a delay element in accordance with one embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating the timing of various DLL clock signals during high frequency operation, in accordance with one embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating the timing of various DLL clock signals during low frequency operation, in accordance with one embodiment of the present invention.

FIG. 2 is a block diagram of a delay locked loop (DLL) 200 in accordance with one embodiment of the present invention. DLL 200 includes delay selection circuit 201 , primary delay chain 202 (which includes delay elements 205 1 – 205 N ), fast delay element 206 , multiplexers 211 – 213 , configuration memory cell 220 and voltage supply, or distribution, line 222 . In the described embodiment, each of delay elements 205 1 – 205 N (and fast delay element 206 ) includes an even number of series connected inverters. As a result, each of these delay elements provides an output signal that is delayed from the input signal and non-inverted.

In accordance with the described embodiment, DLL 200 replaces DLL 101 in FPGA 100 ( FIG. 1 ). Thus, DLL 200 receives the input clock signal CLK_IN received by the FPGA and the distributed clock signal DIST_CLK used to clock data out of the FPGA. In response, DLL 200 provides the output clock signal CLK_OUT to the global clock driver. DLL 200 introduces a delay to the input clock signal CLK_IN to create the output clock signal CLK_OUT. This delay is selected such that the distributed clock signal DIST_CLK has a predetermined, fixed offset with respect to the input clock signal CLK_IN. In the embodiments described below, the delay is selected such that the distributed clock signal DIST_CLK is synchronous with the input clock signal CLK_IN.

Within DLL 200 , the input clock signal CLK_IN is provided to an input terminal of delay chain 202 , an input terminal of multiplexer 211 , and an input terminal of delay selection circuit 201 . The distributed clock signal DIST_CLK is also applied to an input terminal of delay selection circuit 201 . Delay selection circuit 201 provides multiplexer control signals M 1 and M 2 to multiplexers 211 and 212 , respectively, in response to the CLK_IN and DIST_CLK signals. The multiplexer control signals M 1 and M 2 select the delay introduced to the CLK_IN signal in order to create the CLK_OUT signal. Multiplexer control signals M 1 and M 2 can be multi-wire signals in other embodiments.

The input clock signal CLK_IN propagates through the N series-connected delay elements 205 1 – 205 N . Each of these delay elements 205 1 – 205 N provides a corresponding delayed clock signal C 1 –C N , respectively, to an associated input terminal of multiplexer 211 . In the described embodiment, each of the delay elements 205 1 – 205 N introduces a signal delay, D. Thus, the delay introduced by delay element 205 K (where K is equal to an integer equal to 1 to N, inclusive) is equal to K*D. As described in more detail below, the signal delay D is selected to be relatively small (d 1 ) during high frequency operation, and relatively large (d 2 ) during low frequency operation.

FIG. 3 is a circuit diagram of delay element 205 1 in accordance with one embodiment of the present invention. Delay element 205 1 includes a plurality of series-connected inverters 301 1 – 301 M , where M is an even integer. Each of inverters 301 1 – 301 M includes a p-channel field effect transistor (FET) (e.g., p-channel FET 310 ) having a source coupled to voltage supply line 222 , and a drain coupled to an inverter output terminal (e.g., inverter output terminal 312 ). Similarly, each of inverters 301 1 – 301 M includes an n-channel FET (e.g., n-channel FET 320 ) having a source coupled to a ground voltage supply and a drain coupled to the inverter output terminal. The gates of the p-channel and n-channel FETs are commonly coupled to an inverter input terminal (e.g., inverter input terminal 311 ). Each of inverters 301 1 – 301 M introduce a delay to a received signal, such that the entire chain of inverters 301 1 – 301 M introduces the signal delay, D.

Returning now to FIG. 2 , multiplexer 213 has input terminals coupled to receive supply voltages V S1 and V S2 , an output terminal coupled to voltage supply line 222 , and a control terminal coupled to configuration memory cell 220 . Configuration memory cell 220 is programmed to store a configuration data value provided by a user during configuration of the associated FPGA. Configuration memory cell 220 is known to those of ordinary skill in the art of FPGA design. In an alternate embodiment, the control terminal of multiplexer 213 is coupled to an active signal, the value of which may be allowed to change during operation. Multiplexer 213 routes one of the supply voltages V S1 or V S2 to voltage supply line 222 in response to the configuration data value stored in configuration memory cell 220 . In the described embodiment, supply voltage V S1 is significantly greater than supply voltage V S2 . For instance, supply voltage V S1 may be 10 or more percent greater than supply voltage V S2 . As described in more detail below, multiplexer 213 is controlled to provide the relatively high supply voltage V S1 to voltage supply line 222 when FPGA is configured to operate at a relatively high frequency. Conversely, multiplexer 213 is controlled to provide the relatively low supply voltage V S2 to voltage supply line 222 when FPGA is configured to operate at a relatively low frequency.

Multiplexer 211 routes the input clock signal CLK_IN or one of the delayed clock signals C 1 –C N as the clock signal C OUT in response to the multiplexer control signal M 1 . The clock signal C OUT is provided to an input terminal of multiplexer 212 , and to an input terminal of fast delay element 206 . In the described embodiment, fast delay element 206 is substantially identical to delay elements 205 1 – 205 N , except that fast delay element 206 is always coupled to receive the supply voltage V S1 , regardless of the state of configuration memory cell 220 . Delay element 206 provides a delayed clock signal C OUTD to an input terminal of multiplexer 212 . Multiplexer 212 routes one of the received clock signals C OUT or C OUTD as the output clock signal CLK_OUT in response to multiplexer control signal M 2 .

DLL 200 operates as follows in accordance with one embodiment of the present invention. As described above, supply voltage V S1 is significantly greater than supply voltage V S2 . In one embodiment, supply voltage V S1 is equal to a nominal positive supply voltage of the associated FPGA. For example, if the input/output circuitry (e.g., input/output blocks, or IOBs) of the associated FPGA operates in response to a nominal supply voltage of 1.2 Volts, then the supply voltage V S1 can be set equal to 1.2 Volts. Each of the delay elements 205 1 – 205 N exhibits a relatively small signal delay, d 1 , when operating in response to supply voltage V S1 .

Each of the delay elements 205 1 – 205 N exhibits a relatively large signal delay, d 2 , when operating in response to the lower supply voltage V S2 . The supply voltage V S2 may be selected such that the signal delay d 2 is more than 10 percent longer than the delay d 1 . In one embodiment, the supply voltage V S2 is selected such that the signal delay d 2 is approximately twice as long as the signal delay d 1 . The supply voltage V S2 is also selected such that delay elements 205 1 – 205 N are able to operate reliably in response to this supply voltage V S2 . In other embodiments, the supply voltage V S2 can have other values, in accordance with the requirements set forth above. It is important to note that the inverters (e.g., inverters 301 1 – 301 M in delay elements 205 1 – 205 N will naturally introduce more signal delay as the voltage on supply line 222 decreases.

Because fast delay element 206 operates in response to supply voltage V S1 , this delay element will always introduce the smaller signal delay, d 1 , to the clock signal C OUT . As described in more detail below, this enables fine-tuning of the total signal delay when operating at relatively low frequencies. Note that in applications where fine tuning is not necessary, delay element 206 and corresponding multiplexer 212 may be optional and signal C OUT may be provided directly as the output clock signal CLK_OUT.

To operate DLL 200 , the user first determines the frequency at which the FPGA will be operated. If the FPGA is to be operated at a relatively high frequency (e.g., 100 MHz or above), then the user programs configuration memory cell 220 such that multiplexer 213 routes the high supply voltage V S1 to voltage supply line 222 . As a result, each of delay elements 205 1 – 205 N introduces the relatively small signal delay d 1 to the input clock signal CLK_IN. These small delay increments d 1 are desirable to adjust the delay of the output clock signal CLK_OUT. Stated another way, a high frequency input clock signal CLK_IN has a relatively small period. Thus, small delay increments are desirable to adjust the delay of the input clock signal CLK_IN, in this instance.

If the FPGA is to be operated at a relatively low frequency (e.g., 100 MHz or below), then the user programs configuration memory cell 220 such that multiplexer 213 routes the low supply voltage V S2 to voltage supply line 222 . As a result, each of delay elements 205 1 – 205 N introduces the relatively large delay d 2 to the input clock signal CLK_IN. These large delay increments d 2 are desirable to adjust the delay of the output clock signal CLK_OUT. Stated another way, a low frequency input clock signal CLK_IN has a relatively large period. Thus, large delay increments are desirable (and sometimes necessary) to add the necessary delay to the input clock signal CLK_IN.

Delay element 206 is capable of fine-tuning the delay introduced by delay line 202 , when operating in response to an input clock signal CLK_IN having a relatively low frequency. Thus, if the relatively large signal delays d 2 introduced by delay elements 205 1 – 205 N are too large to introduce the required delay, then multiplexer 212 can be controlled to route the C OUTD signal as the output clock signal CLK_OUT. As a result, fast delay element 206 is effectively introduced to the end of the selected elements of delay chain 202 . Thus, the relatively short signal delay d 1 of delay element 206 is added to the relatively long delays d 2 of the selected delay elements 205 1 – 205 N . The short delay d 1 of delay element 206 thereby increases the accuracy of DLL 200 , when operating at relatively low frequencies.

Note that when DLL 200 is operating at a relatively high frequency, fast delay element 206 can also be selected to increase the total delay to (N+1)*d 1 . In another embodiment, fast delay element 206 is designed to provide multiple delays less than d 1 in order to allow even finer resolution tuning.

FIG. 4 is a waveform diagram 400 illustrating the timing of the clock signals CLK_IN, CLK_OUT and DIST_CLK during high frequency operation, in accordance with one embodiment of the present invention. Region 401 of waveform diagram 400 illustrates the CLK_IN, CLK_OUT and DIST_CLK signals before DLL 200 introduces any delay to the output clock signal CLK_OUT. At this time, the CLK_OUT signal exhibits a small delay D C1 with respect to the input clock signal CLK_IN. The DIST_CLK signal exhibits a delay D G1 with respect to the CLK_OUT signal. This delay D G1 is introduced by the global clock routing network. In order for the rising edge of the distributed clock signal DIST_CLK to be synchronous with the rising edge of the input clock signal CLK_IN, a delay of D C2 must be introduced to the distributed clock signal DIST_CLK.

Region 402 of waveform diagram 400 illustrates the CLK_IN, CLK_OUT and DIST_CLK signals after DLL 200 has introduced a delay of D C2 to the output clock signal CLK_OUT. At this time, the CLK_IN and DIST_CLK signals are synchronous. In the illustrated example, the delay D C2 is equal to 5*d 1 . Thus, DLL 200 introduces the delay D C2 by generating multiplexer control signals M 1 and M 2 that cause the clock signal (C 5 ) of the fifth delay element ( 205 5 ) in delay chain 202 to be routed as the output clock signal CLK_OUT. In accordance with the described embodiment, delay elements 205 1 – 205 5 of delay chain 202 are sequentially enabled until the proper delay is achieved. In other embodiments, DLL 200 can be controlled to introduce a delay that results in the DIST_CLK signal having a predetermined fixed delay with respect to the CLK_IN signal (wherein these signals are not necessarily synchronous).

FIG. 5 is a waveform diagram 500 illustrating the timing of the clock signals CLK_IN, CLK_OUT and DIST_CLK during low frequency operation, in accordance with one embodiment of the present invention. FIGS. 4 and 5 have an identical scale in the described examples. Region 501 of waveform diagram 500 illustrates the CLK_IN, CLK_OUT and DIST_CLK signals before DLL 200 introduces any delay to the output clock signal CLK_OUT. At this time, the CLK_OUT signal exhibits a small delay D C1 with respect to the input clock signal CLK_IN. The DIST_CLK signal exhibits a delay D G2 , which is introduced by the global clock routing network. Note that D G2 is equal to D G1 ( FIG. 4 ) in the embodiment described in FIG. 2 . In order for the rising edge of the distributed clock signal DIST_CLK to be synchronous with the rising edge of the input clock signal CLK_IN, a delay of D C3 must be introduced to the distributed clock signal DIST_CLK. Note that D C3 is much greater than D C2 ( FIG. 4 ), due to the lower frequency of the input clock signal CLK_IN in FIG. 5 .

Region 502 of waveform diagram 500 illustrates the CLK_IN, CLK_OUT and DIST_CLK signals after DLL 200 has introduced a delay of D C3 to the output clock signal CLK_OUT. Again, DLL 200 sequentially introduces delay elements to the delay line until the desired delay is achieved. At this time, the CLK_IN and DIST_CLK signals are synchronous. In the illustrated example, the delay D C3 is equal to 6*d 2 +d 1 . Thus, DLL 200 introduces the delay D C3 by generating a multiplexer control signal M 1 that causes the clock signal (C 6 ) of the sixth delay element ( 205 6 ) in delay chain 202 to be routed as the C OUT signal, and generating a multiplexer control signal M 2 that causes the clock signal C OUTD to be routed as the output clock signal CLK_OUT. Note that the delay d 1 of fast delay element 206 is used to fine-tune the delay D C3 in the example of FIG. 5 .

In accordance with one variation of the present invention, bias voltages applied to the well regions of the transistors used in inverters 301 1 – 301 M can be controlled to control the delay of delay element 205 1 (See, FIG. 3 ). Similar control is also exercised over delay elements 205 2 – 205 N . For example, if p-channel FET 310 is fabricated in an n-well region, and n-channel FET 320 is fabricated in a p-well region, then a higher bias voltage applied to the n-well region and a lower bias voltage applied to the p-well region will result in a relatively small signal delay through the associated inverter 301 1 . Conversely, a lower bias voltage applied to the n-well region and a higher bias voltage applied to the p-well region will result in a relatively large signal delay through the associated inverter 301 1 . Thus, during high frequency operation, a high bias voltage is applied to the n-well region and a low bias voltage is applied to the p-well region. During low frequency operation, a low bias voltage is applied to the n-well region and a high bias voltage is applied to the p-well region.

In yet another embodiment, both the well bias voltages and the voltage of voltage supply line 222 are controlled in order to control the delay of delay line 202 . In further embodiments, other techniques known to those of skill in the art may be used to provide a selectable voltage for voltage supply line 222 . For example, the voltage may be supplied from an external source, or by a voltage regulator allowing for selection of one of at least two possible output voltages. In some embodiments, a voltage supply line similar to voltage supply line 222 may be connected to the ground terminals of the delay elements, where adjusting the voltage of that voltage supply line adjusts the delay. In yet other embodiments, other known techniques for adjusting delay of a circuit may be used to adjust delay of the delay elements of delay line 202 in accordance with the present invention. In such embodiments, a delay control circuit, based on a value stored in one or more configuration memory cells, may be used to adjust the delays of the delay elements in accordance with the present invention and such known techniques. The value stored in the configuration memory cell may depend on the mode of operation (e.g., high or low frequency operation).

Although the invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications, which would be apparent to one of ordinary skill in the art. For example, while the present invention has been described using two supply voltages V S1 and V S2 , which provide two delay values d 1 and d 2 , it is understood that the present invention can be extended to more than two supply voltages, which provide more than two delay values. Thus, the invention is limited only by the following claims.