Bi-directional motor control circuit

1. Field of the Invention

The present invention relates to a control circuit and, more particularly, to a motor control circuit for controlling an H-bridge drive circuit to operate a bi-directional motor among a forward rotation mode, a brake mode, and a, reverse rotation mode.

2. Description of the Related Art

FIG. 1 ( a ) is a detailed circuit diagram showing a conventional motor control circuit 10 . FIG. 1 ( b ) is a timing chart showing an operation of the conventional motor control circuit 10 . Referring to FIG. 1 ( a ), a bi-directional motor M is connected with an H-bridge drive circuit 1 , and the motor control circuit 10 operates the bi-directional motor M among a standby mode, a forward rotation mode, a brake mode, and a reverse rotation mode through controlling the H-bridge drive circuit 1 . More specifically, the H-bridge drive circuit 1 is constructed by six drive transistors Q 1 to Q 6 . A terminal Na of the bi-directional motor M is coupled to a collector electrode of the pnp transistor Q 1 and a collector electrode of the npn transistor Q 3 . A terminal Nb of the bi-directional motor M is coupled to a collector electrode of the pnp transistor Q 2 and a collector electrode of the npn transistor Q 4 . Emitter electrodes of the transistors Q 1 and Q 2 are connected together to a drive voltage source Vd while emitter electrodes of the transistors Q 3 and Q 4 are connected together to a ground potential. The transistors Q 1 to Q 4 are provided with flywheel diodes D 1 to D 4 , respectively, for allowing the electromotive force-induced current to flow through when the transistors Q 1 to Q 4 are turned off. The npn transistor Q 5 has a collector electrode coupled to a base electrode of the transistor Q 1 , and an emitter electrode coupled to a base electrode of the transistor Q 4 . The npn transistor Q 6 has a collector electrode coupled to a base electrode of the transistor Q 2 and an emitter electrode coupled to a base electrode of the transistor Q 3 .

The motor control circuit 10 has a forward rotation current source constructed by a pnp transistor Q 7 and a reverse rotation current source constructed by a pnp transistor Q 8 . The transistor Q 7 is biased by a control voltage source Vc 1 for providing a control current Ic 1 . The transistor Q 8 is biased by a control voltage source Vc 2 for providing a control current Ic 2 . The control current Ic 1 is split at a diverging node N 1 into a first partial current If 1 and a second partial current If 2 . The first partial current If 1 is supplied to the base electrode of the transistor Q 5 while the second partial current If 2 is supplied to the base electrode of the transistor Q 4 . On the other hand, the control current Ic 2 is split at a diverging node N 2 into a first partial current Ir 1 and a second partial current Ir 2 . The first partial current Ir 1 is supplied to the base electrode of the transistor Q 6 while the second partial current Ir 2 is supplied to the base electrode of the transistor Q 3 .

In response to a forward rotation command signal FWD and a reverse rotation command signal REV, the motor control circuit 10 controls the motor drive circuit 1 to operate the motor M among a standby mode, a forward rotation mode, a brake mode, and a reverse rotation mode. Each of the forward and reverse rotation command signals FWD and REV is a logic signal having a HIGH state and a LOW state. When the forward rotation command signal FWD and the reverse rotation command signal REV are both at the LOW state, npn transistors Q 11 and Q 12 are turned off. As a result, the control currents Ic 1 and Ic 2 supplied from the control voltage sources Vc 1 and Vc 2 are zero, which may be exemplified by periods T1, T4, and T7 shown in FIG. 1 ( b ). In this case, the motor control circuit 10 is prohibited from supplying the four partial currents If 1 , If 2 , Ir 1 , and Ir 2 and then makes all of the drive transistors Q 1 to Q 6 nonconductive, thereby operating the motor M in the standby mode.

When the forward rotation command signal FWD is at the HIGH state and the reverse rotation command signal REV is at the LOW state, the transistor Q 11 is turned on and the transistor Q 12 is turned off. The control current Ic 1 supplied from the control voltage source Vc 1 has a maximum Ic 1 m and the control current Ic 2 supplied from the control voltage source Vc 2 is zero, which may be exemplified by period T2 shown in FIG. 1 ( b ). At this time, the first partial current If 1 of the control current Ic 1 is allowed to be supplied to the base electrode of the drive transistor Q 5 because npn transistor Q 9 which is controlled by the reverse rotation command signal REV is turned off. As a result, the transistors Q 1 and Q 4 are turned on for allowing a forward current to flow from the terminal Na to the terminal Nb, thereby operating the motor M in the forward rotation mode.

When the forward rotation command signal FWD and the reverse rotation command signal REV are both at the HIGH state, the transistors Q 11 and Q 12 are turned on. The control current Ic 1 supplied from the control voltage source Vc 1 has a maximum Ic 1 m and the control current Ic 2 supplied from the control voltage source Vc 2 has a maximum Ic 2 m , which may be exemplified by periods T3 and T6 shown in FIG. 1 ( b ). At this time, the first partial current If 1 of the control current Ic 1 is bypassed down to the ground potential though the transistor Q 9 which is also turned on by the reverse rotation command signal REV, and therefore prevented from being supplied to the base electrode of the drive transistor Q 5 . Likely, the first partial current Ir 1 of the control current Ic 2 is bypassed down to the ground potential though the transistor Q 10 which is also turned on by the forward rotation command signal FWD, and therefore prevented from being supplied to the base electrode of the drive transistor Q 6 . However, the second partial current If 2 of the control current Ic 1 is allowed to be supplied to the base electrode of the drive transistor Q 4 and the second partial current Ir 2 of the control current Ic 2 is allowed to be supplied to the base electrode of the drive transistor Q 3 . In this case, the motor current is gradually attenuated to zero when circling in a closed loop composed of the conductive transistors Q 3 and Q 4 and the motor M, which is referred to as the brake mode.

When the forward rotation command signal FWD is at the low state and the reverse rotation command signal REV is at the HIGH state, the transistor Q 11 is turned off and the transistor Q 12 is turned on. As a result, the control current Ic 1 supplied from the control voltage source Vc 1 is zero and the control current Ic 2 supplied from the control voltage source Vc 2 has a maximum Ic 2 m , which may be exemplified by a period T5 shown in FIG. 1 ( b ). At this time, the first partial current Ir 1 of the control current Ic 2 is allowed to be supplied to the base electrode of the drive transistor Q 6 because the transistor Q 10 which is controlled by the forward rotation command signal FWD is turned off. As a result, the transistors Q 2 and Q 3 are turned on for allowing a reverse current to flow from the terminal Nb to the terminal Na, thereby operating the motor M in the reverse rotation mode.

Although the conventional motor control circuit 10 effectively controls the various operational modes of the motor M, several problems are inevitably caused in its practical applications. Referring to FIG. 1 ( b ), a curve 11 illustrates the control current Ic 1 supplied from the control voltage source Vc 1 of the motor control circuit 10 among the operational modes. As clearly identified in the curve 11 , the control voltage source Vc 1 supplies the same control current Ic 1 with the maximum Ic 1 m regardless of the forward rotation mode and the brake mode. However, as described above, the first partial current If 1 of the control current Ic 1 in the brake mode is bypassed down to the ground through the conductive transistor Q 9 and has nothing to do with controlling the motor drive circuit 1 , resulting in a meaningless waste of power. Referring to FIG. 1 ( b ), a curve 12 illustrates the control current Ic 2 supplied from the control voltage source Vc 2 of the motor control circuit 10 among the operational modes. As clearly identified in the curve 12 , the control voltage source Vc 2 supplies the same control current Ic 2 with the maximum Ic 2 m regardless of the reverse rotation mode and the brake mode. However, as described above, the first partial current Ir 1 of the control current Ic 2 in the brake mode is bypassed down to the ground through the conductive transistor Q 10 and has nothing to do with controlling the motor drive circuit 1 , resulting in a meaningless waste of power.

Referring to FIG. 1 ( b ), a curve 13 illustrates a total control current consumption of the conventional motor control circuit 10 among the operational modes, i.e. a superposition of the currents Ic 1 and Ic 2 (the curves 11 and 12 ). As clearly identified in the curve 13 , the total control current consumption in the brake mode is twice larger than that in the forward or reverse rotation mode. As described above, the doubling of the total control current consumption is not required by the practical controlling operation and only causes the meaningless waste of power. Therefore, the conventional motor control circuit 10 has a problem with regard to inefficiency and in turn raises operational temperature due to heat generation. A significantly high temperature may cause the circuit malfunction or shut down by thermal protection mechanism.

Furthermore, the practical magnitude of the control current Ic 1 changes in accordance with the control voltage source Vc 1 since the control current Ic 1 is generated by the control voltage source Vc 1 through the transistor Q 7 and the bias resistor. Similarly, the practical magnitude of the control current Ic 2 changes in accordance with the control voltage source Vc 2 since the control current Ic 2 is generated by the control voltage source Vc 2 through the transistor Q 8 and the bias resistor. Because the control currents Ic 1 and Ic 2 directly affects the operation points of the drive transistors Q 1 to Q 6 , the fluctuation of the control voltage sources Vc 1 and Vc 2 brings about a problem with regard to operational instability of the motor M.

In view of the above-mentioned problems, an object of the present invention is to provide a motor control circuit capable of preventing the control currents from being bypassed down to the ground in the brake mode, thereby reducing the power dissipation and suppressing the rise of temperature.

Another object of the present invention is to provide a motor control circuit capable of controlling the brake mode by using a relatively low control current, thereby reducing the power dissipation and suppressing the rise of temperature.

Still another object of the present invention is to provide a motor control circuit capable of supplying the control currents by using constant current sources independent of the fluctuation of the control voltage sources, thereby enhancing the operational stability of the motor.

According to one aspect of the present invention, a motor control circuit is provided for controlling a motor drive circuit to operate a motor among a forward rotation mode, a reverse rotation mode, and a brake mode. The motor control circuit includes a forward rotation control circuit, a reverse rotation control circuit, and a brake control circuit.

The forward rotation control circuit allows a first current source to supply a first current signal to the motor drive circuit, thereby operating the motor in the forward rotation mode. The reverse rotation control circuit allows a third current source to supply a third current signal to the motor drive circuit, thereby operating the motor in the reverse rotation mode. The brake control circuit allows a second current source and a fourth current source to supply a second current signal and a fourth current signal, respectively, to the motor drive circuit, thereby operating the motor in the brake mode. Since the motor control circuit in the brake mode only allows supplying the second and the fourth current signals, the first and the third current signals are prevented from causing undesirable power dissipation.

Preferably, the second current signal is smaller than the first current signal. The fourth current signal is smaller than the third current signal. The motor control circuit effectively reduces the power dissipation and then sup presses the rise of temperature since the second and the fourth current signals are smaller than the first and the third current signals.

Preferably, each of the first to fourth current sources is implemented by a constant current source. The operational stability of the motor is enhanced since the first to fourth current signals supplied from the constant current sources are independent of the fluctuation of control voltage sources.

Preferably, the forward rotation control circuit includes a switch and a logical circuit. The switch is coupled to the first current source. In response to a forward rotation command signal and a reverse rotation command signal, the logical circuit controls the switch for allowing the first current signal to be supplied to the motor drive circuit.

Preferably, the reverse control circuit includes a switch and a logical circuit. The switch is coupled to the third current source. In response to a forward rotation command signal and a reverse rotation command signal, the logical circuit controls the switch for allowing the third current signal to be supplied to the motor drive circuit.

Preferably, the brake control circuit includes a first switch and a second switch. The first switch is coupled to the second current source for allowing the second current signal to be supplied to the motor drive circuit in response to a forward rotation command signal. The second switch is coupled to the fourth current source for allowing the fourth current signal to be supplied to the motor drive circuit in response to a reverse rotation command signal.

The above-mentioned and other objects, features, and advantages of the present invention will become apparent with reference to the following descriptions and accompanying drawings, wherein:

FIG. 1 ( a ) is a detailed circuit diagram showing a conventional motor control circuit;

FIG. 1 ( b ) is a timing chart showing an operation of a conventional motor control circuit;

FIG. 2 ( a ) is a detailed circuit diagram showing a motor control circuit according to a first embodiment of the present invention;

FIG. 2 ( b ) is a timing chart showing an operation of a motor control circuit according to a first embodiment of the present invention; and

FIG. 3 is a detailed circuit diagram showing a motor control circuit according to a second embodiment of the present invention.

The preferred embodiments according to the present invention will be described in detail with reference to the drawings.

FIG. 2 ( a ) is a detailed circuit diagram showing a motor control circuit 20 according to a first embodiment of the present invention. FIG. 2 ( b ) is a timing chart showing an operation of the motor control circuit 20 according to the first embodiment of the present invention. Referring to FIG. 2 ( a ), a motor M is connected with an H-bridge drive circuit 2 , and the motor control circuit 20 operates the motor M among a standby mode, a forward rotation mode, a brake mode, and a reverse rotation mode through controlling the H-bridge drive circuit 2 . The H-bridge drive circuit 2 shown in FIG. 2 ( a ) is the same as the H-bridge drive circuit 1 shown in FIG. 1 ( a ) and, for the sake of simplification, descriptions with regard to the structure and operation of the H-bridge drive circuit 2 will be omitted hereinafter.

The motor control circuit 20 is provided with four current sources 11 to 14 , in which the current sources 11 and 12 are coupled to a control voltage source Vc 1 while the current sources 13 and 14 are coupled to a control voltage source Vc 2 . In one embodiment, the control voltage sources Vc 1 and Vc 2 are identical with respect to each other. The current source 11 may supply a current twice larger than the current source 12 does while the current source 13 may supply a current twice larger than the current source 14 does. The current from the current source 11 may be set equal in magnitude to that from the current source 13 while the current from the current source 12 may be set equal in magnitude to that from the current source 14 . The current source 11 is coupled to the base electrode of the drive transistor Q 5 through a switch S 1 , for supplying a control current signal A. The current source 12 is coupled to the base electrode of the drive transistor Q 4 through a switch S 2 , for supplying a control current signal B. The current source 13 is coupled to the base electrode of the drive transistor Q 6 through a switch S 3 , for supplying a control current signal C. The current source 14 is coupled to the base electrode of the drive transistor Q 3 through a switch S 4 , for supplying a control current signal D.

The switch S 1 is controlled by an output terminal of a NOR gate NG 1 . The NOR gate NG 1 is employed to perform a NOR logical operation between a forward rotation command signal FWD, after inverted by an inverter INV 1 , and a reverse rotation command signal REV. The switch S 2 is controlled by the forward rotation command signal FWD after inverted by series-connected inverters INV 1 and INV 2 . The switch S 3 is controlled by an output terminal of a NOR gate NG 2 . The NOR gate NG 2 is employed to perform a NOR logical operation between a forward rotation command signal FWD and a reverse rotation command signal REV after inverted by an inverter INV 3 . The switch S 4 is controlled by the reverse rotation command signal REV after inverted by series-connected inverters INV 3 and INV 4 .

Each of the forward and reverse rotation command signals FWD and REV is a logical signal having a HIGH state and a LOW state. When the forward rotation command signal FWD and the reverse rotation command signal REV are both at the LOW state, the NOR gate NG 1 outputs LOW for turning off the switch S 1 , the inverter INV 2 outputs LOW for turning off the switch S 2 , the NOR gate NG 2 outputs LOW for turning off the switch S 3 , and the inverter INV 4 outputs LOW for turning off the switch S 4 . Since the switches S 1 to S 4 are all turned off, the current sources 11 to 14 are prevented from supplying any currents, which may be exemplified by periods T1, T4, and T7 shown in FIG. 2 ( b ). In this case, the drive transistors Q 1 to Q 6 are all turned off, thereby operating the motor M in the standby mode.

When the forward rotation command signal FWD is at the HIGH state and the reverse rotation command signal REV is at the LOW state, the NOR gate NG 1 outputs HIGH for turning on the switch 1 , the inverter INV 2 outputs HIGH for turning on the switch S 2 , the NOR gate NG 2 outputs LOW for turning off the switch S 3 , and the inverter INV 4 outputs LOW for turning off the switch S 4 . Since the switches S 1 and S 2 are both turned on, the current sources I 1 and I 2 are allowed to supply the control currents to the base electrodes of the transistors Q 5 and Q 4 , respectively, serving as the control current signals A and B. On the other hand, since the switches S 3 and S 4 are both turned off, the current sources 13 and 14 are pre vented from supplying any currents to the base electrodes of the drive transistors Q 6 and Q 3 . As a result, the control current supplied from the control voltage source Vc 1 has a magnitude of I 1 +I 2 and the control current supplied from the control voltage source Vc 2 is zero, which may be exemplified by a period T2 shown in FIG. 2 ( b ). In this case, the drive voltage source Vd supplies a forward current to flow from the terminal Na to the terminal Nb through the conductive transistors Q 1 and Q 4 , thereby operating the motor M in the forward rotation mode.

When the forward rotation command signal FWD and the reverse rotation command signal REV are both at the HIGH state, the NOR gate NG 1 outputs LOW for turning off the switch S 1 , the inverter INV 2 outputs HIGH for turning on the switch S 2 , the NOR gate NG 2 outputs LOW for turning off the switch S 3 , and the inverter INV 4 outputs HIGH for turning on the switch S 4 . Since the switches S 1 and S 3 are both turned off, the current sources I 1 and I 3 are prevented from supplying any currents to the base electrodes of the transistors Q 5 and Q 6 . However, since the switches S 2 and S 4 are both turned on, the current sources I 2 and I 4 are allowed to supply the control currents to the base electrodes of the transistors Q 4 and Q 3 , respectively, serving as the control current signals B and D. As a result, the control current supplied from the control voltage source Vc 1 has a magnitude of I 2 and the control current supplied from the control voltage source Vc 2 has a magnitude of I 4 , which may be exemplified by periods T3 and T6 shown in FIG. 2 ( b ). In this case, the motor current is gradually attenuated to zero when circling in a closed loop consisting of the conductive transistors Q 3 and Q 4 and the motor M, which is referred to as the brake mode.

When the forward rotation command signal FWD is at the LOW state and the reverse rotation command signal REV is at the HIGH state, the NOR gate NG 1 outputs LOW for turning off the switch S 1 , the inverter INV 2 outputs LOW for turning off the switch S 2 , the NOR gate NG 2 outputs HIGH for turning on the switch S 3 , and the inverter INV 4 outputs HIGH for turning on the switch S 4 . Since the switches S 1 and S 2 are both turned off, the current sources I 1 and I 2 are prevented from supplying currents to the base electrodes of the drive transistors Q 5 and Q 4 . On the other hand, since the switches S 3 and S 4 are both turned on, the current sources I 3 and I 4 are allowed to supply the control currents to the base electrodes of the drive transistors Q 6 and Q 3 , respectively, serving as the control current signals C and D. As a result, the control current supplied from the control voltage source Vc 1 is zero and the control current supplied from the control voltage source Vc 2 has a magnitude of I 3 +I 4 , which may be exemplified by a period T5 shown in FIG. 2 ( b ). In this case, the drive voltage Vd supplies a reverse current to flow from the terminal Nb to the terminal Na through the conductive transistors Q 2 and Q 3 , thereby operating the motor M in the reverse rotation mode.

It should be noted that the motor control circuit 20 according to the first embodiment of the present invention is further provided with resistors Ra and Rb. The resistor Ra is coupled between the base electrode of the drive transistor Q 5 and the base electrode of the drive transistor Q 4 . During a transient period of the switch S 1 from conductive to nonconductive, the charge accumulated between the base and emitter electrodes of the drive transistor Q 5 may be removed though the resistor Ra and therefore the drive transistor Q 5 is turned off more rapidly. Similarly, the resistor Rb is coupled between the base electrode of the drive transistor Q 6 and the base electrode of the drive transistor Q 3 . During a transient period of the switch S 3 from conductive to nonconductive, the charge accumulated between the base and emitter electrodes of the drive transistor Q 6 may be removed though the resistor Rb and therefore the drive transistor Q 5 is turned off more rapidly.

As described above, the motor control circuit 20 according to the first embodiment of the present invention effectively controls the motor M among the forward rotation mode, the brake mode, and the reverse rotation mode. In addition, the motor control circuit 20 provides the following advantages. Firstly, in one embodiment, each of the current sources 11 to 14 may be implemented by a constant current source which supplies the corresponding one of the control current signals A to D independent of the fluctuation of the control voltage sources Vc 1 and Vc 2 . Therefore, the motor control circuit 20 enhances the operational stability of the motor M.

Referring to FIG. 2 ( b ), a curve 21 illustrates the control current supplied from the control voltage source Vc 1 of the motor control circuit 20 among the operational modes. As clearly identified in the curve 21 , the control voltage source Vc 1 in the brake mode is required to supply a single current I 2 only, in contrast with two currents I 1 and I 2 required in the forward rotation mode. Moreover, the single control current I 2 from the control voltage source Vc 1 in the brake mode is completely applied to drive the transistor Q 4 without being bypassed down to the ground. Therefore, the motor control circuit 20 according to the present invention eliminates the meaningless waste of power and effectively suppresses the rise of temperature. Referring to FIG. 2 ( b ), a curve 22 illustrates the control current supplied from the control voltage source Vc 2 of the motor control circuit 20 among the operational modes. As clearly identified in the curve 22 , the control voltage source Vc 2 in the brake mode is required to supply a single current I 4 only, in contrast with two currents I 3 and I 4 required in the reverse rotation mode. Moreover, the single control current I 4 from the control voltage source Vc 2 in the brake mode is completely applied to drive the transistor Q 3 without being bypassed down to the ground. Therefore, the motor control circuit 20 according to the present invention eliminates the meaningless waste of power and effectively suppresses the rise of temperature. Referring to FIG. 2 ( b ), a curve 23 illustrates a total control current consumption of the motor control circuit 20 among the operational modes, i.e. a superposition of the control currents from the control voltage sources Vc 1 and Vc 2 (the curves 21 and 22 ). As clearly identified in the curve 23 , the total control current consumption in the brake mode is two third smaller than that in the forward or reverse rotation mode. Therefore, the motor control circuit 20 achieves a highly efficient operation.

FIG. 3 is a detailed circuit diagram showing a motor control circuit 30 according to a second embodiment of the present invention. Referring to FIG. 3 , the motor control circuit 30 generates four control current signals A to D from four current sources, respectively, in response to a forward rotation command signal FWD and a reverse rotation command signal REV. Pnp transistors P 1 to P 8 form a current source having multiple parallel output stages, coupled to a control voltage source Vc, for providing a reference current Iref to other components in the circuit. The transistors P 1 and P 2 form a Darlington pair. The transistors P 3 and P 8 , serving as the multiple current output stages, have base electrodes all connected to a base electrode of the transistor P 1 .

First is described in detail how the motor control circuit 30 generates the control current signal A. A collector electrode of the transistor P 6 supplies the reference current Iref to a collector electrode of npn transistor W 1 . Npn transistors W 1 and W 2 form a current mirror, in which the transistor W 1 has its base electrode coupled to its collector electrode. In one embodiment, the transistor W 2 may be designed to have an emitter size twice larger than that of the transistor W 1 , for supplying a twice-larger reference current. Npn transistors Aa to Ae form a current source, functioning as the current source 11 shown in FIG. 2 ( a ). More specifically, the transistors Aa and Ab form a current mirror, in which the transistor Aa has its base electrode coupled to its collector electrode. The transistors Ac to Ae form a current output stage for amplifying the current from a collector electrode of the transistor Ab as the control current signal A. The current mirror formed by the transistors W 1 and W 2 , functioning as the switch S 1 shown in FIG. 2 ( a ), is controlled in accordance with the forward and reverse rotation command signals FWD and REV through npn transistors V 1 , G 1 , and G 2 . More specifically, the transistor V 1 functions as the inverter INV 1 shown in FIG. 2 ( a ) and the transistors G 1 and G 2 together function as the NOR gate NG 1 shown in FIG. 2 ( a ). A base electrode of the transistor V 1 is coupled to receive the forward rotation command signal FWD, a base electrode of the transistor G 1 is coupled to a collector electrode: of the transistor V 1 , and a base electrode of the transistor G 2 is coupled to receive the reverse rotation command signal REV. Collector electrodes of the transistors G 1 and G 2 are together coupled to the base electrodes of the transistors W 1 and W 2 . When the forward rotation command signal FWD is at the HIGH state and the reverse rotation command signal REV is at the LOW state, the transistors G 1 and G 2 are both turned off. The reference current Iref is allowed to pass the current mirror formed by the transistors W 1 and W 2 and then be supplied to the current source formed by the transistors Aa to Ae. In this case, the current source formed by the transistors Aa to Ae is allowed to output a predetermined current, serving as the control current signal A. When the forward rotation command signal FWD is at the LOW state, the transistor G 1 is turned on to make the transistors W 1 and W 2 non-conductive. As a result, the reference current Iref is prevented from being supplied to the current source formed by the transistors Aa to Ae. In this case, the current source formed by the transistors Aa to Ae is prohibited from supplying any currents.

Subsequently is described in detail how the motor control circuit 30 generates the control current signal B. A collector electrode of the transistor P 7 supplies the reference current Iref to a collector electrode of npn transistor W 3 . Npn transistors W 3 and W 4 form a current mirror, in which the transistor W 3 has it base electrode coupled to its collector electrode. In one embodiment, the transistor W 4 may be designed to have an emitter size equal to that of the transistor W 3 , for supplying the same reference current. Npn transistors Ba to Bc form a current source, functioning as the current source 12 shown in FIG. 2 ( a ). More specifically, the transistors Ba and Bb form a current mirror, in which the transistor Ba has its base electrode coupled to its collector electrode. The transistor Bc forms a current output stage for amplifying the current from a collector electrode of the transistor Bb as the control current signal B. The current mirror formed by the transistors W 3 and W 4 , functioning as the switch S 2 shown in FIG. 2 ( a ), is controlled in accordance with the forward rotation command signal FWD through npn transistors V 1 and V 2 . More specifically, the transistor V 1 functions as the inverter INV 1 shown in FIG. 2 ( a ) and the transistor V 2 functions as the inverter INV 2 shown in FIG. 2 ( a ). A base electrode of the transistor V 1 is coupled to receive the for ward rotation command signal FWD and a base electrode of the transistor V 2 is coupled to a collector electrode of the transistor V 1 . A collector electrode of the transistor V 2 is coupled to the base electrodes of the transistors W 3 and W 4 . When the forward rotation command signal FWD is at the HIGH state, the transistor V 2 is turned off. The reference current Iref is allowed to pass the current mirror formed by the transistors W 3 and W 4 and then be supplied to the current source formed by the transistors Ba to Bc. In this case, the current source formed by the transistors Ba to Bc is allowed to output a predetermined current, serving as the control current signal B. When the forward rotation command signal FWD is at the LOW state, the transistor V 2 is turned on to make the transistors W 3 and W 4 nonconductive. As a result, the reference current Iref is prevented from being supplied to the current source formed by the transistors Ba to Bc. In this case, the current source formed by the transistors Ba to Bc is prohibited from supplying any currents.

Subsequently is described in detail how the motor control circuit 30 generates the control current signal C. A collector electrode of the transistor P 5 supplies the reference current Iref to a collector electrode of npn transistor W 5 . Npn transistors W 5 and W 6 form a current mirror, in which the transistor W 5 has its base electrode coupled to its collector electrode. In one embodiment, the transistor W 6 may be designed to have an emitter size twice larger than that of the transistor W 5 , for supplying a twice-larger reference current. Npn transistors Ca to Ce form a current source, functioning as the current source 13 shown in FIG. 2 ( a ). More specifically, the transistors Ca and Cb form a current mirror, in which the transistor Ca has its base electrode coupled to its collector electrode. The transistors Cc to Ce form a current output stage for amplifying the current from a collector electrode of the transistor Cb as the control current signal C. The current mirror formed by the transistors W 5 and W 6 , functioning as the switch S 3 shown in FIG. 2 ( a ), is controlled in accordance with the forward and reverse rotation command signals FWD and REV through npn transistors V 3 , G 3 , and G 4 . More specifically, the transistor V 3 functions as the inverter INV 3 shown in FIG. 2 ( a ) and the transistors G 3 and G 4 together function as the NOR gate NG 2 shown in FIG. 2 ( a ). A base electrode of the transistor V 3 is coupled to receive the reverse rotation command signal REV, a base electrode of the transistor G 3 is coupled to a collector electrode of the transistor V 3 , and a base electrode of the transistor G 4 is coupled to receive the forward rotation command signal FWD. Collector electrodes of the transistors G 3 and G 4 are together coupled to the base electrodes of the transistors W 5 and W 6 . When the reverse rotation command signal REV is at the HIGH state and the forward rotation command signal FWD is at the LOW state, the transistors G 3 and G 4 are both turned off. The reference current Iref is allowed to pass the current mirror formed by the transistors W 5 and W 6 and then be supplied to the current source formed by the transistors Ca to Ce. In this case, the current source formed by the transistors Ca to Ce is allowed to output a predetermined current, serving as the control current signal C. When the reverse rotation command signal REV is at the LOW state, the transistor G 3 is turned on to make the transistors W 5 and W 6 nonconductive. As a result, the reference current Iref is prevented from being supplied to the current source formed by the transistors Ca to Ce. In this case, the current source formed by the transistors Ca to Ce is prohibited from supplying any currents.

Subsequently is described in detail how the motor control circuit 30 generates the control current signal D. A collector electrode of the transistor P 4 supplies the reference current Iref to a collector electrode of npn transistor W 7 . Npn transistors W 7 and W 8 form a current mirror, in which the transistor W 7 has it base electrode coupled to its collector electrode. In one embodiment, the transistor W 8 may be designed to have an emitter size equal to that of the transistor W 7 , for supplying the same reference current. Npn transistors Da to Dc form a current source, functioning as the current source 14 shown in FIG. 2 ( a ). More specifically, the transistors Da and Db form a current mirror, in which the transistor Da has its base electrode coupled to its collector electrode. The transistor Dc forms a current output stage for amplifying the current from a collector electrode of the transistor Db as the control current signal D. The current mirror formed by the transistors W 7 and W 8 , functioning as the switch S 4 shown in FIG. 2 ( a ), is controlled in accordance with the reverse rotation command signal REV through npn transistors V 3 and V 4 . More specifically, the transistor V 3 functions as the inverter INV 3 shown in FIG. 2 ( a ) and the transistor V 4 functions as the inverter INV 4 shown in FIG. 2 ( a ). A base electrode of the transistor V 3 is coupled to receive the reverse rotation command signal REV and a base electrode of the transistor V 4 is coupled to a collector electrode of the transistor V 3 . A collector electrode of the transistor V 4 is coupled to the base electrodes of the transistors W 7 and W 8 . When the reverse rotation command signal REV is at the HIGH state, the transistor V 4 is turned off. The reference current Iref is allowed to pass the current mirror formed by the transistors W 7 and W 8 and then be supplied to the current source formed by the transistors Da to Dc. In this case, the current source formed by the transistors Da to Dc is allowed to output a predetermined current, serving as the control current signal D. When the reverse rotation command signal REV is at the LOW state, the transistor V 4 is turned on to make the transistors W 7 and W 8 nonconductive. As a result, the reference current Iref is prevented from being supplied to the current source formed by the transistors Da to Dc. In this case, the current source formed by the transistors Da to Dc is prohibited from supplying any currents.

While the invention has been described by way of examples and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications.