Semiconductor wafer having identification indication

This application claims priority from Korean Patent Application No. 2002-61718 filed on Oct. 10, 2002, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.

The present invention generally relates to a semiconductor device and specifically to a semiconductor wafer having an identification indication and a method of fabricating the same.

In order to analyze various process steps in the fabrication of semiconductor devices, a method for identifying each semiconductor wafer is usually required. Conventionally, identification indications such as letters, numerals, or bar cords are written on each of the semiconductor wafers. The identification indication provides a method to identify each wafer after process conditions are applied to each of the wafers. By having an identification indication on each wafer the results of exposing the wafers to the conditions can be analyzed. This analysis of the effects of process conditions on wafers makes failure analysis and process feedback feasible, thus reducing the time for developing products and preventing errors from being repeated.

Generally, the identification indication is carved on top of the semiconductor substrate using a laser beam.

FIG. 1 is a diagram of a top plane view of a semiconductor wafer having an identification indication in accordance with the prior art. FIG. 2 is a diagram of a perspective view of a marking region illustrated in FIG. 1 . FIG. 3 is a vertical cross-sectional view diagram taken along a line I-I′ of FIG. 2 , which shows dots that are formed by laser marking.

Referring to FIGS. 1 , 2 , and 3 , a marking region 20 is disposed at an edge 15 of an upper side of a semiconductor wafer 10 . The marking region 20 is where an identification indication is written. Therefore, the usable chip region 25 , in which semiconductor devices are formed, is decreased by as much area as is needed for the marking region 20 . If the area of the chip region 25 decreases, then fewer chips can be produced per wafer, which leads to an increase in the unit cost of the semiconductor production.

In addition, the identification indication is composed of dots 30 that are conventionally formed by laser beam. As illustrated in FIG. 3 , the dots 30 do not have flat shapes. This potentially can cause problems during the subsequent process of forming the semiconductor circuits on the wafer such as particle defects due to the non-uniform shape of the identification indication. In addition, the non-flat shapes of the dots 30 may cause a chuck defect while the semiconductor wafer 10 is being fixed.

One aspect of the present invention is directed to effectively utilizing the area of a semiconductor wafer. Another aspect of the present invention is directed to reducing the particle defects due to a non-uniform shape of the identification indication on a semiconductor wafer.

In accordance with broad aspects of the present invention, a semiconductor wafer including an outwardly convex edge section is provided. The convex edge is divided into an upper side surface and a lower side surface The lower side surface can be wider than the upper side surface. Furthermore a wider region of the lower side surface of the wafer can also be formed to be thicker than the upper side surface. This formation of different side surfaces can be applied to the entire circumference of the wafer as well.

The marking region is disposed at the wide region of the lower side surface of the convex edge. The wafer identification indication is still preferably composed of dots formed by a laser beam and may further include additional information, such as a bar code.

FIG. 1 is a top plane view diagram of a semiconductor wafer having an identification indication that is fabricated in accordance with prior art.

FIG. 2 is a perspective view diagram of a typical identification indication.

FIG. 3 is a vertical cross-sectional view diagram taken along line I-I′ of FIG. 2 , showing the identification indication.

FIG. 4 is a diagram that shows a front side of the semiconductor wafer in accordance with an embodiment of the present invention.

FIG. 5A is a diagram that shows a back side of the semiconductor wafer in accordance with this embodiment of the present invention.

FIG. 5B is a diagram that shows a back side of the semiconductor wafer in accordance with another embodiment of the present invention.

FIG. 6 is a perspective view diagram of a side of the semiconductor wafer in accordance with the embodiment of the present invention described first.

FIG. 7 is a perspective view diagram of a side of a semiconductor wafer with symmetric side surfaces.

FIG. 8 is a perspective view diagram of a side of the semiconductor wafer in accordance with yet another embodiment of the present invention.

The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention, however, may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity.

FIG. 4 shows a front side of a semiconductor wafer in accordance with an embodiment of the present invention. FIG. 5A shows a back side of the semiconductor wafer in accordance with this embodiment.

Referring to FIGS. 4 and 5A , a semiconductor wafer includes a top surface 130 , a bottom surface 135 , and a side surface 120 . Additionally, a chip region 110 and an edge region are disposed on the top surface 130 . The chip region 110 is the region where semiconductor devices are fabricated and defined by a scribe line. The edge region is the rest of the top surface 130 not included in the chip region 110 , and it borders the side surface 120 of the wafer.

The side surface 120 is not strictly perpendicular to the top 130 and the bottom 135 surfaces, but is rather formed in an outward convex shape such as that shown in FIG. 7 . The convex side surface 120 is divided into an upper side surface 122 and a lower side surface 124 . There is a boundary between the upper surface 122 which forms the top part of the convex shape and the top 130 and there is a boundary between the lower surface 124 and the bottom surface 135 .

The upper side surface 122 is preferably formed to have a constant width L 1 along an entire circumference of the semiconductor wafer 100 . Meanwhile, the lower side surface 124 is divided into a narrow region 150 and a wide region 160 . The wide region 160 has a width L 3 , which is larger than a width L 2 of the narrow region 150 . The width L 3 is also larger than the width L 1 of the upper side surface 122 .

As illustrated in FIGS. 5A and 7 , a cross-section of the side 120 may be symmetric. That is, the upper side surface 122 and the lower side surface 124 may be identical in a width and in a thickness (i.e., L 1 =L 2 , and h 1 ′=h 2 ′). This symmetric side 120 is preferably formed at the narrow region 150 .

A marking region 200 , which is the region where an identification indication 300 is written, is disposed at the wide region 160 of the lower side surface 124 . Forming the identification indication 300 here can prevent particles caused by the non-uniformly-shaped dots from being transferred into the chip region 110 . In addition, the marking region 200 is not formed on the top surface 130 of the semiconductor wafer where the semiconductor devices are formed. Thus, more of the top surface of the wafer can be efficiently utilized for the chip region 110 .

A vacuum chucking method, which utilizes a pressure of vacuum, may be used so as to fix the semiconductor wafer 100 . The vacuum chucking method requires close adhesion between a vacuum chuck and the semiconductor wafer 110 . Thus, by forming the marking region 200 on the lower side surface 124 of the wafer, a chucking fault of the semiconductor wafer 100 due to non-uniform shape of the identification indication 300 can be prevented.

Another embodiment of the present inventive idea can be performed, as illustrated in FIG. 5B . In this alternate embodiment the lower side surface 124 may be formed to have a constant width L 3 ′ along an entire circumference of the semiconductor wafer 100 . In this case, the lower side 124 forms wide region 160 throughout the circumference. The width L 3 ′ is preferably wider than the width L 1 of the upper side surface 122 . Again the marking region 200 is disposed at the lower side surface 124 .

In the above two embodiments, the lower side surface 124 , where the marking region is disposed, is wider than the upper side surface 122 , such that the semiconductor wafer 100 may have asymmetrical lateral surfaces. That is, as illustrated by the cross-sectional diagram of the marking region 200 of the semiconductor wafer in FIG. 6 , the lower side surface 124 is wider than at the upper side surface 122 . In addition, a thickness h 1 of the upper side surface 122 is preferably thinner than a thickness h 2 of the lower side surface 124 at the wide region 160 (i.e., h 1 <h 2 ).

An identification indication 300 including carved symbols, such as numerals or letters, is formed at the marking region 200 . The symbols composing the identification indication 300 are preferably formed of a plurality of dots that are carved by a laser. Meanwhile, as illustrate in FIG. 8 , the identification indication 300 may comprise patterns having information, such as, for example, a bar code.

According to the present invention, a wider region disposed at a lower side surface of a semiconductor wafer is an advantageous location for an identification indication. By locating an identification indication on a lower side surface, a top surface of the semiconductor wafer can be efficiently utilized in the fabrication of semiconductor chips. Not only is there more useable area on the top surface, but also a particle problem and chuck fixing fault, which are due to the non-uniform shape of the identification region, can be prevented. As a result of decreasing faults, manufacturing productivity the semiconductor chips can be increased and production costs can be reduced.