Semiconductor memory device

This invention relates to a semiconductor memory device such as a flash module.

To increase the scale of memory capacity of a conventional semiconductor memory device, a method of increasing the size of each memory cell array of a flash memory may be employed. For example, the number of word lines of each memory cell array is increased from 512 to 1024.

As another method for increasing the scale of memory capacity of the conventional semiconductor memory device, the number of memory cell arrays provided in a flash memory may be increased. For example, the number of memory cell arrays is increased from one to four, or from four to eight. JP-A-2001-84777 discloses a flash memory having four memory cell array units (in this publication, a memory cell array unit not including a control circuit is referred to as “BANK”).

However, since both of the above-described methods employ development of a new flash memory (that is, the size of memory cell arrays is increased in the former method and the number of memory cell arrays is increased in the latter method), the capability of each constituent block constituting the flash memory, the layout of the flash memory and the like needs to be redesigned. In the case the flash memory is redesigned, its interface circuit needs to be redesigned, too. Therefore, both of the above-described methods will take time for product development.

Moreover, as the size of each memory cell array is increased, the evaluation time for the flash module using an LSI tester increases. For example, in the case of evaluating a memory module that is newly developed with the size of each memory cell array doubled from 512 word lines by 512 bit lines to 1024 word lines by 512 bit lines, using an LSI tester, the test time is twice that for a memory module of the conventional size. This is because, in the case of evaluating a memory module with the double number of sectors (double number of word lines), the number of times of rewriting, which is carried out on each word line, is doubled and as a result, the practical rewrite test time for the flash module using the LSI tester is doubled, too.

The present invention may provide a semiconductor memory device that does not need redesigning of a memory cell array and a memory block having a control circuit for the memory cell array and enables increase in scale of memory capacity simply by making a simple design change of an interface circuit.

Further, the present invention may provide a semiconductor memory device that can restrain increase in test time even when the memory capacity is increased.

A semiconductor memory device according to the present invention includes memory banks each including a memory cell array and a control circuit for the memory cell array and an interface circuit shared by the plural memory banks. The semiconductor memory device is adapted for performing reading of data from the plural memory banks and rewriting of data to the plural memory banks. In an operation mode for reading, the following processing is performed: processing A 1 in which the interface circuit outputs an active read enable signal to the plural memory banks; processing A 2 in which the interface circuit outputs address information specifying a memory cell as a reading target to the plural memory banks; processing A 3 in which each of the plural memory banks reads out data of the memory cell specified by the inputted address information and outputs the read-out data as an output data group to the interface circuit; and processing A 4 in which the interface circuit selectively outputs one of plural output data groups outputted from the plural memory banks, to outside. In an operation mode for rewriting, the following processing is performed: processing B 1 in which the interface circuit output address information specifying a memory cell as a rewriting target to the plural memory banks; processing B 2 in which the interface circuit outputs an input data group from outside to the plural memory banks; processing B 3 in which the interface circuit selectively outputs an active write enable signal to one of the plural memory banks; and processing B 4 in which a memory bank to which the active write enable signal is inputted, of the plural memory banks, rewrites data of the memory cell specified by the address information to data of the input data group.

The memory bank to which the active write enable signal is inputted, of the plural memory banks, may output a busy signal indicating that it is during the processing B 4 , and the interface circuit may output an active write enable signal to a memory bank that is not outputting a busy signal even during a period when the interface circuit is receiving a busy signal from at least one of the plural memory banks.

Moreover, in a test mode for the plural memory banks, the following processing may be performed: processing C 1 in which the interface circuit outputs address information specifying a memory cell as a rewriting target to the plural memory banks; processing C 2 in which the interface circuit outputs an input data group from outside to the plural memory banks; processing C 3 in which the interface circuit outputs an active write enable signal to the plural memory banks; and processing C 4 in which the plural memory banks rewrite data of the memory cell specified by the address information to data of the input data group.

As described above, according to the present invention, it is possible to control the plural memory banks of the same structure as that of the conventional memory bank simply by adding a simple circuit to the interface circuit. Therefore, according to the present invention, redesigning of the memory banks themselves is not necessary and it is possible to increase the scale of memory capacity of the memory cell arrays of the memory banks simply by making a simple design change of the interface circuit. According to the present invention, since the circuit change is thus minimized, development of a semiconductor memory device can be made in a short period.

Moreover, in the present invention, in the case the function to enable activate all write enable signals in the test mode is provided, the same data can be simultaneously written into all the plural memory banks and the rewriting test time can be shortened.

Furthermore, in the present invention, in the case there is provided the function to enable output of an active write enable signal to a memory bank that is not activating a busy signal even when one of the memory banks is activating a busy signal, during data rewriting of the memory cell of one memory bank, data loading to the other memory bank and data rewriting to its memory cell can be started, and the rewriting test time using an LSI tester or the like can be shortened.

FIG. 1 is a block diagram schematically showing the structure of a flash module according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining a reading operation in the flash module of FIG. 1 .

FIG. 3 is a timing chart for explaining a rewriting operation in the flash module of FIG. 1 .

FIG. 4 is a block diagram schematically showing the structure of a flash module according to a second embodiment of the present invention.

FIG. 5 is a timing chart for explaining a rewriting operation in the flash module of FIG. 4 .

FIG. 6 is a block diagram schematically showing the structure of a flash module according to a third embodiment of the present invention.

FIG. 7 is a timing chart for explaining a rewriting operation in the flash module of FIG. 6 .

First Embodiment

FIG. 1 is a block diagram schematically showing the structure of a flash module according to a first embodiment of the present invention.

The flash module (semiconductor memory device) according to the first embodiment includes two flash memories (memory banks) FM 1 and FM 2 , and an interface circuit IF 1 . The flash memory FM 1 and the flash memory FM 2 have the same structure. The flash module according to the first embodiment is built in, for example, in a system LSI, and stores a program code of MCU.

As shown in FIG. 1 , each of the flash memories FM 1 and FM 2 has memory cell arrays MC 1 to MC 4 , X decoder blocks XD 1 to XD 4 , Y decoder blocks YD 1 to YD 4 , Y gate blocks YG 1 to YG 4 , data register blocks DR 1 to DR 4 , a control block C 1 , a sector address input buffer SAB, a Y address input buffer YAB, a data input buffer DIB, and a data output buffer DOB.

The X decoder blocks XD 1 to XD 4 are arranged adjacently to the memory cell arrays MC 1 to MC 4 , respectively. The data register blocks DR 1 to DR 4 are arranged adjacently to the memory cell arrays MC 1 to MC 4 , respectively. The Y gate blocks YG 1 to YG 4 are arranged adjacently to the data register blocks DR 1 to DR 4 , respectively. The Y decoder blocks YD 1 to YD 4 are arranged adjacently to the Y gate blocks YG 1 to YG 4 , respectively.

A write enable signal WEB 1 (or WBE 2 ) and a read enable signal REB outputted from the interface circuit IF 1 are inputted to the control block C 1 . The control block C 1 receives the write enable signal WEB 1 (or WEB 2 ) and the read enable signal REB and executes data rewriting of a memory cell, reading of a memory cell and the like. The control block C 1 outputs an internal control signal group CO based on the inputted write enable signal WEB 1 (or WEB 2 ) and read enable signal REB to the sector address input buffer SAB, the Y address input buffer YAB, the data input buffer DIB and the data output buffer DOB.

To the sector address input buffer SAB, a sector address group SA outputted from the interface circuit IF 1 and the internal control signal group CO outputted from the control block C 1 are inputted. The sector address input buffer SAB is controlled on the basis of the inputted internal control signal group CO. The sector address input buffer SAB converts the inputted sector address group SA to an internal sector address group SABO and outputs the internal sector address group SABO to the X decoder blocks XD 1 to XD 4 .

To the Y address input buffer YAB, a Y address group YA outputted from the interface circuit IF 1 and the internal control signal group CO outputted from the control block C 1 are inputted. The Y address input buffer YAB is controlled on the basis of the inputted internal control signal group CO. The Y address input buffer YAB converts the inputted Y address group YA to an internal Y address group YABO and outputs the internal Y address group YABO to the Y decoder blocks YD 1 to YD 4 .

To the data input buffer DIB, an input data group DI outputted from the interface circuit IF 1 and the internal control signal group CO outputted from the control block C 1 are inputted. The data input buffer DIB is controlled on the basis of the inputted internal control signal group CO. The data input buffer DIB converts the inputted input data group DI to an internal input data group DIBO and outputs the internal input data group DIBO to the Y gate blocks YG 1 to YG 4 .

To the data output buffer DOB, an input internal output data group DOBI outputted from the Y gate blocks YG 1 to YG 4 and the internal control signal group CO outputted from the control block C 1 are inputted. The data output buffer DOB is controlled on the basis of the inputted internal control signal group CO. The data output buffer DOB converts the input internal output data group DOBI to an output data group DO 1 (or DO 2 ) and outputs the output data group to the interface circuit IF 1 .

In each of the memory cell arrays MC 1 to MC 4 , memory cells for storing data are arranged in a matrix. Each of the memory cell arrays MC 1 to MC 4 has 512 word lines arrayed in parallel, 512 bit lines arrayed in parallel in a direction intersecting the word lines, and the memory cells arranged at the points of intersection of the word lines and the bit lines. The number of word lines and the number of bit lines are not limited to the above-described numbers. The number of memory cell arrays is not limited to four, either.

Each of the data register blocks DR 1 to DR 4 temporarily stores data to be written to a memory cell at the time of data loading in the rewriting operation. Each of the data register blocks DR 1 to DR 4 has a latch circuit for storing data every bit line. Each of the data register blocks DR 1 to DR 4 transmits the stored data to a memory cell of a selected sector address through the bit line, thereby rewriting data stored in the memory cell.

Each of the Y gate blocks YG 1 to YG 4 has a transistor group arranged every bit line and adapted for sending and receiving data to and from the bit line. Each of the Y gate blocks YG 1 to YG 4 outputs data of a selected memory cell as an internal output data group DOBI at the time of data reading operation. At the time of data loading in the rewriting operation, the Y gate blocks YG 1 to YG 4 convert input data to an internal input data group DIBO and transmit the internal input data group DIBO to the data register blocks DR 1 to DR 4 , respectively.

To the X decoder blocks XD 1 to XD 4 , the same internal sector address group SABO is inputted. The X decoder blocks XD 1 to XD 4 decode the internal sector address group SABO and simultaneously select arbitrary word lines in the memory cell arrays MC 1 to MC 4 , respectively.

To the Y decoder blocks YD 1 to YD 4 , the same internal Y address group YABO is inputted. The Y decoder blocks YD 1 to YD 4 decode the internal Y address group YABO.

In accordance with the Y address group YA, arbitrary Y gates in the Y gate blocks YG 1 to YG 4 are simultaneously selected and arbitrary latch circuits in the data register blocks DR 1 to DR 4 are simultaneously selected. Also arbitrary bit lines in the memory cell arrays MC 1 to MC 4 are simultaneously selected. In accordance with the sector address group SA and the Y address group YA, arbitrary memory cells are selected.

The interface circuit IF 1 enables operations in a ROM writer, an LSI tester, a CPU mode and a serial mode. In each of these modes, the interface circuit IF 1 converts a signal from outside of the flash module so as to operate the flash memory FM 1 or FM 2 . The interface circuit IF 1 has an interface core block IC 1 , a write enable signal control circuit WEC 1 , a selector element S 1 , and a selector element S 2 .

The interface core block IC 1 has a structure in which a function to output a bank address group BA for selecting one of the flash memories FM 1 and FM 2 is added to a conventional interface circuit. The interface core block IC 1 outputs the write enable signal WEB and the bank address group BA to the write enable signal control circuit WEC 1 . The interface core block IC 1 outputs the bank address group BA to the selector element S 1 for selectively outputting an output data group and the selector element S 2 for selectively outputting a busy signal. The interface core block IC 1 outputs the read enable signal REB, the sector address group SA, the Y address group YA and the input data group DI to the flash memories FM 1 and FM 2 .

To the interface core block IC 1 , an output data group DO outputted from the selector element S 1 and a busy signal BUSY outputted from the selector element S 2 are inputted. The busy signal BUSY indicates whether the flash memory FM 1 or FM 2 is performing the rewriting operation or not. Also an external input signal IFIN, which is an input signal to the flash module, is inputted to the interface core block IC 1 . The interface core block IC 1 outputs an external output signal IFOUT, which is a flash module output signal.

The write enable signal control circuit WEC 1 includes inverter elements INV 1 to INV 3 , and NOR elements NOR 1 and NOR 2 . The write enable signal WEB is inputted to one input terminal of each of the NOR elements NOR 1 and NOR 2 , and the bank address group BA is inputted to the other input terminal of the NOR element NOR 1 and the input terminal of the inverter element INV 1 . An output of the inverter element INV 1 is inputted to the other input terminal of the NOR element NOR 2 via a node N 1 . An output of the NOR element NOR 1 is inputted to the input terminal of the inverter terminal INV 2 via a node N 2 . An output of the NOR element NOR 2 is inputted to the input terminal of the inverter element INV 3 via a node N 3 . An output of the inverter element INV 2 is inputted to the flash memory FM 1 as the write enable signal WEB 1 .

The output data group DO 1 and DO 2 from the flash memories FM 1 and FM 2 are inputted to the input terminal of the selector element S 1 , and the bank address group BA is inputted to the selector terminal of the selector element S 1 . The selector element S 1 outputs the output data group DO to the interface core block IC 1 . When the bank address group BA has a ground potential Vss, the selector element S 1 outputs the output data group DO 1 as the output data group DO. When the bank address group BA has a power-supply potential Vdd, the selector element S 1 outputs the output data group DO 2 as the output data group DO.

Busy signals BUSY 1 and BUSY 2 from the flash memories FM 1 and FM 2 are inputted to the input terminal of the selector element S 2 , and the bank address group BA is inputted to the selector terminal of the selector element S 2 . The selector element S 2 outputs the busy signal BUSY to the interface core block IC 1 . When the bank address group BA has a ground potential Vss, the selector element S 2 outputs the busy signal BUSY 1 as the busy signal BUSY. When the bank address group BA has a power-supply potential Vdd, the selector element S 2 outputs the busy signal BUSY 2 as the busy signal BUSY.

FIG. 2 is a timing chart for explaining the reading operation in the flash module according to the first embodiment.

As shown in FIG. 2 , in the initial state, the bank address group BA has the ground potential Vss, and the sector address group SA and the Y address group YA select arbitrary addresses. The read enable signal REB has the power-supply potential Vdd, and the output data groups DO 1 and DO 2 and the output data group DO have the ground potential Vss.

In the reading operation period (reading operation mode), the read enable signal REB has the power-supply potential Vdd, and the write enable signal WEB and the write enable signals WEB 1 and WEB 2 have the power-supply potential Vdd. The busy signals BUSY 1 and BUSY 2 and the busy signal BUSY have the ground potential Vss, and the input data group DI may have the power-supply potential Vdd or the ground potential Vss.

Next, when the read enable signal REB is turned to the ground potential Vss (time point t 1 ), data of memory cells of arbitrary addresses selected by the sector address group SA and the Y address group YA in the flash memories FM 1 and FM 2 are read out and outputted as the output data groups DO 1 and DO 2 (time point t 2 ). At this point, since the bank address group BA has the ground potential Vss, the output data group DO 1 is selected by the selector element S 1 and the output data group DO 1 is outputted as the output data group DO.

Next, when the bank address group BA is switched to the power-supply potential Vdd and addresses selected by the sector address group SA and the Y address group YA are switched (time point t 3 ), data of newly selected memory cells in the flash memories FM 1 and FM 2 are read out and outputted as the output data groups DO 1 and DO 2 , respectively (time point t 4 ). At this point, since the bank address group BA has the power-supply potential Vdd, the output data group DO 2 is selected by the selector element S 1 and the output data group DO 2 is outputted as the output data group DO. As an operation similar to the operation from the time point t 3 to the time point t 4 is repeated, data is continuously read out from the flash memories FM 1 and FM 2 .

After that, when the read enable signal REB is turned to the power-supply potential Vdd (time point t 5 ), the output data groups DO 1 and DO 2 and the output data group DO have the ground potential Vss and the reading operation ends (time point t 6 ).

FIG. 3 is a timing chart for explaining the rewriting operation in the flash module according to the first embodiment. In this case, an operation to rewrite data of a memory cell in a sector of an arbitrary address in the flash memory FM 1 and then rewrite data of a memory cell in a sector of an arbitrary address in the flash memory FM 2 will be described.

As shown in FIG. 3 , in the initial state, the bank address group BA has the power-supply potential Vdd, and the write enable signal WEB has the power-supply potential Vdd. The busy signals BUSY 1 and BUSY 2 and the busy signal BUSY have the ground potential Vss. The sector address group SA and the Y address group YA select arbitrary addresses. The input data group DI has arbitrary data. All the nodes N 1 to N 3 have the ground potential Vss, and both of the write enable signals WEB 1 and WEB 2 have the power-supply potential Vdd. During the rewriting operation period (rewriting operation mode), the read enable signal REB is held at the power-supply potential Vdd.

Next, when the bank address group BA is switched to the ground potential Vss to select the flash memory FM 1 , and the node N 1 is switched to the power-supply potential Vdd. The sector address group SA is switched to the address of a sector (word line) in which rewriting is to be executed, and the Y address group YA is switched to the address of the latch circuit of the data register blocks DR 1 to DR 4 to which data is to be loaded first (time point t 1 a). The bank address group BA and the sector address group SA maintain this state during the loading.

Next, when the write enable signal WEB is turned to the ground potential Vss, the node N 2 is switched to the power-supply potential Vdd and the write enable signal WEB 1 is switched to the ground potential Vss. At the leading edge of this write enable signal WEB 1 , the latch circuit of the target one of the data register blocks DR 1 to DR 4 in the flash memory FM 1 is selected, and the input data group DI becomes data to be loaded to the latch circuit (time point t 2 a). Then, as the write enable signal WEB is turned to the power-supply potential Vdd, the node N 2 is switched to the ground potential Vss and the write enable signal WEB 1 is switched to the power-supply potential Vdd. At the leading edge of this write enable signal WEB 1 , the data of the input data group DI of the flash memory FM 1 is loaded to the target one of data register blocks DR 1 to DR 4 (time point t 3 a). Next, the Y address group YA selects the address of the latch circuit of the data register blocks DR 1 to DR 4 of the flash memory FM 1 to which the second data is to be loaded, and in such a manner, an operation similar to the operation from the time point t 1 a to the time point t 3 a is executed to the latch circuits of all the data register blocks DR 1 to DR 4 , for example, 512 cycles.

When data loading to the latch circuits of all the data register blocks DR 1 to DR 4 of the flash memory FM 1 is completed, the flash memory FM 1 itself automatically starts the rewriting operation to all the memory cells selected by the sector address group SA using the data of the data register blocks DR 1 to DR 4 . The busy signal BUSY 1 is switched to the power-supply potential Vdd and the busy signal BUSY is switched to the power-supply potential Vdd via the selector element S 2 (time point t 4 a).

During the period when the busy signal BUSY has the power-supply potential Vdd, access to the flash memories FM 1 and FM 2 is inhibited. When the rewriting operation is completed, the busy signal BUSY 1 is switched to the ground potential Vss and the busy signal BUSY is switched to the ground potential Vss via the selector element S 2 . The inhibition of access to the flash memories FM 1 and FM 2 is canceled and the rewriting operation to the flash memory FM 1 ends (time point t 5 a).

Next, the bank address group BA is switched to the power-supply potential Vdd to select the flash memory FM 2 , the node N 1 is switched to the ground potential Vss, the sector address group SA is switched to the address of a sector (word line) in which rewriting is to be executed, and the Y address group YA is switched to the address of the latch circuit of the data register blocks DR 1 to DR 4 to which data is to be loaded first. In such a manner, the operation from the time point t 1 b to the time point t 5 b (rewriting operation to the flash memory FM 2 ) is executed similarly to the foregoing operation from the time point t 1 a to the time point t 5 a (rewriting operation to the flash memory FM 1 ).

As described above, in the flash module according to the first embodiment, the function to output the bank address BA is added to the interface core block IC 1 of the interface circuit IF 1 , and the selector element S 1 and the write enable signal selector circuit WEC 1 are additionally provided in the interface circuit IF 1 , thereby enabling control of the plural flash memories having the same structure as that of the conventional flash memory. Therefore, with the flash module according to the first embodiment, redesigning of the flash memories themselves is not necessary and it is possible to increase the scale of memory capacity of the memory cell arrays of the flash module simply by making a simple design change of the interface circuit. With the flash module according to the first embodiment, since the circuit change is thus minimized, development of the flash module can be made in a short period.

Moreover, with the flash module according to the first embodiment, since the circuit newly added to the interface circuit is small-scaled, the increase in layout size of the interface circuit can be minimized.

Second Embodiment

FIG. 4 is a block diagram schematically showing the structure of a flash module according to a second embodiment of the present invention.

The structure of flash memories FM 1 and FM 2 is the same as the structure described in the first embodiment. External signals inputted to and outputted from the flash memories FM 1 and FM 2 are the same as those described in the first embodiment. The flash module (semiconductor memory device) according to the second embodiment includes the two flash memories (memory banks) FM 1 and FM 2 , and one interface circuit IF 2 .

The interface circuit IF 2 has an interface core block IC 1 , a write enable signal control circuit WEC 1 , a selector element S 1 , and a busy signal control circuit BC 1 . The structures of the interface core block IC 1 , the write enable signal control circuit WEC 1 and the selector element S 1 are the same as those described in the first embodiment.

The busy signal control circuit BC 1 includes a NOR element NOR 3 and an inverter element INV 4 . Busy signals BUSY 1 and BUSY 2 are inputted to the input terminals of the NOR element NOR 3 , respectively, and an output of the NOR element NOR 3 is inputted to the input terminal of the inverter element INV 4 via a node N 4 . A busy signal BUSY outputted from the output terminal of the inverter element INV 4 is inputted to the interface core block IC 1 . The interface circuit IF 2 is so constituted that even when one of the flash memories FM 1 or FM 2 is performing a rewriting operation and its busy signal BUSY 1 or BUSY 2 and the busy signal BUSY have a power-supply potential Vdd, the other flash memory with its busy signal not having the power-supply potential Vdd can be accessed for the rewriting operation.

A data reading operation in the flash module according to the second embodiment is the same as the data reading operation in the flash module according to the first embodiment.

FIG. 5 is a timing chart for explaining the rewriting operation in the flash module according to the second embodiment. In this case, an operation to rewrite data of a memory cell in a sector of an arbitrary address in the flash memory FM 1 and then rewrite data of a memory cell in a sector of an arbitrary address in the flash memory FM 2 will be described.

As shown in FIG. 5 , in the initial state, the bank address group BA has the power-supply potential Vdd, and the write enable signal WEB has the power-supply potential Vdd. The busy signals BUSY 1 and BUSY 2 have the ground potential Vss. The sector address group SA and the Y address group YA select arbitrary addresses. The input data group DI has arbitrary data. All the nodes N 1 to N 3 have the ground potential Vss, and both of the write enable signals WEB 1 and WEB 2 have the power-supply potential Vdd. The node N 4 has the power-supply potential Vdd and the busy signal BUSY has the ground potential Vss. During the rewriting operation period (rewriting operation mode), the read enable signal REB is held at the power-supply potential Vdd.

Next, when the bank address group BA is switched to the ground potential Vss to select the flash memory FM 1 , and the node N 1 is switched to the power-supply potential Vdd. The sector address group SA is switched to the address of a sector (word line) in which rewriting is to be executed, and the Y address group YA is switched to the address of the latch circuit of the data register blocks DR 1 to DR 4 to which data is to be loaded first (time point t 21 ).

The bank address group BA and the sector address group SA maintain this state during the loading. When the write enable signal WEB is turned to the ground potential Vss, the node N 2 is switched to the power-supply potential Vdd and the write enable signal WEB 1 is switched to the ground potential Vss. At the leading edge of this write enable signal WEB 1 , the latch circuit of the target one of the data register blocks DR 1 to DR 4 in the flash memory FM 1 is selected, and the input data group DI becomes data to be loaded to the latch circuit (time point t 22 ).

Next, as the write enable signal WEB is switched to the power-supply potential Vdd, the node N 2 is switched to the ground potential Vss and the write enable signal WEB 1 is switched to the power-supply potential Vdd. At the leading edge of this write enable signal WEB 1 , the data of the input data group DI of the flash memory FM 1 is taken into the latch circuit of the target one of data register blocks DR 1 to DR 4 (time point t 23 ).

Next, the Y address group YA selects the address of the latch circuit of the data register blocks DR 1 to DR 4 of the flash memory FM 1 to which the second data is to be loaded, and in such a manner, an operation similar to the operation from the time point t 21 to the time point t 23 is executed to the latch circuits of all the data register blocks DR 1 to DR 4 , for example, 512 cycles.

When data loading to the latch circuits of all the data register blocks DR 1 to DR 4 of the flash memory FM 1 is completed, the flash memory FM 1 itself automatically starts the rewriting operation to all the memory cells selected by the sector address group SA using the data of the data register blocks DR 1 to DR 4 . The busy signal BUSY 1 is switched to the power-supply potential Vdd and the node N 4 of the busy signal control circuit BC 1 is switched to the ground potential Vss. The busy signal BUSY is switched to the power-supply potential vdd (time point t 24 ).

Next, the bank address group BA is switched to the power-supply potential Vdd to select the flash memory FM 2 , the node N 1 is switched to the ground potential Vss, the sector address group SA is switched to the address of a sector (word line) in which rewriting is to be executed, and the Y address group YA is switched to the address of the latch circuit of the data register blocks DR 1 to DR 4 to which data is to be loaded first (time point t 25 ).

The bank address group BA and the sector address group SA maintain this state during the loading. When the write enable signal WEB is turned to the ground potential Vss, the node N 3 is switched to the power-supply potential vdd and the write enable signal WEB 2 is switched to the ground potential Vss. At the leading edge of this write enable signal WEB 2 , the latch circuit of the target one of the data register blocks DR 1 to DR 4 in the flash memory FM 2 is selected, and the input data group DI becomes data to be loaded to the latch circuit (time point t 26 ).

Next, as the write enable signal WEB is switched to the power-supply potential Vdd, the node N 3 is switched to the ground potential Vss and the write enable signal WEB 2 is switched to the power-supply potential Vdd. At the leading edge of this write enable signal WEB 2 , the data of the input data group DI of the flash memory FM 2 is taken into the latch circuit of the target one of data register blocks DR 1 to DR 4 (time point t 27 ). Next, the Y address group YA selects the address of the latch circuit of the data register blocks DR 1 to DR 4 of the flash memory FM 2 to which the second data is to be loaded, and in such a manner, an operation similar to the operation from the time point t 25 to the time point t 27 is executed to the latch circuits of all the data register blocks DR 1 to DR 4 , for example, 512 cycles.

When data loading to the latch circuits of all the data register blocks DR 1 to DR 4 of the flash memory FM 2 is completed, the flash memory FM 2 itself automatically starts the rewriting operation to all the memory cells selected by the sector address group SA using the data of the data register blocks DR 1 to DR 4 . The busy signal BUSY 2 is switched to the power-supply potential Vdd. At this point, node N 4 has the ground potential Vss and the busy signal BUSY is held at the power-supply potential Vdd (time point t 28 ).

Next, when the rewriting operation to the flash memory FM 1 is completed, the busy signal BUSY 1 is switched to the ground potential Vss. At this point, the busy signal BUSY 1 has the ground potential Vss and the busy signal BUSY 2 has the power-supply potential Vdd. The node N 4 has the ground potential Vss and the busy signal BUSY is held at the power-supply potential Vdd (time point t 29 ).

Next, when the rewriting operation to the flash memory FM 2 is completed, the busy signal BUSY 2 is switched to the ground potential Vss. At this point, the busy signals BUSY 1 and BUSY 2 have the ground potential Vss and the node N 4 has the power-supply potential Vdd. The busy signal BUSY is switched to the ground potential Vss and the rewriting operation to the flash memories FM 1 and FM 2 is completed (time point t 30 ).

As described above, in the flash module according to the second embodiment, the function to output the bank address BA is added to the interface core block IC 1 of the interface circuit IF 2 , and the selector element S 1 and the write enable signal selector circuit WEC 1 are additionally provided in the interface circuit IF 2 , thereby enabling control of the plural flash memories having the same structure as that of the conventional flash memory. Therefore, with the flash module according to the second embodiment, redesigning of the flash memories themselves is not necessary and it is possible to increase the scale of memory capacity of the memory cell arrays of the flash module simply by making a simple design change of the interface circuit. With the flash module according to the second embodiment, since the circuit change is thus minimized, development of the flash module can be made in a short period.

Moreover, with the flash module according to the second embodiment, since the interface circuit IF 2 is equipped with the circuit BC 1 for performing OR processing of the busy signals BUSY 1 and BUSY 2 of the plural flash memories FM 1 and FM 2 is provided, during data rewriting of the memory cell of one of the flash memories, data loading to the other flash memory and data rewriting to its memory cell can be started, and the rewriting test time using an LSI tester or the like can be shortened.

Third Embodiment

FIG. 6 is a block diagram schematically showing the structure of a flash module according to a third embodiment of the present invention.

The structure of flash memories FM 1 and FM 2 is the same as the structure described in the first embodiment. External signals inputted to and outputted from the flash memories FM 1 and FM 2 are the same as those described in the first embodiment. The flash module (semiconductor memory device) according to the third embodiment includes the two flash memories (memory banks) FM 1 and FM 2 , and one interface circuit IF 3 .

The interface circuit IF 3 has an interface core block IC 2 , a write enable signal control circuit WEC 2 , a selector element S 1 , and a busy signal control circuit BC 1 .

The interface core block IC 2 has a structure in which the interface core block IC 1 of the first or second embodiment is additionally equipped with a function to output a test mode signal TEST. The interface core block IC 2 outputs a write enable signal WEB, a bank address group BA and a test mode signal TEST to the write enable signal control circuit WEC 2 . The interface core block IC 2 outputs the bank address group BA to the selector element S 1 . The interface core block IC 2 outputs a read enable signal REB, a sector address group SA, a Y address group YA and an input data group DI to the flash memories FM 1 and FM 2 . To the interface core block IC 2 , an output data group DOI is inputted from the selector element S 1 and a busy signal BUSY indicating that the flash memory is performing a rewriting operation is inputted from the busy signal control circuit BC 1 . An external input signal IFIN, which is an input signal to the flash module, is also inputted to the interface core block IC 2 . The interface core block IC 2 outputs an external output signal IFOUT, which is a flash module output signal.

The test mode signal TEST is a signal that can be switched from a ground potential Vss to a power-supply potential Vdd at the time of rewriting test of the flash memory using an LSI tester. The Structure of the selector element S 1 of FIG. 6 , the structure of the busy signal control circuit BC 1 of FIG. 6 and the like are the same as those of the second embodiment.

The write enable signal control circuit WEC 2 includes NOR elements NOR 4 to NOR 7 and inverter elements INV 5 to INV 7 . The test mode signal TEST is inputted to one input terminal of each of the NOR elements NOR 4 and NOR 6 . The bank address group BA is inputted to the other input terminal of each of the NOR elements NOR 4 and NOR 6 and to the input terminal of the inverter element INV 5 . An output of the inverter element INV 5 is inputted to the other input terminal of the NOR element NOR 4 via a node N 5 . Outputs of the NOR elements NOR 4 and NOR 6 are inputted to one-side input terminals of the NOR elements NOR 5 and NOR 7 via nodes N 6 and N 8 , respectively. The write enable signal WEB is inputted to the other input terminal of each of the NOR elements NOR 5 and NOR 7 . Outputs of the NOR elements NOR 5 and NOR 7 are inputted to the input terminals of the inverter elements INV 6 and INV 7 via nodes N 7 and N 9 , respectively. Outputs of the inverter elements INV 6 and INV 7 are inputted to the flash memories FM 1 and FM 2 as write enable signals WEB 1 and WEB 2 , respectively.

The interface circuit IF 3 is so constituted that even when one of the flash memories FM 1 and FM 2 is performing the rewriting operation and its busy signal BUSY 1 or BUSY 2 and the busy signal BUSY have the power-supply potential Vdd, the other flash memory can be accessed for the rewriting operation.

A data reading operation in the flash module according to the third embodiment is the same as the data reading operation in the flash module according to the first embodiment.

FIG. 7 is a timing chart for explaining the rewriting operation in the flash module of FIG. 6 . In this case, an operation to simultaneously rewrite the same data in the flash memories FM 1 and FM 2 will be described with reference to rewriting of a memory cell in a sector of an arbitrary address, as an example.

As shown in FIG. 7 , in the initial state, the write enable signal WEB has the power-supply voltage Vdd. The busy signals BUSY 1 and BUSY 2 have the ground potential Vss. The test mode signal TEST has the power-supply potential Vdd. The sector address group SA and the Y address group YA select arbitrary addresses. The input data group DI has arbitrary data. The nodes N 6 and N 8 have the ground potential Vss. The nodes N 7 and N 9 have the ground potential Vss. Both of the write enable signals WEB 1 and WEB 2 have the power-supply potential Vdd. The node N 4 has the power-supply potential Vdd. The busy signal BUSY has the ground potential Vss. The bank address group BA may have either the power-supply potential Vdd or the ground potential Vss. During the rewriting operation period (rewriting operation mode), the read enable signal REB and the test mode signal TEST are held at the power-supply potential Vdd.

Next, the sector address group SA is switched to the address of a sector (word line) in which rewriting is to be executed, and the Y address group YA is switched to the address of the latch circuit of the data register blocks DR 1 to DR 4 to which data is to be loaded first (time point t 31 ).

The bank address group BA and the sector address group SA maintain this state during the loading. When the write enable signal WEB is turned to the ground potential Vss, the nodes N 7 and N 9 are switched to the power-supply potential vdd and both of the write enable signals WEB 1 and WBE 2 are switched to the ground potential Vss. At the leading edge of these write enable signals WEB 1 and WEB 2 , the latch circuits of the target ones of the data register blocks DR 1 to DR 4 in the flash memories FM 1 and FM 2 are selected, and the input data group DI becomes data to be loaded to the latch circuits (time point t 32 ). The data to be loaded to the flash memories FM 1 and FM 2 are the same data.

Next, as the write enable signal WEB is switched to the power-supply potential Vdd, the nodes N 7 and N 9 are switched to the ground potential Vss and both of the write enable signals WEB 1 and WEB 2 are switched to the power-supply potential Vdd. At the leading edge of these write enable signals WEB 1 and WEB 2 , the data of the input data group DI of the flash memories FM 1 and FM 2 are taken into the latch circuits of the target ones of data register blocks DR 1 to DR 4 (time point t 33 ).

Next, the Y address group YA selects the address of the latch circuits of the data register blocks DR 1 to DR 4 of the flash memories FM 1 and FM 2 to which the second data is to be loaded, and in such a manner, an operation similar to the operation from the time point t 31 to the time point t 33 is executed to the latch circuits of all the data register blocks DR 1 to DR 4 , for example, 512 cycles.

When data loading to the latch circuits of all the data register blocks DR 1 to DR 4 of the flash memories FM 1 and FM 2 is completed, the flash memories FM 1 and FM 2 themselves automatically start the rewriting operation to all the memory cells selected by the sector address group SA using the data of the data register blocks DR 1 to DR 4 . The busy signals BUSY 1 and BUSY 2 are switched to the power-supply potential Vdd and the node N 4 of the busy signal control circuit BC 1 is switched to the ground potential Vss. The busy signal BUSY is switched to the power-supply potential Vdd (time point t 34 ).

When the rewriting operation ends, the busy signals BUSY and BUSY 2 are switched to the ground potential Vss and the node N 4 is switched to the power-supply potential Vdd. The busy signal BUSY is switched to the ground potential Vss and the rewriting operation to the flash memories FM 1 and FM 2 is completed (time point t 35 ).

In the case of executing the rewriting operation with the test mode signal TEST at the ground potential Vss, the write enable signal control circuit WEC 2 has the same logic as that of the write enable signal control circuit WEC 1 of the second embodiment and therefore the operation is the same as the operation described in the second embodiment. In this case, the operation-has effects similar to those of the second embodiment.

As described above, in the flash module according to the third embodiment, the function to output the bank address BA is added to the interface core block IC 2 of the interface circuit IF 3 , and the selector element S 1 and the write enable signal selector circuit WEC 2 are additionally provided in the interface circuit IF 3 , thereby enabling control of the plural flash memories having the same structure as that of the conventional flash memory. Therefore, with the flash module according to the third embodiment, redesigning of the flash memories themselves is not necessary and it is possible to increase the scale of memory capacity of the memory cell arrays of the flash module simply by making a simple design change of the interface circuit. With the flash module according to the third embodiment, since the circuit change is thus minimized, development of the flash module can be made in a short period.

Moreover, in the third embodiment, by providing the circuit WEC 2 for activating all the write enable signals WEB 1 and WEB 2 by switching the test mode signal TEST, which can be switched from the ground potential Vss to the power-supply potential Vdd at the time of rewriting test using an LSI tester, to the power-supply potential Vdd, it is possible to simultaneously write the same data to all of the provided plural flash memories at the time of rewriting test using an LSI tester, and the rewriting test time can be shortened.

In the case of executing rewriting with the test mode signal TEST at the ground potential Vss, the rewriting operation of different data to the plural flash memories is executed, and during data rewriting of the memory cell of one of the flash memories, data loading to the other flash memory and data rewriting to its memory cell can be started. The rewriting test time using an LSI tester or the like can be shortened.

In the first to third embodiments, the method for constructing the flash memory and the interface circuit in the flash-hybrid LSI is described. However, the present invention is not limited to this and can be applied to the structure of a memory such as DRAM or SRAM and its interface circuit.

Moreover, in the first to third embodiments, the method for constructing the two flash memories and the interface circuit is described. However, the present invention can also be applied to a method for constructing plural flash memories other than two and an interface circuit.