Comparison apparatus operated at a low voltage

The present invention relates to a comparison apparatus; and, more particularly, to the same operated at a high speed and at a low voltage by using an analog signal.

Recently, complementary metal oxide semiconductor (CMOS) process techniques are common. Accordingly, a system on chip (SOC) technique integrating a number of circuits on one chip became important to a modern industry. The SOC is integrated with an analog circuit processing an analog signal as well as a large scale digital circuit capable of performing a complicated logic operation. A process technique for large scale integration less than 0.18 μm can be used for a transistor device operated at a low voltage less than 1.8 Voltage (V). A conventional circuit design may be applied to the digital circuit. However, in this case, it is not possible to apply it to an analog circuit because an operation range of the transistor is substantially limited at such low voltage. Accordingly, a new circuit design should be required.

An analog to digital converter (ADC) among a number of analog circuits integrated at the SOC is a most important block capable of controlling whole SOC.

Concisely describing a conversion principal of the ADC, an analog input signal is first compared with a finely subdivided standard voltage and converted to a digital value. Consequently, the ADC is used to convert an analog type of input signal to a digital type of output signal.

The ADC is used for a peripheral device of a communication circuit, a digital signal processor (DSP), and a micro-controller unit (MCU). In addition, the ADC is broadly used for all kinds of circuit chips requiring an interface of the analog signal and the digital signal.

Usually, the ADC uses a 2-phase clocked comparator operated by a clock signal and such comparator could have two operation types classified by the clock signal, that is, a track mode and a latch mode. In a first mode, that is, the track mode, two input analog signals are tracked by being amplified to have a low gain. In a second phase, that is, the latch mode, the amplified signal is applied to a positive feedback circuit. Continuously, a polarity of the signal is latched and thereafter, outputting one bit digital signal.

FIG. 1 is a block diagram showing a constitution of a CMOS comparator used for a conventional ADC. Herein, the CMOS comparator is constituted with an amplification unit 10 and a latch circuit 11 . Herein, the amplification unit amplifies a difference of a standard signal and an input signal, and the latch circuit latches the difference. An amplifier used for the CMOS comparator mentioned above does not need to be a linear or a closed loop, and obtains a virtually infinite gain by forming a positive feedback of the latch circuit.

FIG. 2 is a circuit diagram specifically illustrating the comparator shown in FIG. 1 (Ref. “Principles of data conversion system design—Behzad Razavi (AT&T Bell Laboratories)” IEEE PRESS 189p.)

As shown, the comparator device is constituted with a differential pair input unit 10 constituted with a first PMOS transistor MP 1 and a second PMOS transistor MP 2 , a first latching unit 11 constituted with a fifth PMOS transistor MP 5 and a sixth transistor MP 6 . Herein, both gates of the fifth and the sixth PMOS transistors are cross-coupled to two output terminals Vout 1 and Vout 2 respectively, a second latching unit 12 constituted with a fourth NMOS transistor and a fifth NMOS transistor, wherein both gates of the fourth and the fifth NMOS transistors MN 4 and MN 5 are cross-coupled to a first node and a second node respectively, an inverter, a third NMOS transistor MN 3 controlling the clock signal which can operate the second latching unit 12 in the track mode or the latch mode, Herein, the third NMOS transistor MN 3 is formed between the first node N 1 and the second node N 2 corresponding to both drains of the fourth and the fifth NMOS transistor MN 4 and MN 5 . A clock signal Clk inverted by the inverter INV is applied to the followings: a gate of the third NMOS transistor MN 3 and making the second latching unit 12 serve as the amplifier having a constant turn-on resistance during a track mode operation; a coupled fourth PMOS transistor MP 4 and a first NMOS transistor MP 4 ; and another coupled seventh PMOS transistor MP 7 and second NMOS transistor MN 2 which get alternately turned on and off by the clock signal Clk, a third PMOS transistor MP 3 being turned on during a latch mode operation and serving as a source follower turning off the differential pair input unit 10 by forming a current pass from a drain voltage terminal VDD to a ground terminal GND, and a bias transistor MP 8 .

FIG. 3 illustrates an equivalent circuit of the track mode shown in FIGS. 3 and FIG. 4 is a timing chart illustrating an entire operation of the circuit shown in FIG. 2 . The operation of the comparator is observed by referring to FIGS. 2 , 3 and 4 .

Herein, if the clock signal Clk is in a logic low state or a logic high state, the comparator is operated in the track mode or the latch mode, respectively.

First, in case that the clock signal Clk is in the logic low state, the MN 1 and the MN 2 are turned off, and the MP 3 is also turned off. In a meantime, the MP 4 and MP 7 are turn on. Consequently, the Vout 1 and Vout 2 get identical to a voltage level at the VDD.

Accordingly, the latch operation is about to be performed by Vx and Vy respectively applied to the second node N 2 and the first node N 1 by two input signals Vin 1 and Vin 2 . At this time, the MN 3 is turned on and its turn-on resistance value becomes high. Consequently, the Vx and Vy approach to each other temporarily. Thereafter, the MN 3 is operated in the track mode in which the Vx and Vy are amplified.

In the track mode, the comparator shown in FIG. 2 is commonly operated as a differential amplifier, and the analog signals Vin 1 and Vin 2 are amplified and tracked. At this time, a gain A of the analog signal Vin 1 or Vin 2 is obtained by below equation Eq. 1.

[First Mathematic Formula]

A=Gm 1 × Ron 3 /(2 −Gm 4 × Ron 3 )  Eq. 1.

Herein, ‘Gm 1 ’ means a trans-conductance value for the MP 1 and the ‘Gm 4 ’ means the trans-conductance value for the MN 4 . In addition, the Ron 3 means an impedance of the MN 3 .

Commonly, the differential amplifier is designed to have a result value 1 for ‘Gm 1 ×Ron 3 ’, that is, ‘Gm 1 ×Ron 3 =1’. However, if the result value of the ‘Gm 4 ×Ron 3 ’ becomes over 2, a denominator value of the first mathematic formula becomes negative. That means the circuit for the differential amplifier does not work as a normal amplifier. In this case, a positive feedback is commonly applied to the circuit and thereby, operating the circuit only in the latch mode. In short, voltage values of Vx and Vy are biased to be contrary to each other and the circuit does not get to response to the Vin 1 and Vin 2 .

Accordingly, the circuit for the differential amplifier should be designed not to have the result value of ‘Gm 4 ×Ron 3 ’ over 2.

As shown in FIG. 4 , each of Vx and Vy is amplified in the track mode. In addition, if the clock signal Clk is converted from the logic low state to the logic high state, all of the MP 1 , MP 2 , MN 3 , MP 4 and MP 7 are turned off and the MN 3 is removed from the circuit as it is turned off.

As the MP 3 is turned on, the current pass is formed from the VDD to the GND via the MP 8 and MP 3 . At this time, PMOS transistors MP 1 , MP 2 of the differential pair input terminal are turned off by the MP 3 serving as the source follower.

Differential current from PMOS transistors MP 1 , MP 2 of the differential pair input unit is generated by a voltage difference of the voltages Vx and Vy applied to the nodes N 1 and N 2 .

As mentioned above, the differential voltage is amplified by a positive amplifier and the Vx and the Vy are diverged in a direction predetermined by an input voltage for a standard voltage.

The Vx and Vy are much more amplified and thereby, generating out-put voltages, that is, Vout(+) and Vout(−) in such wave forms shown in FIG. 4 .

In addition, if the circuit shown in FIG. 3 is operated in a low voltage, a value of voltage Vgs 3 applied between a gate and a source is reduced and thereby, increasing a value of Ron 3 . If Gm 3 is decreased to reduce the value of ‘Gm 4 ×Ron 3 ’, the Vx and Vy are increased. Consequently, the Vgs 3 of the MN 3 is reduced and thereby, increasing the Ron 3 . Therefore, it is not easy to make the result value of ‘Gm 3 ×Ron 5 ’ become 1. Even though the Ron 3 is reduced by increasing a width of the M 5 , the MN 3 is in a turn-on condition slightly exceeding a threshold voltage. Accordingly, the MN 3 gets close to a turn-off condition and a resistance value is rapidly increased in case that the threshold voltage of the MN 3 is varied by a process change. Consequently, a possibility that ‘Gm 4 ×Ron 3 ’ is over 2 becomes high.

Furthermore, if a power voltage is varied, the value of the Ron 4 is greatly varied because the MN 3 is weakly turned on at a low power voltage. Accordingly, a stable operation of the circuit in accordance with the prior art can not be guaranteed.

It is, therefore, an object of the present invention to provide a comparator operated stably even at a low power voltage and preventing its property change caused by a process change.

In accordance with an aspect of the present invention, there is provided the comparator outputting one bit digital signal after comparing two analog input signals by alternately performing a track mode operation and a latch mode operation, wherein the operation of the track mode or the latch mode is decided by a clock signal having a constant period, including: a latching unit having the main/sub input terminal; a first switching transistor having the clock signal as a gate input and having one end coupled to main input terminal; a first load transistor diode-connected to the other end of the first switching transistor and a ground end; a second switching transistor having a gate receiving the clock signal as a gate input and one end coupled to the sub input terminal; and a second load transistor diode-connected to the second switching transistor and to the other end of the ground terminal.

Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram showing a constitution of a CMOS comparator used for a common ADC;

FIG. 2 is a circuit diagram of the CMOS comparator shown in FIG. 1 more precisely;

FIG. 3 is an equivalent circuit diagram of the comparator operated in a track mode as shown in FIG. 2 ;

FIG. 4 is a timing chart illustrating an entire operation of the comparator shown in FIG. 2 ;

FIG. 5 is a detailed circuit diagram depicting a CMOS comparator used for an ADC, wherein the CMOS comparator is designed in accordance with an embodiment of the present invention;

FIG. 6 is an equivalent circuit diagram of the CMOS comparator operated in a track mode as shown in FIG. 5 ;

FIG. 7 is an equivalent circuit diagram of the CMOS comparator operated in a latch mode as shown in FIG. 5 ; and

FIG. 8 is a timing chart illustrating an entire operation of the CMOS comparator shown in FIG. 5 .

Hereinafter, an inventive CMOS comparator outputting one bit digital signal after comparing two analog input signals by alternately performing a track mode operation and a latch mode operation will be described in detail referring to the accompanying drawings.

The present invention relates to the CMOS comparator using a low power voltage, for example, 1.8 V. Two groups of transistors are distinctly disposed to have a switch function and a resistor function, respectively. A stable gain without being affected by a voltage or current change or a process can be obtained by forming a ground terminal by using a current pass between two nodes.

FIG. 5 is a detailed circuit diagram of the CMOS comparator used for an analog to digital converter (ADC), wherein the CMOS comparator is designed in accordance with an preferred embodiment of the present invention.

Referring to FIG. 5 , the CMOS comparator includes a differential input unit 50 , a tracking/latching units 51 a second latching unit 52 and a switching unit. The differential input unit 50 is constituted with two PMOS transistors M 1 and M 2 , wherein a first input signal Vin 1 and a second input signal Vin 2 are generated by the M 1 and M 2 , respectively, and treated as a discrete input.

The tacking/latching units 51 receives the differential output at a main sub input terminals N 1 and N 2 from the differential input unit 50 and thereby, performing a tacking and latch operation. For this, tracking/latching units 51 are used. The differential input unit 50 in the track mode is operated as a load of the differential input unit 50 for the tacking operation and thereby, performing an operation of a differential amplifier.

The tacking/latching unit 51 includes a first latch unit 510 having a first node N 1 as the main input terminal and a second node N 2 as the sub input terminal, a first switching transistor M 7 receiving a revered clock signal Clk by an inverter INV and having one end connected to the first node N 1 , a first load transistor M 5 diode coupled to the other end of the first switching transistor M 7 and coupled to the ground, a second switching transistor M 8 receiving the reversed clock signal Clk by the inverter INV as a gate input and having one end coupled to the second node N 2 , and a second load transistor M 6 diode coupled to the other end of the second switching transistor M 8 and coupled to the ground.

The first latching unit 510 further includes a NMOS transistor M 4 having a gate coupled to the first node N 1 and a gate of a MMOS transistor M 3 coupled to the second node N 2 .

Herein, a first current pass X between the first node N 1 and the ground terminal GND is formed by the first switching transistor M 7 and the first load transistor M 5 , and a second current pass Y between the second node N 2 and the ground terminal GND is formed by the second switching transistor M 8 and the second load transistor M 6 . Consequently, the tracking operation is performed.

An explanation for the tracking operation will be described later.

In addition, the first load transistor M 5 and the second load transistor M 6 need to be large enough to neglect turn-on resistances of the first switching transistor M 7 and the second switching transistor M 8 , respectively. At this time, size of the first load transistor M 5 should be identical to that of the second load transistor M 6 and also, size of the first switching transistor M 7 should be identical to that of the second transistor M 8 .

In addition, a second latching unit 52 resets a prior voltage level of output terminals Vout 1 and Vout 2 to the voltage level of a drain voltage terminal VDD in the track mode and generates output of the tracking/latching units 51 through output terminals Vout 1 and Vout 2 by latching the output of the tracking/latching units 51 in the latch mode.

The second latching unit 52 responding to the clock signal Clk includes a main output terminal Vout 1 , sub output terminal Vout 2 and two PMOS 12 and 13 . The main output terminal and the sub output terminal are cross coupled to gates of two PMOS transistors.

A switching unit 53 is formed in between the second latching unit 52 and the tracking/latching unit 51 for connecting or disconnecting the second latching unit 52 and the tracking/latching unit 51 in response to the clock signal Clk.

In addition, a fifth and sixth switching transistor are operated as a switch in order to reset output terminals Vout 1 and Vout 2 by using the second latch unit 52 when the latch mode is transformed to the track mode according to the clock signal Clk by receiving the clock signal Clk into gates of transistor M 14 and M 15 , and forming the source-drain path between the power voltage terminal VDD and the output terminals Vout 1 and Vout 2 .

In addition, a PMOS transistor M 9 is formed to serve as a source-follower which forms a current pass between the drain voltage terminal VDD and the ground terminal GND via a bias transistor M 16 . Herein, the PMOS transistor is turned on in the latch mode and performs the above mentioned operation. Furthermore, the differential input unit 50 is turned off in the latch mode thereby.

FIG. 6 illustrates an equivalent circuit of the detailed circuit of the CMOS comparator shown in FIG. 5 . FIG. 7 illustrates the equivalent circuit in the latch mode. FIG. 8 is a timing chart showing whole operation of the CMOS comparator shown in FIG. 5 .

Hereafter, the operation of the comparator in accordance will be described referring to FIG. 5 or FIG. 8 , and the abbreviation of each transistor is used for description simplicity.

Herein, it is supposed that the comparator is operated in the track mode when the clock signal Clk is in a logic low state and the comparator is operated in the latch mode when the clock signal Clk is in a logic high state.

First, if the clock signal Clk becomes the logic low state, M 1 and M 2 are turned off and M 9 is also turned off. The other hand, M 14 and M 15 are turned on. As a result, Vout 1 and Vout 2 become identical to a voltage level of the drain voltage terminal VDD.

Accordingly, a voltage Vy applied to the second node N 2 and another voltage Vx applied to the first node N 1 are latched by the input signals Vin 1 and Vin 2 , respectively. At this time, M 7 and M 8 are turned on. Herein, a current pass to the ground terminal GND is formed by transistors M 5 and M 6 respectively diode-connected with the M 7 and M 8 .

Consequently, it is operated as the track mode and Vx and Vy are located and amplified.

In such track mode, the comparator illustrated in FIG. 5 is operated as a common differential amplifier, and amplifies and tracks analog input signals of Vin 1 and Vin 2 . At this time, a direct current DC gain A of the amplifier is calculated by belowe equation Eq. 2.

A=Gm 1 /( Gm 5 − Gm 3 )  Eq. 2

Herein, Gm 1 , Gm 5 and Gm 3 are trans-conductance of M 1 , M 5 , and M 3 , respectively.

Referring to the FIG. 6 and the above expressed the mathematic formula 2, the turn-on resistance Ron 7 of M 7 is neglected because the Ron 7 is series-connected with 1/Gm 5 and much lower than 1/Gm 5 . In addition, output impedance values of M 5 and M 3 , that is, Ron 5 and Ron 3 are also neglected because the Ron 5 and Ron 3 are much higher than 1/Gm 5 even though parallel-connected to 1/Gm 5 .

According to the Eq 2, the circuit of the comparator in accordance with the present invention should be devised to keep a positive value of the denominator ‘Gm 5 −Gm 3 ’. Generally, the positive value is maintained by increasing the value of Gm 5 . Accordingly, the gain value becomes stable. In addition, Vx and Vy are lowered if the value of Gm 5 is increased. Consequently, the turn-on resistance of M 7 is decreased. Herein, Gm 5 and Gm 3 are kept to have a constant value regardless of changes of a power voltage and a threshold voltage. However, only one factor, that is, a bias current merely affects the values of Gm 5 and Gm 3 .

In case that the value of Gm 3 is a little lower than that of Gm 5 , it is possible to increase the gain of the amplifier much more and thereby, improving a resolution of the comparator.

Gm 3 and Gm 5 can be constantly maintained constant by adjusting a transistor rate (W/L) regardless of the change of manufacturing process steps and a power voltage and thereby, guaranteeing a stable operation of the comparator.

As shown in FIG. 8 , each of Vx and Vy is amplified in the track mode, and all of M 1 , M 2 , M 7 , M 8 , M 14 , and M 15 are turned off when the clock signal Clk in the logic low state is converted to that in the logic high state.

Accordingly, M 7 and M 8 are removed from a real circuit.

A current pass is formed from the VDD to M 9 via M 16 as M 9 is turned on, and M 1 and M 2 are turned off.

A differential current from the PMOS transistors M 1 and M 2 of the differential input unit 50 is generated by a difference between Vx and Vy. Herein, Vx is the voltage of N 1 and Vy is the voltage of N 2 . Such differential current is amplified by a positive amplifier. Furthermore, Vx and Vy are diverged in predetermined directions by an input voltage for a standard voltage. Vx and Vy are much more amplified. Consequently, Output voltages Vout 1 (+) and Vout 2 (−) are generated in a wave shape shown in FIG. 8 .

More specifically, M 1 and M 2 serve as a pre-amplifier amplifying the input signal after receiving the input signal when the comparator is in the track mode. At this time, M 3 , M 4 , M 5 and M 6 receive the input signal. The gain of the amplified signal is ‘Vx−Vy’.

In the track mode, M 10 and M 11 are turned off, and Vx and Vy are not affected by M 12 , M 13 , M 14 and M 15 . M 14 and M 15 are turned on. As a result, Vout 1 and Vout 2 become identical to the drain voltage terminal VDD and consequently, a memory effect deciding voltage polarity when a prior latch state is converted to a next latch mode is eliminated. In short, output latch state becomes reset.

When the comparator is operated in the latch mode, M 10 and M 11 are turned on and M 14 and M 15 are turned off. In addition, M 7 and M 8 are turned off as shown in FIG. 7 and operated as a typical latch circuit. At this time, a gate voltage of M 9 is reduced to the voltage level of the ground terminal GND. Consequently, electrical current does not flow to M 1 and M 2 , and Vin 1 and Vin 3 do not affect the first and second latch units 510 52 anymore. Furthermore, the node having a relatively high voltage obtains the voltage level identical to the drain voltage terminal VDD through a positive feedback of the first and the second latch units 510 and 52 . At this time, an initial state of a moment of starting the latch mode by Vx and Vy is kept. Contrarily, the node having a relatively low voltage obtains the voltage level of the ground terminal GND and digital signals are generated. FIG. 8 illustrates real output waveforms of such Vout 1 and Vout 2 .

As mentioned above, the present invention can prevent variation of characteristic according to change of power voltage or variation of process by designing a comparator having stable gain of amplifier not to be affected by threshold voltage and power voltage of transistor in tracking mode.

Also, the present invention can be implemented not only device comparing two analog signals.

Furthermore, by designing a gain of comparator not to be affected by process variation and power voltage change in order to have independent characteristic, the present invention can increased efficiency of manufacturing comparators.

Although the preferred embodiment of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.