Line frequency switching regulator

This application claims the benefit, under 35 U.S.C. § 365 of International Application PCT/US03/10013, filed Apr. 2, 2003, which was published in accordance with PCT Article 21(2) on Oct. 16, 2003 in English and which claims the benefit of provisional application Ser. No. 60/370,072, filed Apr. 4, 2002.

The invention relates to a switch mode power supply for a communication device.

Typically, a switch mode power supply (SMPS), includes a switching power transistor having a controllable duty cycle that is controlled by a duty cycle modulated signal. An alternating current (AC) mains supply voltage source is coupled to a rectifier for producing an input supply voltage for energizing the SMPS. Typically, a large input filter capacitor is coupled at an input of the SMPS for filtering AC components from a rectified input supply voltage produced in the rectifier. It may be desirable to eliminate the large input filter capacitor.

A typical SMPS requires the generation of a periodic switching signal to establish the timings of the duty cycle modulated signal. It may be desirable to utilize the periodic waveform of the mains supply voltage to establish the timings of the duty cycle modulated signal. Thereby, SMPS operation can be obtained without an added circuit complexity associated with the generation of the periodic switching signal.

In a SMPS, embodying an inventive feature, a mains supply voltage source is coupled to a rectifier for producing an input supply voltage. The rectified input supply voltage is coupled unfiltered to an input of the SMPS. A switching power transistor having a controllable duty cycle is controlled by a duty cycle modulated signal for producing a regulated output supply voltage from the rectified input supply voltage. The periodic waveform of the mains supply voltage is used to establish the timings of the duty cycle modulated signal.

In carrying out an inventive feature, in each cycle, current flow is initiated in the transistor, when the transistor is already fully turned on and a voltage developed between its main current conducting terminals is low or close to zero volts. Thereby, power dissipation is, advantageously, small. When the output supply voltage attains a threshold level the transistor is turned off.

In carrying out another inventive feature, hysteresis is provided for preventing the transistor from turning on again in the same cycle, after it has been turned off. Thereby, advantageously, the transistor is prevented from turning on again in the same cycle, when the voltage developed between its main current conducting terminals is no longer close to zero volts. Consequently, increased power dissipation is, advantageously, prevented.

A switch mode power supply, embodying an inventive feature includes a source of a periodic input supply voltage and a filter capacitor. A power, switching semiconductor is coupled to the source and to the capacitor for generating periodic rectified supply current pulse in the semiconductor having a first transition in a first direction and a second transition at an opposite direction at a frequency related to that of the input supply voltage to develop an output supply voltage in the capacitor. A source of a first switch control signal is provided for conditioning the semiconductor to conduction prior to the first transition in a manner to provide for zero voltage switching in the semiconductor, during the first transition. A comparator is responsive to a signal indicative of the output supply voltage and to a signal at a reference level for generating a second switch control signal for the semiconductor to produce the second transition of the current pulse that is modulated, in accordance with a difference between the output supply voltage and the reference level signal. The comparator has a positive feedback signal path that provides hysteresis with respect to the output supply voltage.

FIG. 1 illustrates an unfiltered full-wave rectified sinewave waveform produced from a mains supply voltage at a line frequency that is useful for explaining the operation of the circuit of FIG. 2 ;

FIG. 2 illustrates a switch mode power supply, embodying an inventive feature; and

FIGS. 3 a , 3 b and 3 c illustrate waveforms useful for explaining the operation of the power supply of FIG. 2 .

FIG. 2 illustrates a switch mode power supply that includes a switch mode regulator 100 , embodying an inventive feature. A mains supply voltage VM is applied via a line transformer T 1 to a bridge rectifier 101 . A voltage Vin, developed at a terminal 102 a or 102 b of rectifier 101 , is coupled to an emitter of a regulator, series pass switching transistor Q 1 via terminal 102 a or 102 b . Transistor Q 1 is coupled in series with a rectifier or diode D 2 to form a switching semiconductor. A collector of transistor Q 1 is coupled via diode D 2 to a filter capacitor C 1 for producing a regulated, output supply voltage Vout in capacitor C 1 .

Voltage Vout is coupled via a voltage divider that includes a resistor R 7 and a resistor R 6 , having, for example, equal values, to an inverting input terminal of a comparator or an operation amplifier U 1 , pin 2 , of the type LM324. A reference voltage Vref is coupled via an adjustable voltage divider resistor R 10 and a resistor R 5 to a non-inverting input terminal, pin 3 , of amplifier U 1 to establish a reference voltage Vref 1 at the non-inverting input terminal of amplifier U 1 , pin 3 . An output terminal of amplifier U 1 , pin 1 , is coupled via a voltage divider formed by a resistor R 2 and a resistor R 3 to the base of a switching transistor Q 2 . A collector of transistor Q 2 is coupled via a current limiting resistor R 1 to the base of transistor Q 1 .

FIGS. 1 and 3 a – 3 c illustrate waveforms useful for explaining the operation of switching regulator 100 of FIG. 2 . Similar symbols and numerals in FIGS. 1 , 2 and 3 a – 3 c indicate similar items or functions.

Assume that terminal 102 a of bridge rectifier 101 of FIG. 2 is separated from an emitter terminal 102 b of transistor Q 1 , as shown by the broken lines in the form of the letter “x”. Assume also that a resistive load, not shown, is applied to terminal 102 a . In that case, the waveform of input supply voltage Vin at terminal 102 a of FIG. 2 would be an unfiltered full-wave rectified sinewave waveform, of mains supply voltage VM having a line frequency of, for example, 60 Hz, as shown in FIG. 1 . In the following description, assume that terminals 102 a and 102 b are connected to each other, as shown in FIG. 2 , and are at the same potential.

During each period 9 of voltage Vin of FIG. 3 b , and as long as voltage Vout of FIG. 3 a is lower than two times the voltage at the non-inverting input terminal, pin 3 , of amplifier U 1 of FIG. 2 , an output voltage of amplifier U 1 , at output pin 1 , is at a HIGH level, that is substantially equal to a 20 volt supply voltage, not shown, of amplifier U 1 . As a result, transistor Q 2 is turned on causing transistor Q 1 to turn on in a saturated condition. Thus, advantageously, transistor Q 1 is conditioned for conduction before a current Ieq 1 of FIG. 3 c flows in transistor Q 1 .

When voltage Vin becomes sufficiently large to forward bias diode D 2 , as indicated by a portion of voltage Vin that is above a broken line in FIG. 1 , a collector-emitter voltage, not shown, of transistor Q 1 of FIG. 2 changes polarity. Consequently, rectified supply current Ieq 1 of FIG. 3 c begins flowing through a current path that includes an emitter-collector current path of transistor Q 1 of FIG. 2 , diode D 2 and filter capacitor C 1 to charge capacitor C 1 and produces voltage Vout. Voltage Vout varies together with an instantaneous value of voltage Vin, during an interval t 1 of FIG. 3 b . FIG. 3 c illustrates a waveform of emitter current Ieq 1 in transistor Q 1 of FIG. 2 , during interval t 1 , when voltage Vout of FIG. 2 is coupled to a load, not shown, of for example, 11 ohm.

In carrying out an inventive feature, output voltage Vout of FIG. 3 a is regulated in a power efficient manner by initiating the flow of current Ieq 1 of FIG. 3 c in transistor Q 1 of FIG. 2 , when voltage Vin of FIG. 3 b is approximately equal to voltage Vout of FIG. 3 a or a magnitude of the collector-emitter voltage, not shown, of transistor Q 1 of FIG. 2 is small. Current Ieq 1 of FIG. 3 c begins flowing in transistor Q 1 of FIG. 2 after transistor Q 1 is already conditioned for conduction. Therefore, advantageously, zero voltage switching is provided when transistor Q 1 is turned on. The result is that less power is dissipated in transistor Q 1 than if a significant voltage difference were developed between its emitter and collector of transistor Q 1 of FIG. 2 , prior to the initiation of emitter current Ieq 1 of FIG. 3 c.

When voltage Vout of FIG. 3 a reaches a threshold level that is equal to two times the voltage at the non-inverting input terminal, pin 2 , of amplifier U 1 of FIG. 2 , amplifier U 1 output at pin 1 attains a LOW level, causing transistors Q 2 and Q 1 to turn off. Voltage Vout does not increase significantly above two times the voltage at the non-inverting input terminal, pin 3 , of amplifier U 1 . Therefore, during a transition interval, not shown, when transistor Q 1 is turned off, the power dissipation in transistor Q 1 is also, advantageously, small. The process of replenishing the charge on capacitor C 1 that was removed by the load circuit, not shown, is repeated in each period T of voltage Vin of FIG. 3 b.

A positive feedback resistor R 4 of FIG. 2 , embodying an inventive feature, is coupled from output terminal of amplifier U 1 , pin 1 , to the non-inverting input terminal of amplifier U 1 , pin 3 , to provide hysteresis. Positive feedback resistor R 4 causes the voltage difference between that at the inverting input terminal, pin 2 , and at the non-inverting input terminal, pin 3 , of amplifier U 1 to increase further.

Thereby, the hysteresis prevents amplifier U 1 from turning on transistor Q 1 again to avoid multiple occurrences of pulses of current Ieq 1 of FIG. 3 c , during a down-ramping portion Vindr of voltage Vin. Without the hysteresis, amplifier U 1 of FIG. 2 might have been capable of turning on transistor Q 1 to produce a second pulse of current Ieq 1 in transistor Q 1 and diode D 2 , during the same period T of FIG. 3 b , when the voltage difference between the emitter and collector of transistor Q 1 of FIG. 2 is significant and greater than zero. Thereby, the hysteresis prevents power dissipation increase in transistor Q 1 by preserving the zero voltage switching.

A pull-down diode D 3 , embodying an inventive feature, is coupled between the emitter of transistor Q 1 and the inverting input terminal, pin 2 , of amplifier U 1 . Pull-down diode D 3 couples voltage Vin to inverting input terminal, pin 2 , of amplifier U 1 . Decreasing voltage Vin, during a down-ramping portion Vindr of voltage Vin of FIG. 3 b , causes the voltage at output terminal of amplifier U 1 , pin 1 , to attain the HIGH level again. Consequently, advantageously, transistor Q 1 is conditioned for conduction in preparation to the next cycle.

Diode D 2 is back biased immediately after transistor Q 1 is conditioned for conduction. Therefore, current flow in conductive transistor Q 1 that, otherwise, could have discharged capacitor C 1 is prevented until the next conduction interval t 1 a of FIG. 3 c . Only when voltage Vin of FIG. 3 b again reaches a level that is approximately equal to voltage Vout of FIG. 3 a , diode D 2 begins conducting current Ieq of FIG. 3 c again, as explained before.

The level of voltage Vout is, advantageously, maintained substantially the same in each period T of FIG. 3 b regardless of variations in the amplitude of input voltage Vin. A variation in output load current may change a peak-to-peak ripple voltage VRIPPLE in FIG. 3 a . However, the average value of DC output voltage Vout is maintained. Ripple voltage VRIPPLE can be controlled by appropriate selection of the value of capacitor C 1 with respect to the load, as is well known. Thus, regulation is achieved for input voltage variations and for load variations.

A diode D 1 of FIG. 2 , a capacitor C 2 , and a resistor R 8 form a transient suppresser. When transistor Q 1 turns off, the leakage inductance in transformer T 1 tends to keep the current flowing which produces a high voltage spike, not shown, which could damage transistor Q 1 and/or produce noise in the regulated output. Diode D 1 and capacitor C 2 conduct this spike and resistor R 8 provides a leakage path for the voltage generated. A junction terminal 106 of resistor R 8 , capacitor C 2 and the cathode of diode D 1 could also be used for providing an auxiliary supply voltage, such as needed to supply amplifier U 1 or other circuits. In the arrangement of FIG. 2 it is used to derive reference voltage Vref.