Error correcting device and method thereof that turbo-decodes only if an error is detected in the received data

1. Field of the Invention

The present invention relates, in general, to an error correcting device and a method thereof and, more particularly, to a turbo decoding device and a method thereof.

This is a counterpart of and claims priority to Japanese patent application Ser. No. 172707/2002, filed on Jun. 13, 2002, the subject matter of which is incorporated herein by reference.

2. Description of the Related Art

In a wireless communication system, a transmitter side adds a cyclic redundancy check (CRC) to an information data to be sent, causing a block code data to be generated (CRC coding). The block code data is coded with a turbo code to generate a turbo code data (turbo coding). Then, an order of the turbo code data is arranged for dispersing an error (interleave), and the arranged turbo code data is transmitted.

On the other hand, a conventional receiver side rearranges the order of the transmitted arranged turbo code data (hereinafter “received data”) to have the previous order (deinterleave). The rearranged received data is decoded to generate the block code data (turbo decoding). Then, the conventional receiver side detects an error in the decoded block code data with CRC.

However, in the conventional receiver side the rearranged received data is always turbo-decoded. Although an ability of error correcting of turbo decoding is high, it necessitates lots of calculation. As a result, much more time and electric power is required.

According to one aspect of the present invention, there is provided a method for extracting an information sequence from transmitted data, which includes receiving the transmitted data, rearranging the order of the received data, extracting a block coding sequence from the rearranged received data, detecting whether an error exists in the extracted block coding sequence, and decoding the extracted block coding sequence using block decoding to obtain the information sequence if no error is detected in the extracted block coding sequence.

The novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.

FIG. 1 is a block diagram showing data constructions used in the present invention.

FIG. 2 is a block diagram showing a turbo coder used in the present invention.

FIG. 3 is a block diagram showing an apparatus of the present invention.

FIG. 4 is a flow chart showing an operation of the apparatus of the present invention.

The preferred embodiments of the present invention will be described. However, the invention is not limited to the specific embodiments. Moreover, not all the combinations of the characteristics of the present invention described in the embodiments are essential to the present invention.

The data constructions used in the present invention will be described with reference to FIGS. 1-2 . FIG. 1 is a block diagram showing data constructions used in the present invention. FIG. 2 is a block diagram showing a turbo coder used in the present invention. The turbo coder is described in “Turbo Coding”, Haruo Hagihara et al., Electro Information Communication, vol. 84 No.3, FIG. 3 .

As shown in FIG. 1 , an information sequence Xk (k: integer) comprises four bits (X 1 , X 2 , X 3 , X 4 ) as an example. The information sequence is coded with a block code to generate the block coding sequence Bn (n: integer) which comprises seven bits (X 1 , X 2 , X 3 , X 4 , α 1 , α 2 , α 3 ) as an example. The first four bits are the information sequence Xk, and the last three bits are redundancy bits Pj (J: integer). The block code to generate this block coding sequence Bn is called a systematic code.

As shown in FIG. 2 , the turbo coder comprises an interleaver 200 , element coders 210 and 220 , a switch 230 and a parallel/serial converter 240 . The block coding sequence Bn is coded by the element coder 210 , and a coded data Y 1 n (n: integer) is generated. On the other hand, an order of the block coding sequence Bn is arranged by the interleaver 200 . The arranged block coding sequence Bn is coded by the element coder 220 , and a coded data Y 2 m (m: integer) is generated. The parallel/serial converter 240 outputs the block coding sequence Bn, the coded data Y 1 n and the coded data Y 2 m in serial (time division multiple). As shown in FIG. 1 , the turbo coding sequence Zp (p: integer) is 21 bits (X 1 ,Y 11 ,Y 21 , X 2 ,Y 12 ,Y 22 , X 3 , . . . , α 3 ,Y 17 ,Y 27 ). As mentioned above, both the block code and the turbo code are the systematic codes.

First, the apparatus for extracting an information sequence from transmitted data in a wireless communication system of the present invention will be described with reference to FIG. 3 .

The apparatus comprises a deinterleaver 300 and a decoding circuit 310 . The apparatus receives a transmitted data. As mentioned above, the transmitted data is the turbo coding sequence Zp an order of which is arranged. The turbo coding sequence Zp is generated by coding the block coding sequence Bn with the turbo code as noted above. Also, the block coding sequence Bn is generated by coding the information sequence Xk with the block code.

The deinterleaver 300 arranges the order of the received data to be in the previous order as it was at the transmitter side, and generates an arranged received data 300 a.

The decoding circuit 310 is coupled with the deinterleaver 300 . The decoding circuit 310 comprises a storing circuit 311 , an information sequence extracting circuit 312 , a turbo decoder 313 , a switch 314 , a cyclic redundancy check (CRC) decoder 315 and a block decoder 316 . The storing circuit 311 is coupled with the deinterleaver 300 . The storing circuit 311 comprises a memory 3111 and a control circuit 3112 . The memory 3111 is DRAM or RAM or the like. The memory 3111 must have the capacity to store at least one unit of received data at a time. The memory 3111 stores the arranged received data 300 a . The control circuit 3112 instructs the memory 3111 to output the stored received data 311 a according to a control signal 315 a.

The information sequence extracting circuit 312 is coupled with the storing circuit 311 . The information sequence extracting circuit 312 comprises an AND circuit 3121 and a D-type flip-flop 3122 . The AND circuit 3121 is coupled with the storing circuit 311 . The AND circuit 3121 extracts the block coding sequence from the stored received data 311 a according to a control signal 317 . The control signal 317 is generated in a main control circuit. As shown in FIG. 1 , the control signal 317 is a pulse signal having a high voltage level for a short time every cycle. The AND circuit 3121 extracts the data from the stored received data 311 a when the control signal 317 has a high voltage level. The extracted data 3121 a is (X 1 , X 2 , X 3 , . . . , α 3 ). If there is no error in the transmitted data, the extracted data 3121 a is the same as the block coding sequence Bn. The D-type flip-flop 3122 is coupled with the AND circuit 3121 . The D-type flip-flop 3122 latches the extracted data 3121 a according to a clock signal 318 which is generated by a central control portion, and outputs the latched data 312 a . The information sequence extracting circuit 312 extracts the block coding sequence from the arranged received signal (turbo coding sequence) without turbo decoding. Because, the turbo code is the systematic code, and comprises the block coding sequence Bn and the redundancy bits Yij which is attached after the block coding sequence Bn. Therefore, only if the information sequence extracting circuit 312 extracts the redundancy bits Yij from the stored received data 311 a , the block coding sequence Bn is extracted.

The turbo decoder 313 is coupled with the storing circuit 311 . The turbo decoder 313 decodes the stored received data 311 a according to the control signal 315 a , and generates a turbo-decoded data (new block coding sequence) 313 a . The switch 314 is coupled with the information sequence extracting circuit 312 and the turbo decoder 313 . The switch 314 outputs either the latched data 312 a or the turbo-decoded data 313 a according to the control signal 315 a . The CRC detector 315 detects whether an error exists in the latched data 312 a or the turbo-decoded data 313 a , and outputs the control signal 315 a , the latched data 312 a or the turbo-decoded data 313 a and a detection result 315 b which shows whether an error is detected or not. The block decoder 316 decodes the latched data 312 a or the turbo-decoded data 313 a.

Next, an operation of the apparatus for extracting an information sequence from transmitted data in a wireless communication system of the present invention will be described reference to FIG. 4 . FIG. 4 is a flow chart showing an operation of the apparatus of the present invention.

The deinterleaver 300 arranges an order of the received data to be in the previous order as it was at the transmitter side (S 401 ). The memory 3111 of the storing circuit 311 stores the arranged received data 300 a (S 402 ). The control circuit 3112 of the storing circuit 311 instructs the memory 3111 to output the stored received data 311 a , according to the control signal 315 a . The AND circuit 3121 extracts the data from the stored received data 311 a according to the control signal 317 . The D-type flip-flop 3122 of the information sequence extracting circuit 312 latches the extracted data 3121 a according to the clock signal 318 , and outputs the latched data 312 a (S 403 ). The switch 314 electrically connects the information sequence extracting circuit 312 and the CRC detector 315 . The CRC detector 315 detects whether an error exists in the latched data 312 a (S 404 ). If no error is detected in the latched data 312 a , the latched data 312 a and a CRC detection result 315 b are output to the block decoder 316 . The block decoder 316 decodes the latched data 312 a (S 407 ).

On the other hand, if error is detected in the latched data 312 a (S 407 ), the CRC detector 315 outputs the control signal 315 a having a high voltage level. The turbo decoder 313 decodes the stored received data 311 a according to the control signal 315 a , and generates the turbo-decoded data 313 a (S 405 ). The switch 314 electrically connects the turbo decoder 313 and the CRC detector 315 . The CRC detector 315 detects whether an error exists in the turbo-decoded data 313 a (S 406 ). If no error is detected in the turbo-decoded data 313 a , the turbo-decoded data 313 a and a CRC detection result 315 b are output to the block decoder 316 . The block decoder 316 decodes the turbo-decoded data 313 a (S 407 ). If error is detected in the turbo-decoded data 313 a , the control circuit 3112 instructs the memory 3111 to output next arranged transmitted data 300 a.

According to the apparatus for extracting an information sequence from received data in a wireless communication system and the method thereof, first, the received data is detected using CRC. Then, if no error is detected in the received data, the apparatus and method of the present invention does not turbo-decode. On the other hand, if error is detected in the received data, the apparatus and method of the present invention turbo-decodes the received data. Therefore, the apparatus and method of the present invention prevent electric power consumption from increasing.

While the preferred form of the present invention has been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the spirit of the invention.

The scope of the invention, therefore, is to be determined solely by the following claims.