Method and apparatus for encoding or decoding data in accordance with an NB/(N+1)B block code, and method for determining such a block code

The invention pertains to methods and apparatus for encoding data in accordance with an NB/(N+1)B block code for transmission and to methods and apparatus for decoding the encoded data. The invention is particularly useful in communication environments in which the spectrum of the transmitted signal is significantly constrained, e.g., in high-speed, wired data transmission systems which require the spectrum of the transmitted signal to be restricted to as a narrow a band of high frequencies as possible, and to be free of a DC component.

Throughout the disclosure, including in the claims, the notation “nB/mB” code (or “n-bit-to-m-bit” code) is used to denote a block code in which n-bit symbols (input words) are encoded as m-bit code words, where m>n. For example, in a class of well-known conventional block codes are 8B/10B codes in wich 8-bit input words are encoded as 10-bit code words.

Throughout the disclosure, including in the claims, the term “symbol” is used synonymously and interchangeably with the expression “input word.”

Throughout the disclosure, including in the claims, the expression “table lookup” denotes a mapping operation that is implemented in any manner (not necessarily by searching a ROM or CAM type memory for an output value in response to an input value). For example, table lookup can be implemented using a memory-based lookup table or a logic-based lookup table, as a complex logic function (that performs the equivalent of a memory-based table lookup), as a logic truth table/Karnaugh map, or in any other suitable manner.

A digital communication channel imposes restrictions on the nature of the data it can carry. For example, during serial data transmission (transmission of a signal indicative of a bit sequence), sufficient transitions must be present to enable accurate clock and data recovery at the receiver, the DC component of the transmitted signal should be eliminated to prevent baseline wander, and the pass band frequency range should be minimized to reduce design complexity. To meet these requirements, conventional high-speed serial communication often transmits data that have been encoded using a conventional 8B/ 10B block code (e.g., the conventional code, sometimes referred to as the “IBM” 8B/10B code, described in U.S. Pat. No. 4,486,739, issued on Dec. 4, 1984). The IBM 8B/10B block code is DC-free, guarantees 3 transitions per code word, and ensures that the maximum run without a transition is 4 bits. However, an 8B/10B block code provides low channel utilization (only 80% of the channel capacity is available for application use). Communication protocols layered above this channel code further reduce channel capacity for carrying useful data.

To encode data using a block code, a sequence of user data bits is encoded as a larger number of bits according to a predetermined table or function. The added bits of overhead preferably ensure a high transition density to facilitate clock/data recovery, and accomplish DC balancing to maintain running disparity near zero, which enables the use of AC-coupling. Since the code space is larger than the data space, a modest error detection capability is also afforded.

Various serial links for transmitting data and clock signals are well known. One conventional serial link, used primarily for high-speed transmission of video data from a host processor (e.g., a personal computer) to a monitor, is known as a transition minimized differential signaling interface (“TMDS” link). The characteristics of a TMDS link include the following:

1. video data are encoded using an 8B/10B block code and transmitted as encoded words (each 8-bit word of digital video data is converted to an encoded 10-bit word before transmission):

a. the encoding determines a set of “in-band” words and a set of “out-of-band” words (the encoder can generate only “in-band ” words in response to video data, although it can generate “out-of-band” words in response to control or sync signals. Each in-band word is an encoded word resulting from encoding of one input video data word. All words transmitted over the link that are not in-band words are “out-of-band” words);

b. the encoding of video data is performed such that the in-band words are transition minimized (a sequence of in-band words has a reduced or minimized number of transitions);

c. the encoding of video data is performed such that the in-band words are DC balanced (the encoding prevents each transmitted voltage waveform that is employed to transmit a sequence of in-band words from deviating by more than a predetermined threshold value from a reference potential. Specifically, the tenth bit of each “in-band” word indicates whether eight of the other nine bits thereof have been inverted during the encoding process to correct for an imbalance between running counts of ones and zeroes in the stream of previously encoded data bits);

2. the encoded video data and a video clock signal are transmitted as differential signals (the video clock and encoded video data are transmitted as differential signals over conductor pairs);

3. three conductor pairs are employed to transmit the encoded video, and a fourth conductor pair is employed to transmit the video clock signal; and

4. signal transmission occurs in one direction, from a transmitter (typically associated with a desktop or portable computer, or other host) to a receiver (typically an element of a monitor or other display device).

A use of the TMDS serial link is the “Digital Visual Interface” interface (“DVI” link) adopted by the Digital Display Working Group. A DVI link can be implemented to include two TMDS links (which share a common conductor pair for transmitting a video clock signal) or one TMDS link, as well as additional control lines between the transmitter and receiver.

A typical DVI link includes a transmitter, a receiver, and a cable comprising conductors connected between the transmitter and receiver. The conductors include a conductor pair for transmitting serialized data over one channel (Channel 0) from an encoder (in the transmitter) to a decoder (in the receiver), a conductor pair for transmitting serialized data over another channel (Channel 1) from another encoder in the transmitter to another decoder in the receiver, a conductor pair for transmitting serialized data over another channel (Channel 2) from a third encoder in the transmitter to third decoder in the receiver, and a conductor pair for transmitting a video clock over a fourth channel (Channel C) from the transmitter to the receiver. The conductors also include wires for a Display Data Channel (“DDC”) channel (which can be used for bidirectional I2C communication between the transmitter and receiver), a Hot Plug Detect (HPD) line (on which a monitor associated with the receiver transmits a signal that enables a processor associated with the transmitter to identify the monitor's presence), “Analog” lines for analog video transmission from the transmitter to the receiver, and “Power” lines for provision of power from the transmitter to the receiver.

Each encoder in the transmitter encodes the data to be transmitted over one of Channels 0, 1, and 2, and serializes the encoded bits to be transmitted over the relevant channel. Each encoder responds to a control signal (an active high binary control signal referred to as a “data enable” or “DE” signal) by selectively encoding either digital video words (in response to DE having a high value) or a control or synchronization signal pair (in response to DE having a low value). Each of the encoders receives a different pair of control or synchronization signals: a first encoder receives horizontal and vertical synchronization signals (HSYNC and VSYNC); a second encoder receives control bits CTL 0 and CTL 1 ; and a third encoder receives control bits CTL 2 and CTL 3 . Thus, each encoder generates in-band words indicative of video data (in response to DE having a high value), the first encoder generates out-of-band words indicative of the values of HSYNC and VSYN having a low value), the second encoder generates out-of-band words indicative of the values of CTL 0 and CTL 1 (in response to DE having a low value), and the third encoder generates out-of-band words indicative of the values of CTL 2 and CTL 3 (in response to DE having a low value). In response to DE having a low value, each of the second and third encoders generates one of four specific out-of-band words indicative of the values 00, 01, 10, or 11, respectively, of control bits CTL 0 and CTL 1 (or CTL 2 and CTL 3 ).

Another serial link is the “High Definition Multimedia Interface” interface (“HDMI” link) developed by Silicon Image, Inc., Matsushita Electric, Royal Philips Electronics, Sony Corporation, Thomson Multimedia, Toshiba Corporation, and Hitachi. It has been proposed to transmit encrypted video and audio data over an HDMI link.

Another serial link (sometimes referred to as a “SATA” link) complies with the standard known as Serial ATA, Revision 1.0, adopted on Aug. 29, 2001, by the Serial ATA Working Group, for communication between a host and storage device. A host can be coupled to each of one or more storage devices, with a SATA link between the host and each storage device.

Other serial links differ from TMDS links by encoding data as N-bit code words that are not 10-bit TMDS code words, or by transmitting encoded video over more than three or less than three conductor pairs, or in other ways.

The term “transmitter” is used herein in a broad sense to denote any device capable of encoding data and transmitting the encoded data over a serial link (and optionally also performing additional functions, which can include encrypting the data to be transmitted and other operations related to encoding, transmission, or encryption of the data). The term “receiver” is used herein in a broad sense to denote any device capable of receiving and decoding data that has been transmitted over a serial link (and optionally also performing additional functions, which can include decrypting the received data and other operations related to decoding, reception, or decryption of the received data). For example, the term transmitter can denote a transceiver that performs the functions of a receiver as well as the functions of a transmitter. For another example, in a system including two transceivers which communicate via a serial link, each transceiver can be both a receiver and a transmitter.

The data transmitted between the transmitter and receiver of a serial link can, but need not, be transmitted differentially (over a pair of conductors). Also, although a TMDS link has four differential pairs (in the single pixel version), three for video data and the other for a video clock, other serial links include a different number of conductors or conductor pairs.

Typically, the primary data transmitted by a TMDS link are video data. What is often significant about this is that the video data are not continuous, and instead have blanking intervals. These blanking intervals provide an opportunity for auxiliary data to be transported, and they represent unused bandwidth. However, many serial links do not transmit data having blanking intervals, and thus do not encode input data (for transmission) in response to a data enable signal. For example, audio serial links would typically transmit continuous data.

The term “stream” of data, as used herein, denotes that all the data are of the same type and are transmitted with the same clock frequency. The term “channel,” as used herein, refers to a portion of a serial link that is employed to transmit data serially (e.g., a particular conductor or conductor pair between the transmitter and receiver over which the data are transmitted serially, and specific circuitry within the transmitter and/or receiver used for transmitting and/or recovery of the data) and to the technique employed to transmit the data over the link.

It is known to encode input words in accordance with an NB/(N+1)B block code, and to transmit the resulting (N+1)-bit code words over a serial link. For example, U.S. Pat. No. 6,198,413, issued on Mar. 6, 2001, teaches use of a 7B/8B block code with a 9B/10B block code, with concatenation of the resulting 8 and 10 bit code words to implement 16B/18B encoding. U.S. Pat. No. 6,198,413 suggests (at col. 10, line 51 to col. 11, line 22) generation of some of the code words by logic circuitry (e.g., circuitry that appends a zero or one to a 9-bit input word to generate a 10-bit code word), but that table lookup may need to be used to generate other ones of the code words where logic circuitry for doing so cannot readily be implemented. It also suggests (at col. 11, lines 25-30) use of two sets of logic circuitry for encoding (e.g., logic circuitry for appending a zero or one to some 9-bit input words to generate 10-bit code words, and other logic circuitry which inverts some bits of other 9-bit input words and performs some other logical operation on each resulting 9-bit word to generate a 10-bit code word). It also teaches (e.g., with reference to XOR gates 4008 and 4010 of FIG. 4) an encoding method in which two different codebooks are used to encode each input word of an input word sequence, and a code word is chosen from one codebook (rather than the other) to encode each input word such that the chosen code word will not increase running disparity (and will thus tend to promote DC balance) of a code word sequence indicative of the input word sequence.

However, U.S. Pat. No. 6,198,413 does not teach an automated, robust method for choosing an NB/(N+1)B code, or a method for choosing an NB/(N+1)B code so that table lookup is used only rarely (if ever) during encoding of an input word sequence.

In preferred embodiments, the invention is a method and apparatus for encoding N-bit input words using a block code to generate (n+1)bit code words. Preferably, “N” is an odd integer (e.g., N=7 or N=9). In some preferred embodiments, (N+M)-bit input words are encoded to generate (N+N+2)-bit code word, using a first block code to encode an N-bit fragment of each input word as an (N+1)-bit code word, using a second block code to encode the remaining M bits of the input word as an (M+1)-bit code word, and concatenating the (N+1)-bit code word with the (M+1)-bit code word. Preferably, “N” and “M” are odd integers.

Block coding in accordance with the invention can provide spectral properties similar to those provided by conventional 8B/10B coding while reducing the channel coding overhead (e.g., to about 10% for a 9B/10B code from about 20% for a conventional 8B/10B code). This provides greater channel capacity for application use, thereby increasing the effective bandwidth of the communication link. Alternatively, the savings from the reduced overhead is redeployed (e.g., by transmitting control bits and/or special characters with the encoded data) to create an enhanced physical and link layer that provides higher level communication protocol functionality (communication protocol functionality at at least one level higher than the link level).

To implement preferred embodiments of the invention, the N most desirable (N+1)-bit code words having disparity greater than or equal to zero (i.e., the N most desirable code words that have more ones than zeros, or an equal number of ones and zeros) are selected to determine a “positive” codebook (each N-bit input word is mapped to one of the code words in the positive codebook). A “negative” codebook, including the complement of each code word in the positive codebook, is also determined. Each code word in the negative codebook has disparity less than or equal to zero, and each of the N-bit input words is mapped to one of the code words in the negative codebook. The code words are chosen so that, for most input words, a simple systematic mapping to an (N+1)-bit code word in the positive codebook exists and can be implemented by simple logic circuitry (e.g., to force a transition with the added bit). During encoding, the other N-bit input words (typically only a small subset of the full set of N-bit symbols) can be replaced by code words of the positive codebook via table lookup. The resulting code words from the positive codebook are then replaced by their complements (members of the negative codebook) as necessary to maintain DC balancing.

When using positive and negative codebooks in which each code word has an even number of bits, code words of neutral disparity (disparity equal to zero) can occur in both codebooks. If each code word has an odd number of bits, each codebook would include only code words with strictly positive (or strictly negative) disparity. In the latter case, the codebooks would be forced to contain disjoint halves of the code space and the spectrum could not be deterministically controlled. Thus, in preferred implementations of NB/(N+1)B coding in accordance with the invention, N is an odd number. However, such codes do not have good affinity with 8-bit data that is typically used in computer systems. If this issue increases the implementation complexity beyond a reasonable measure, two such codes can be used together to form less dense code spaces that possess better alignment with 8-bit data. For example, 9B/10B and 7B/8B codes can be used together to form a 16B/ 18B code, by concatenating 8-bit and 10-bit code words generated in accordance with the 9B/10B and 7B/8B codes to generate 18-bit code words.

Preferred embodiments of the invention take advantage of the typical case that most of the N-bit input words exhibit the desired spectral properties by implementing a simple, systematic mapping of each such input word to an (N+1)-bit code word (preferably using simple logic circuitry). The input words that do not exhibit desired spectral properties are mapped to code words with more complex functions or via a simple table.

In preferred embodiments, the invention is a method for selecting positive and negative codebooks that are complements of each other that includes the following steps. Selection of the positive codebook begins by eliminating all candidate code words having negative disparity. The remaining candidate code words are then filtered, preferably in automated fashion (e.g., by a programmed computer) based on predetermined spectral properties to select a subset of the candidate code words that determines the positive codebook. For example, simple filters eliminate each of the candidate code words having transition density below a predetermined transition density, each of the candidate code words having disparity greater than a predetermined disparity, and each of the candidate code words having a transition-free run of length that exceeds a predetermined maximum run length. Spectral analysis of the code space can be used to rank the potential code words and select only those above a particular threshold for inclusion in the codebook. For example, code words with runs greater than 5, transition density less than 30%, or disparity greater than 4 can be eliminated. The code words of the positive codebook are then selected from the remaining candidate code words to determine a bijective (injective, in the sense that when f(x 1 )=f(x 2 ), it is true that x 1 =x 2 , and positive codebook. For each input symbol, the code word in the negative codebook is then identified as the complement of the code word in the positive codebook for the input symbol.

In variations, the positive and negative codebooks are not strictly complements of each other. For example, in some embodiments, the code words of the negative codebook having nonzero disparity are complements of corresponding code words of the positive codebook, but the code words of the negative codebook that have zero disparity are identical to (they are not complements of) corresponding code words of the positive codebook.

In preferred embodiments, a mapping is defined from input words to a “positive” codebook containing only code words of neutral or positive disparity, and the mapping of each code word of the positive codebook to a code word of a corresponding “negative” codebook is determined simply by complementing the former code word to generate the latter code word. Alternatively, the mapping of each code word (having nonzero disparity) of the positive codebook to a code word of a corresponding “negative” codebook is determined by complementing the former code word to generate the latter code word, and each code word (having zero disparity) of the positive codebook is identical to a corresponding code word of the “negative” codebook. Ideally, for each codebook, a mapping function from the input words to the code words (of the codebook) is found that is bijective and simple to implement using logic circuitry. However, even if such an ideal mapping function cannot be found, a simple mapping function can typically be identified that covers a large subset of the input symbol space, and the remaining input symbols are handled as special cases (e.g., special input symbols for which encoding must be accomplished using look up tables).

Preferred embodiments in which most input words meet the desired spectral constraints employ a straightforward mapping that systematically concatenates a bit of predetermined value (e.g. a zero bit) with (e.g., prepends or appends the bit to) each input word to form a code word, or systematically inserts a bit of predetermined value (e.g. a zero bit) in a predetermined position among the bits of each input word to form a code word. Possibilities for such mapping functions include inserting a bit so that symbol disparity becomes more positive (and complementing the resulting code word if its disparity is negative) and inserting a bit so that symbol disparity approaches zero (complementing the resulting code word if its disparity is negative). Many other mappings are also possible. The selection of a mapping depends on its symbol coverage and implementation complexity. For small code spaces, the exemplary mappings set forth in this paragraph can provide coverage of roughly 80% of the input words, while requiring only simple logic circuitry to implement.

The input words for which a straightforward mapping (implementable by simple logic circuitry) fails will typically significantly violate the spectral constraints (e.g., they will have very low transition density). These symbols can be subjected to a secondary mapping technique that applies a more complex function. For example, the secondary mapping could perform alternate bit inversion for symbols with low transition density, complementing the resulting code word if its disparity is negative. The implementation cost of the secondary mapping must be weighed against the cost of simply handling all the unmapped symbols as special cases, using a simple implementation structure such as a lookup table.

When the secondary mapping is accomplished by table lookup, the mapping can be arbitrarily complex. This gives greater flexibility to the mapping process. For example, code words can be selected so as to minimize the magnification of bit errors in the encoded data stream.

In a class of embodiments, the invention is a communication system including two endpoints (e.g., a transmitter and receiver or two transceivers) and a serial link (having at least one channel) between the endpoints, at least one of the endpoints is configured to generate encoded data by encoding input words in accordance with a line code and to transmit the resulting code words over each of one or more channels of the link to the other endpoint, and the line code specifies an NB/(N+1)B block code for encoding the input words. Typically, the line code also specifies special characters that are distinguishable from bit sequences of the transmitted code words. Another aspect of the invention is an endpoint device (i.e., a transmitter, receiver, or transceiver) configured to generate encoded data in accordance with a line code (where the line code specifies an NB/(N+1)B block code for encoding input words, and typically also specifies special characters) and to transmit the encoded data over a serial link, and/or to receive and decode such encoded data after the encoded data have propagated over a serial link.

Other aspects of the invention are methods for generating encoded data in accordance with a line code (where the line code specifics an NB/(N+1)B block code for encoding input words, and typically also specifies special characters), methods for decoding such encoded data, and methods for determining a set of code words (e.g., positive and negative codebooks) for implementing such a block code.

FIG. 1 is a block diagram of an embodiment of the inventive system.

FIG. 2 is a diagram of a cell of data (cell 80 ), an ordered set of 9-bit words (indicative of the cell) that can be encoded in accordance with the invention, and an ordered set ( 89 ) of 10-bit code words (indicative of the cell) generated in accordance with an embodiment of the invention.

FIG. 3 is a block diagram of an embodiment of an encoder that can be included in circuit 32 of transmitter 10 , and in circuit 42 of receiver 20 , of the FIG. 1 system.

FIG. 4 is a block diagram of an embodiment of a decoder that can be included in circuit 33 of transmitter 10 , and in circuit 43 of receiver 20 , of the FIG. 1 system.

In preferred embodiments, the invention is a method and apparatus for encoding N-bit input words using a block code to generate (N+1)-bit code words. Preferably, “N” is an odd integer (e.g., N=7 or N=9).

Preferred embodiments of the invention take advantage of the typical case that most of the N-bit input words exhibit the desired spectral properties by implementing a simple, systematic mapping of each such input word to an (N+1)-bit code word (preferably using simple logic circuitry). The input words that do not exhibit desired spectral properties are mapped to code words with more complex functions or via a simple table.

To implement preferred embodiments of the invention, the N most desirable (N+1)-bit code words having disparity greater than or equal to zero (i.e., the N most desirable code words that have more ones than zeros, or an equal number of ones and zeros) are selected to determine a “positive” codebook (each N-bit input word is mapped to one of the code words in the positive codebook). A “negative” codebook, including the complement of each code word in the positive codebook, is also determined. Each code word in the negative codebook has disparity less than or equal to zero, and each of the N-bit input words is mapped to one of the code words in the negative codebook. The code words are chosen so that, for most input words, a simple systematic mapping to an (N+1)-bit code word in the positive codebook exists and can be implemented by simple logic circuitry (e.g., to force a transition with the added bit). During encoding, the other N-bit input words (typically only a small subset of the full set of N-bit symbols) can be replaced by code words of the positive codebook via table lookup. The resulting code words from the positive codebook are then replaced by their complements (members of the negative codebook) as necessary to maintain DC balancing.

In variations, the positive and negative codebooks are not strictly complements of each other. For example, in some embodiments, the code words of the negative codebook having nonzero disparity are complements of corresponding code words of the positive codebook, but the code words of the negative codebook that have zero disparity are identical to corresponding code words of the positive codebook. In the embodiments described in the two previous paragraphs, the same code word can belong to both codebooks, and two different input words can map to the same code word (e.g., in the example of 7B/8B encoding shown in Table 3, the input 0000000 maps to “11000011” in the positive codebook and to “00111100” in the negative book, and the input word whose decimal value is “60” maps to “00111100” in the positive book and “11000011” in the negative book). The running disparity value determines which codebook to use in encoding/decoding each value (e.g., in a typical embodiment, the positive codebook is used if the running disparity is negative, and otherwise the negative codebook is used).

One codebook (a “positive” codebook) contains only code words of neutral or positive disparity (i.e., code words containing more 1's than 0's, or an equal number of 1's and 0's), and the other (a “negative” codebook) contains code words of neutral or negative disparity. Symbols are encoded with the codebook that moves the running disparity toward zero (or leaves the running disparity unchanged). When using “positive” and “negative” codebooks, in which each code word has an even number of bits, code words of neutral disparity (disparity equal to zero) can occur in both codebooks. If each code word has an odd number of bits, each codebook would include only code words with strictly positive (or strictly negative) disparity. In the latter case, the codebooks would be forced to contain disjoint halves of the code space and the spectrum could not be deterministically controlled. Thus, in preferred implementations of NB/(N+1)B coding in accordance with the invention, N is an odd number.

Use of two codebooks that are complementary means that if a particular input symbol s maps to code word pcs in the positive disparity codebook and to code word ncs in the negative disparity codebook, then pcs is the bitwise inverse of ncs. This enables circuitry for one codebook (together with code word-inverting logic) to perform encoding/decoding in accordance with both codebooks.

A preferred method for selecting positive and negative codebooks that are complements of each other includes the following steps. Selection of the positive codebook begins by eliminating all candidate code words having negative disparity. The remaining candidate code words are then filtered based on desired spectral properties. For example, simple filters eliminate candidate code words with insufficient transition density, with excessive disparity, or with transition-free runs that widen the pass band too greatly. Spectral analysis of the code space can be used to rank the potential code words and select only those above a particular threshold for inclusion in the codebook. For example, code words with runs greater than 5, transition density less than 30%, or disparity greater than 4 could be eliminated. The code words of the positive codebook are then selected from the remaining candidate code words to create a one-to-one mapping between the symbol space and the positive codebook. For each input symbol, the code word in the negative codebook is then identified as the complement of the code word in the positive codebook for the input symbol.

Another preferred method for selecting positive and negative codebooks includes the following steps. Selection of the positive codebook begins by eliminating all candidate code words having negative disparity. The remaining candidate code words are then filtered based on desired spectral properties. For example, simple filters eliminate candidate code words with insufficient transition density, with excessive disparity, or with transition-free runs that widen the pass band too greatly. Spectral analysis of the code space can be used to rank the potential code words and select only those above a particular threshold for inclusion in the codebook. For example, code words with runs greater than 5, transition density less than 30%, or disparity greater than 4 could be eliminated. The code words of the positive codebook are then selected from the remaining candidate code words to create a one-to-one mapping between the symbol space and the positive codebook. For each input symbol, the code word in the negative codebook is then identified as the complement of the code word in the positive codebook for the input symbol (if the code word in the positive codebook for the symbol has nonzero disparity), or as the code word in the positive codebook for the input symbol (if the code word in the positive codebook for the symbol has zero disparity).

In a class of embodiments, a positive codebook for implementing a target code (e.g. a 9B/10B code) is selected in accordance with the invention as follows. First, guidelines for the desired spectral properties (e.g., minimum transition density and maximum run length) of the encoded data are established. Candidate code spaces are then selected (where “code space” denotes the set of all code words to which a set of input symbols can be mapped) using the guidelines, preferably by searching in automated fashion (e.g., using a programmed computer) through a wide range of possible code spaces. A mapping (“candidate” mapping) from input symbols to code words is determined for each candidate code space, and the candidate mappings are evaluated using a small set of metrics to select at least one “best” code (consisting of a set of input symbols, a positive codebook, and a mapping between each input symbol to a different code word of the positive codebook). For example, in one implementation of the method, the guidelines specify that each code word of a candidate code space must have a minimum transition density of 20% (or 30%), a maximum disparity of 4 (or 6), and a maximum run length of 6 (or 7). In addition, several run length guidelines can be employed, each specifying an allowable pattern of runs in each code word of a candidate code space. For example, the guidelines can specify that a code word be excluded from the code space if there is a run at the left end of the code word of length greater than 3, a run at the right end of the code word of length greater than 3, or a run away from the left and right ends of the code word of length greater than 6 (with the intent to choose code words that can create maximum runs of no more than 6 in any stream of valid code words). However, the same effect could be had by excluding (from the code space) each code word having a run of length greater than 2 on the left (i.e., a run including the most significant bit, and having length greater than 2), a run of length greater than 4 on the right (i.e., a run including the least significant bit, and having length greater than 4), or a run of length greater than 6 away from the left and right ends of the code word has length greater than 6. Also, it is sometimes desirable to select the guidelines so they over-constrain relative to an initial choice of guidelines (e.g., by excluding each code word having a run of length greater than 5 away from the left and right ends of the code word, where exclusion of each code word having a run of length greater than 6 away from the left and right code word ends would achieve adequate results). Run length filters can be applied to runs of 0s and 1s independently. Since allowing any possible disparity and transition density for code words would typically allow selection of more candidate code spaces than would be practical, it is typically desirable to specify constraints on the code space in addition to run length constraints. For example, only code words with a disparity of less than 8 might be allowed, or (where it is desired to find a code with minimum disparity to avoid EMI issues) only code words with a disparity of less than 4 might be allowed.

Once the filters (for selecting candidate code spaces) are defined, a wide range of possible code spaces is preferably searched (e.g., by brute force) to identify candidate code spaces, a mapping is created from the input symbols to the code words of each candidate code space, and the candidate mappings are evaluated based on the small set of metrics. The metrics that are used for evaluation specify spectral properties, and typically include the following: minimum transitions per code word, average transitions per code word over all legal code word pairs (all possible pairs of code words that could appear in a transmission stream of valid code words according to one of the candidate code spaces), normalized DC offset (sum of running disparity values after each bit of a block of code words, divided by the number of bits in the block), maximum run length (e.g., for all possible pairs of code words that could appear in a transmission stream of valid code words according to one of the candidate code spaces), maximum digital sum variation, and the number of exception cases in the code mapping (i.e. the number of mappings that must be implemented using a table lookup, or other secondary mapping, rather than by applying a primary mapping). The best code space and mapping with respect to each parameter are reported, and the ranges of metric values encountered are preferably also reported. Typically, this narrows the code possibilities to not more than six, and the designer can select the most desirable code based on the engineering trade-offs appropriate to the application.

To choose a mapping between the input symbols and the code words of each candidate code space, preferred embodiments of the invention proceed in two phases as follows, using a greedy algorithm (preferably performed by an appropriately programmed personal computer or other processor) in the second phase. The first phase seeks a systematic mapping (sometimes referred to herein as a “primary” mapping) from input symbols to code words that provides the best coverage (i.e., the primary mapping function that successfully maps the largest number of input symbols to valid code words). Typically, several systematic mappings are evaluated, including mappings that: force a transition on the first (or last) bit consider disparity of input symbol and add a bit to make the disparity of the resulting code word approach zero (preferably, insertion of the bit in all possible positions is tested); use alternate bit inversion (i.e. flip every other bit of the input symbol) for symbols with transition density below the minimum; add a 0 bit to the input symbol so that disparity of the resulting code word is less (if the input symbol's disparity is negative, all bits are inverted after the 0 bit is added. Preferably, insertion of the bit in all possible positions is tested); add a 1 bit to the input symbol so that disparity of the resulting code word is greater (if the input symbol's disparity is positive, all bits are inverted after the 1 bit is added. Preferably, insertion of the bit in all possible positions is tested); and always add a 0 bit (or 1 bit) to the input symbol (preferably, insertion of the bit in all possible positions is tested). Many other primary mapping functions are possible.

Once each of the candidate primary mappings has been evaluated, the primary mapping function that successfully maps the most input symbols is selected (for each candidate code space), and the second phase then determines a mapping (for each candidate code space) of the remaining unmapped input symbols to the remaining code words. The second phase considers only symbols that were not mapped by the primary function selected in the first phase, and can determine any of a variety of “secondary” mapping functions for mapping those input symbols that are not mapped to code words by the primary mapping. In preferred embodiments, the secondary mapping is accomplished using table lookup and limits (or minimizes) error magnification. Error magnification occurs when a small error in the transmitted code word results in successful decoding of a symbol that differs from the intended symbol by a larger amount. For example, suppose symbol 000000000 maps to code word 1010101010 and symbol 111111111 maps to code word 1010101011. If the code word 1010101010 is transmitted, but the last bit of this code word receiver will decode the errored word 1010101011 and determine the received symbol to be 111111111. Thus, a 1-bit error in the code space has been magnified to a 9-bit error in the symbol space. Since preferred embodiments of the primary mapping leaves the symbol unchanged and merely adds a bit, the error magnification for these symbols is limited.

Preferably, the second phase searches for individual secondary mappings that minimize error magnification using a greedy algorithm that enumerates through all possible error magnification values, beginning at 1, and tries to map as many symbols as possible so that errors are magnified by no more than the amount specified. For example, the algorithm first maps as many symbols as it can so that each 1-bit error in the code space results in only a 1-bit error in the symbol space. Next, it maps as many symbols as it can so that each 1-bit error in the code space results in only a 1-bit or 2-bit error in the symbol space. This process continues (each time with a relaxed error magnification constraint) until all symbols have been mapped. The greedy algorithm preferably includes the steps of: (a) selecting a code word of the code space that does not have a symbol mapped to it; (b) then, considering all code words that differ from the selected code word by a single bit (i.e. all code words that would result from a single bit error), and identifying each symbol (if any) that maps to one of the errored versions of the selected code word (steps (a) and (b) select an unused code word and identify a first set of symbols that map to all code words that differ from the selected code word by a target error magnification, where the target error magnification is a single bit during the first performance of step (b)); (c) then, searching the unmapped symbols for one that differs from each member of the first set by no more than the target error magnification (which is equal to one bit during the first performance of step (c), and can be equal to two or more bits during subsequent performances of step (c)) and mapping such previously unmapped symbol (if one is found) to the selected code word; (d) then, repeating steps (a), (b), and (c), each time for a different selected code word but without changing the target error magnification, until all previously unmapped symbols are mapped or no new mapping having the target error magnification can be determined; (e) then, if all the symbols have not been mapped, incrementing the target error magnification by one, and repeating steps (a), (b), (c), and (d), using the incremented target error magnification (e.g., two bits during the first performance of step (e), and three bits during the next performance of step (e)) until all previously unmapped symbols are mapped or no new mapping having the increased target error magnification limit can be determined; and (f) then, if all the symbols have not been mapped, again incrementing the target error magnification by one, and repeating step (e) using the newly incremented target error magnification. A mapping determined in accordance with such an algorithm minimizes error magnification during the decoding process.

In preferred embodiments, a mapping is defined from input words to a “positive” codebook containing only code words of neutral or positive disparity, and the mapping of each code word of the positive codebook to a code word of a corresponding “negative” codebook is determined simply by complementing the former code word to generate the latter code word. Alternatively, the mapping of each code word (having nonzero disparity) of the positive codebook to a code word of a corresponding “negative” codebook is determined by complementing the former code word to generate the latter code word, and each code word (having zero disparity) of the positive codebook is identical to a corresponding code word of the “negative” codebook. Ideally, a mapping function from input words to the code words of the positive codebook (or the negative codebook) is found that is bijective and simple to implement using logic circuitry. However, even if such an ideal mapping function cannot be found, a simple mapping function can typically be identified that covers a large subset of the input symbol space, and the remaining input symbols are handled as special cases (e.g., special input symbols for which encoding must be accomplished using lookup tables or other “secondary” encoding circuitry).

For many applications, full lookup tables (for encoding or decoding) are not practical implementation choices. Preferred embodiments for such applications use a systematic mapping technique implemented by simple logic circuitry without any lookup table (or with only a small lookup table for handling a small subset of the full set of input words) for encoding and decoding. The encoder in each of circuit 32 and 42 of the FIG. 1 system preferably implements such a systematic mapping technique.

FIG. 1 is a block diagram of a typical system that embodies the invention. The FIG. 1 system includes transceivers 10 and 20 , and a serial link between them. The serial link includes primary channel 51 and back channel 52 (and optionally also other channels, not shown). Transceiver 10 will be referred to as a transmitter since it transmits application data to transceiver 20 over the serial link. Transceiver 20 will be referred to as a receiver since it does not transmit application data to transceiver 10 over the serial link, although it does transmit other data to transceiver 10 . The FIG. 1 system implements a bidirectional communication path in which primary channel 51 carries application traffic, and back channel 52 (which typically is smaller than channel 51 in the sense that it carries a smaller volume of data than channel 51 ) carries link management traffic that is not exposed to the application. Primary channel 51 carries code words indicative of control data (e.g., out-of-band or “OOB” bits to be discussed below) and application data, and typically also special characters (e.g., idle characters used for simplex or duplex link flow control, and link training characters) that are not indicative of application data. Back channel 52 carries information related to error control, end-to-end flow control, and data sequencing. For example, back channel 52 carries code words indicative of control data related to error control, end-to-end flow control, and data sequencing, and typically also special characters (e.g., link training characters). Typically, the same physical layer requirements are applied across both channels 51 and 52 . Preferably, a block code is used, and the length of the block code is chosen to ensure that total overhead is comparable to other common line codes while simultaneously minimizing design and implementation complexity.

Some but not all elements of transmitter 10 are shown in FIG. 1 . The physical layer and link layer circuitry of transmitter 10 includes packetizing circuit 31 , encoding and transmission circuit 32 , receiving and decoding circuit 33 , error detection and correction circuit 34 , and de-packetizing circuit 35 , connected as shown. Transmitter 10 also includes higher layer circuitry 30 , which typically includes network layer circuitry, transport layer circuitry, and application layer circuitry. In operation, higher layer circuitry 30 provides application data and control data to packetizing circuit 31 . For example, the control data provided to circuit 31 by circuitry 30 can determine the XTND, FLOW, OOB 1 , and OOB 2 bits to be described with reference to FIG. 2 . In response, packetizing circuit 31 generates (and asserts to circuit 32 ) sequences of input words (e.g., the 9-bit input words of FIG. 2, each of which comprises eight application data bits and one control bit) that are indicative of cells (e.g., a sequence of code words having the form shown in FIG. 2, each cell including two 64-bit application data blocks, and 16 control bits). In typical implementations, packetizing circuit 31 generates CRC bits for each cell and includes the CRC bits in the input word sequences asserted to circuit 32 . Packetizing circuit 31 performs any necessary serialization of the application data and control data from circuitry 30 , and asserts the input word sequences as serial data to circuit 32 .

Circuit 32 encodes the input words from circuit 31 (e.g., to generate one of the 10-bit code words shown in FIG. 2 in response to each 9-bit input word), and transmits the code words serially over channel 51 to receiver 20 . Circuit 32 can also transmit (over channel 51 ) one or more special characters. In some implementations, circuit 32 transmits each special character before or after a cell of code words (i.e., before or after a sequence of code words indicative of a cell), but does not transmit any special character during a cell. However, in preferred implementations, the set of code words employed to encode cells (for transmission over channel 51 ) and the special characters are chosen such that no special character can unintentionally occur in a sequence of code words indicative of a cell (i.e., no special character matches any of the code words, and no sequence of bits from any possible sequence of consecutively transmitted code words matches any of the special characters). In such preferred implementations, circuit 32 can transmit any special character at any time (including by interrupting transmission of a cell to transmit the special character), and the circuitry (e.g., circuit 43 of receiver 20 ) employed for receiving and decoding code words transmitted by circuit 32 can be configured (e.g., can include logic configured) to recognize each transmitted special character, regardless of whether transmission of the special character has or has not interrupted transmission of a cell.

An example of special character transmission by an implementation of circuit 32 is the transmission of special “idle” characters at appropriate times between cells (e.g., for duplex link flow control). For another example, in response to control signals from error detection and correction circuit 34 , an implementation of circuit 32 asserts special “link training” characters and special “state exchange” characters with embedded sequence numbers during a link re-training operation initiated by a control signal from circuit 34 .

Receiving and decoding circuit 33 decodes code words received sequentially on back channel 52 to generate a stream of decoded words (e.g., 9-bit words as shown in FIG. 2, each comprising eight application data bits and one control bit). In various implementations of the FIG. 1 system (and variations thereon) which implement different line codes, the decoded words generated by the receiver are M-bit words (where M can be any integer, although M is odd in preferred embodiments), and the decoded words of a cell can include any predetermined pattern of application data and control bits (e.g., each cell can include a repeating pattern of four control bits followed by thirty-two application data bits, or can consist of four control bits followed by 128 application data bits followed by twelve CRC bits, or any of many other patterns of application data and control bits).

In a typical implementation, error detection and correction circuit 34 identifies CRC bits in the stream of decoded words, uses the CRC bits to perform error detection and correction on a cell of the decoded words (e.g., on a sequence of sixteen 9-bit words having the FIG. 2 format), and asserts the corrected decoded words to de-packetizing circuit 35 (except in the event that circuit 34 identifies an uncorrectable error in a cell).

De-packetizing circuit 35 then determines which of the bits of the corrected, decoded words are application data bits and which are control data bits, and asserts the application data, and appropriate ones of the control bits (separately from the application data) to higher layer circuitry 30 for processing. Circuit 35 performs any necessary deserialization of the data it receives from circuit 34 (e.g., to assert application data and control bits in parallel to circuitry 30 ).

Some but not all elements of receiver 20 are shown in FIG. 1 . The physical layer and link layer circuitry of receiver 20 includes packetizing circuit 41 , encoding and transmission circuit 42 , receiving and decoding circuit 43 , error detection and correction circuit 44 , and de-packetizing circuit 45 , connected as shown. Receiver 20 also includes higher layer circuitry 40 , which typically includes network layer circuitry, transport layer circuitry, and application layer circuitry. In operation, higher layer circuitry 40 can provide application data and control data to packetizing circuit 41 . For example, circuitry 40 can provide (to circuit 41 ) control data (generated by application layer circuitry) that determine the FLOW bits to be described with reference to FIG. 2 . In response, packetizing circuit 41 generates (and asserts to circuit 42 ) sequences of input words (e.g., the 9-bit input words of FIG. 2, each of which comprises eight application data bits and one control bit) that are indicative of cells (e.g., a sequence of code words having the form shown in FIG. 2, each cell including two 64-bit application data blocks, and 16 control bits). In typical implementations, packetizing circuit 41 generates CRC bits for each cell and includes the CRC bits in the input word sequences asserted to circuit 42 . Packetizing circuit 41 performs any necessary serialization of the application data and control data from circuitry 40 , and asserts the input word sequences as serial data to circuit 42 .

Circuit 42 encodes the input words from circuit 41 (e.g., to generate one of the 10-bit code words shown in FIG. 2 in response to each 9-bit input word), and transmits the code words serially over channel 52 to transmitter 10 . Circuit 42 can also transmit one or more special characters over channel 52 . In some implementations, circuit 42 transmits each special character before or after a cell of code words (i.e., before or after a sequence of code words indicative of a cell), but does not transmit any special character during a cell. However, in preferred implementations, the set of code words employed to encode cells (for transmission over channel 52 ) and the special characters are chosen such that no special character can unintentionally occur in a sequence of code words indicative of a cell (i.e., no special character matches any of the code words, and no sequence of bits from any possible sequence of consecutively transmitted code words matches any of the special characters). In such preferred implementations, circuit 42 can transmit any special character at any time (including by interrupting transmission of a cell to transmit the special character), and the circuitry (e.g., circuit 33 of transmitter 10 ) employed for receiving and decoding code words transmitted by circuit 42 can be configured (e.g., can include logic configured) to recognize each transmitted special character, regardless of whether transmission of the special character has or has not interrupted transmission of a cell.

An example of special character transmission by an implementation of circuit is the transmission of special “idle” characters at appropriate times between cells (in a manner to be described below). For another example, in response to control signals from error detection and correction circuit 44 , an implementation of circuit 42 asserts special “link training” characters and special “state exchange” characters with embedded sequence numbers during a link re-training operation (to be described below) initiated by a control signal from circuit 44 .

Receiving and decoding circuit 43 (of receiver 40 ) decodes code words received sequentially on channel 51 to generate a stream of decoded words (e.g., 9-bit words as shown in FIG. 2, each comprising eight application data bits and one control bit). In a typical implementation, error detection and correction circuit 44 identifies CRC bits in the stream of decoded words, uses the CRC bits to perform error detection and correction on a cell of the decoded words (e.g., on a sequence of sixteen 9-bit words having the FIG. 2 format), and asserts the corrected decoded words to de-packetizing circuit 45 (except in the event that circuit 44 identifies an uncorrectable error in a cell). De-packetizing circuit 45 then determines which of the bits of the corrected, decoded words are application data bits and which are control data bits, and asserts the application data, and appropriate ones of the control bits (separately from the application data) to higher layer circuitry 40 for processing. Circuit 45 performs any necessary deserialization of the data it receives from circuit 44 (e.g., to assert application data and control bits in parallel to circuitry 40 ).

In a class of preferred embodiments, code words indicative of cells (of application data and control data) having the format shown in FIG. 2 are transmitted over a serial link. The following steps are performed to accomplish this.

First, logical blocks of application data are defined (e.g. 64-bit blocks as shown in FIG. 2, or 32-bit blocks). This can be accomplished, for example, by application layer circuitry within circuitry 30 (or circuitry 40 ) of FIG. 1 . For each application data block, an out-of-band (“OOB”) bit is provided to indicate the priority level of the block, or to specify a virtual channel to which the block belongs. For example, the “OOB 1 ” bit in FIG. 2 can indicate whether the block labeled “Application Data Word 1 ” consists of low priority data (e.g., application data) or high priority data (e.g., control data), and the “OOB 2 ” bit can similarly indicate whether the block labeled “Application Data Word 2 ” consists of low priority data (e.g., application data) or high priority data (e.g., control data.

The application data blocks (sometimes referred to as words) are grouped into cells (e.g., by packetizing circuit 31 or 41 of FIG. 1 ). To minimize latency associated with re-transmission (e.g., after an uncorrectable error during transmission), the number of application data words per cell should be minimized (e.g., there are only two words per cell). A flow control bit (identified as “FLOW” in FIG. 2) is included in each cell. The flow control bits and application data blocks are the only data visible to the application. In each cell, at least one additional control bit (e.g., the XTND control bit of FIG. 2) can be included, and additional bits (e.g., an address extension) can also be included to provide optional functionality such as network addressing. Also, error control bits (e.g., parity bits, or the CRC bits of FIG. 2) are generated for (and included in) each cell to enable error detection and/or correction. FIG. 2 shows an example of such a cell, consisting of 144 bits and not including an extension.

The bits of each cell are grouped into input words (e.g., in packetizing circuit 31 or 41 of FIG. 1 ). For example, the 144 bits of cell 80 of FIG. 2 are grouped into the sixteen 9-bit input words shown in FIG. 2, each comprising eight application data bits (D 0 , D 1 , D 2 , D 3 , D 4 , D 5 , D 6 , D 7 , D 8 , D 9 , D 10 , D 11 , D 12 , D 13 , D 14 , control bit.

Finally, the input words indicative of each cell are encoded, preferably to transform the frequency spectrum of a serial data stream so as to adapt to channel requirements in a manner to be described below.

In different embodiments of the invention, the sizes of input words (to be encoded), cells of the input words, blocks of CRC bits (or other error control bits) in each cell of input words, and other parameters are adjusted according to desired features and coding efficiency. For a cell having the FIG. 2 format, the above-described coding method provides 131 bits of application information (128 bits of application data, two OOB bits, and one FLOW bit) with 29 bits of protocol overhead per cell, which gives an 82% coding efficiency. The commonly used conventional 8B/10B coding scheme achieves only 80% efficiency for the physical layer alone.

In many contemplated embodiments, code words indicative of cells (of application data and control data) having format other than that shown in FIG. 2 are transmitted. For example, in some embodiments the XTND bit discussed with reference to FIG. 2 is replaced by a second FLOW bit. If each cell includes two evenly spaced FLOW bits (each applying to all priority levels of application data), no more than half a cell time would be wasted on either endpoint when the value of the FLOW bit is to be changed, which would reduce system buffering requirements by one cell.

In other exemplary embodiments, the FLOW bit of FIG. 2 is removed and replaced by a “Valid” bit that indicates whether or not the second 64-bit block of application data in the cell contains valid data (in such embodiments the first 64-bit application data block is always valid; otherwise, the transmitter would transmit “idle” characters, of the type mentioned above and discussed further below, rather than code words indicative of cells). The line code employed in some embodiments of the invention has a coding efficiency of less than 80%, although many other embodiments have a coding efficiency greater than 80%.

FIG. 3 is a block diagram of an embodiment of an encoder that can be included in circuit 32 of transmitter 10 and in circuit 42 of receiver 20 of the FIG. 1 system. The FIG. 3 circuit includes encoding logic circuit 60 (“primary” encoding logic 60 ), lookup table circuit 61 (“secondary” encoding circuit 61 ), and disparity calculation circuit 62 , each coupled to receive a sequence of symbols to be encoded. Each symbol consists of N bits. Each of circuits 60 and 61 outputs an (N+1)-bit code word in response to an N-bit symbol at its input. The output of circuit 61 (the codebook, and the output of circuit 60 can be a member of either the positive codebook or the negative codebook. Inverter 65 outputs the complement of each code word output from circuit 60 . Inverter 71 outputs the complement of each code word output from circuit 61 .

The FIG. 3 circuit operates as follows to perform encoding in accordance with the invention. A running disparity value (the “disparity in ” value) is asserted to an input of each of addition unit 72 , subtraction unit 73 , and multiplexer 76 . The running disparity value is indicative of the accumulated disparity of a sequence of code words generated by the FIG. 3 circuit. Typically, the running disparity value is initially set to one (for processing the first input symbol). The running disparity value is then updated each time another input symbol is generated. When a new symbol is ready to be encoded, the current running disparity (the current “disparity in ” value) is used to select the appropriate codebook (the positive or negative codebook) to be used to encode the symbol. If the current “disparity in ” value is less than zero, the positive disparity codebook is used (the first, or upper, input of each of multiplexers 67 , 70 and 75 is selected). Otherwise, the negative disparity codebook is used (the second, or lower, input of each of multiplexers 67 , 70 , and 75 is selected). For each symbol of a subset of the full set of symbols, a look up table (implemented by circuit 61 ) determines the code word. The code word for each symbol is output (at the output of multiplexer 68 ) and its disparity is added to the running disparity value to generate an updated running disparity value (the “disparity out ” value) which is asserted at the output of multiplexer 76 .

Both the primary mapping and secondary mapping of the input symbol are applied (by circuits 60 and 61 , respectively) to generate candidate code words, and the complements of these candidate code words are also created (in inverters 65 and 71 ). Thus, four candidate code words (the outputs of circuits 60 and 61 and inverters 65 and 71 ) are generated in response to each input symbol.

Primary encoding logic 60 concatenates a zero bit with the N-bit input symbol so that the most significant bit (MSB 0 ) of the resulting (N+1)-bit candidate code word is a zero. In variations on the FIG. 3 embodiment, other primary mapping functions are utilized.

Lookup table circuit 61 asserts an (N+1)-bit candidate code word in response to each N-bit input symbol that is a member of a small subset of the full set of 2 N input symbols (the members of this subset are sometimes referred to herein as “secondary” symbols). The output of circuit 61 is valid (as indicated by a “one” value of the “SEL” bit asserted by circuit 61 ) when the input symbol asserted thereto is a secondary symbol. Circuit 61 does not output valid lookup table values in response to input symbols that are not secondary symbols. A “zero” value of the SEL bit indicates that the output of circuit 61 is not valid. In other words, the SEL bit indicates whether or not the lookup table (implemented by circuit 61 ) includes a code word determined by the most recent input symbol, and thus indicates whether or not the input symbol's spectral properties meet the criteria for primary mapping by logic circuit 60 . The SEL bit is asserted as a control signal to multiplexer 68 , to cause multiplexer 68 to select a candidate code word generated by the primary mapping (the output of multiplexer 67 ) if SEL has a “zero” value, or to select a candidate code word generated by the secondary mapping (the output of multiplexer 70 ) if SEL has a “one” value. The SEL bit is also asserted as a control signal to multiplexer 76 , to cause multiplexer 76 to select the appropriate updated running disparity value (in a manner to be discussed below).

Each valid word output from circuit 61 is an (N+1)-bit candidate code word having known disparity (e.g., zero disparity assuming that the code is as set forth in Table 1, 3, 4, or 5, or positive disparity in other possible codes generated in accordance with the invention). Thus, the complement of each such valid word (asserted at the output of inverter 71 ) also has known disparity. The output of circuit 61 is asserted to the first input (the upper input in FIG. 3) of multiplexer 70 , and its complement is asserted to the second input (the lower input in FIG. 3) of multiplexer 70 .

The disparity of the input symbol must be determined to identify whether the candidate code word output from circuit 60 , or its complement (the candidate code word asserted at the output of inverter 65 ) is a member of the positive codebook. This operation is performed by logic circuit 64 . Circuit 64 calculates the disparity of the candidate code word output from circuit 60 by summing its bits. If the candidate code word output from circuit 60 has non-negative disparity, circuit 64 asserts to the first (upper) input of multiplexer 67 the output of circuit 60 and asserts to the second (lower) input of multiplexer 67 the output of circuit 65 . If the candidate code word output by circuit 60 has negative disparity, circuit 64 asserts to the first input of multiplexer 67 the output of circuit 65 and asserts to the second input of multiplexer 67 the output of circuit 60 . This description assumes that each code word of the negative codebook is the complement of a corresponding code word of the positive codebook. Of course, if the code words of the negative codebook having zero disparity are identical to corresponding code words of the positive codebook, the encoding circuitry would be modified accordingly (so that the complement is never selected for zero disparity code words).

The current running disparity (the “disparity in ” value at the inputs of addition unit 72 and subtraction unit 73 ) is updated as follows to generate the updated running disparity (the “disparity out ” value at the output of multiplexer 76 ).

If we assume that all code words determined by the lookup table (implemented by circuit 61 ) have zero disparity (as is true in the cases that the FIG. 3 circuit implements the code to be described with reference to Table1, 3, 4, or 5), then each code word determined by the secondary mapping (i.e., each code word output from multiplexer 68 when SEL=1) has zero disparity. Thus, in response to the control signal value SEL=1, multiplexer 76 selects the current running disparity (“disparity in ”) as the updated running disparity (“disparity out ”).

To determine the updated running disparity in the case that the primary mapping is used (i.e., when SEL=0), disparity calculation circuit 62 determines the disparity (“sdisp”) of a candidate code word that consists of a zero bit concatenated with (e.g., appended or prepended to) the bits of the input symbol (i.e., circuit 62 determines the disparity of the input symbol and subtracts one therefrom). Disparity calculation circuit 62 asserts a signal indicative of the disparity value “sdisp” to circuit 74 and to an input of each of units 72 and 73 . It should be kept in mind that the candidate code word whose disparity is determined by circuit 62 can be the actual code word asserted at the output of multiplexer 68 , or the complement of such actual code word.

If the value “sdisp” is negative, circuit elements 74 , 75 , and 76 ensure that the updated running disparity (“disparity out ”) is the output of addition unit 72 (“sdisp” plus “disparity in ,” where disparity in is the current running disparity) when disparity in is positive, and that disparity out is the output of subtraction unit 73 (“disparity in ” minus “sdisp”) when disparity in is negative. If the value “sdisp” is positive or zero, circuit elements 74 , 75 , and 76 ensure that the updated running disparity (“disparity out ”) is the output of addition unit 72 (“sdisp” plus “disparity in ”) when disparity in is negative and that the updated running disparity (“disparity out ”) is the output of subtraction unit 72 (“disparity in ” minus “sdisp”) when disparity in is positive.

Thus, circuit 74 asserts the output of addition unit 72 to the first (upper) input of multiplexer 75 and the output of subtraction unit 73 to the second (lower) input of multiplexer 75 when “sdisp” is positive or zero, and circuit 74 asserts the output of addition unit 72 to the second input of multiplexer 75 and the output of subtraction unit 73 to the first input of multiplexer 75 when “sdisp” is negative or zero. Multiplexer 75 passes through the value at its first input to multiplexer 76 when the current running disparity (disparity in ) is negative, and multiplexer 75 passes through the value at its second input to multiplexer 76 when disparity in is non-negative.

Multiplexer 76 passes through to its output the value it receives from multiplexer 75 when the primary mapping is used (i.e., when SEL=0). Otherwise, multiplexer 76 passes through to its output the current running disparity (disparity in ).

With reference to FIG. 4, we next describe an embodiment of the inventive circuitry for decoding the code words generated by the encoder of FIG. 3 . In some implementations of the FIG. 1 system, the decoder circuit of FIG. 4 is included in block 33 of transmitter 10 of FIG. 1, and in block 43 of receiver 20 of FIG. 1 . The FIG. 4 circuit includes decoding logic circuit 80 (“primary” decoding logic 80 ), lookup table circuit 87 (“secondary” decoding circuit 87 ), multiplexers 81 , 85 , and 86 , inverters 82 and 84 , and disparity calculation circuit 83 , connected as shown. Each of elements 80 , 81 , 82 , and 83 is coupled to receive a sequence of code words to be decoded. Each code word consists of N+1 bits. Each of circuits 80 and 87 outputs an N-bit symbol in response to an (N+1)-bit code word at its input. Inverter 82 outputs the complement of each code word, and asserts this complement to the second input of multiplexer 81 .

The FIG. 4 circuit operates as follows to perform decoding in accordance with the invention. The decoding method is essentially the reverse of the encoding method performed by the FIG. 3 circuit.

Primary decoding logic 80 decodes each (N+1)-bit code word that it receives by passing through, to inverter 84 and the first (upper) input of multiplexer 85 , the N least significant bits of the code word. The output of inverter 84 , which is the complement of each N-bit symbol received at its input, is asserted to the second (lower) input of multiplexer 85 . Multiplexer 85 passes through to a first input of multiplexer 86 the N-bit symbol at its first input when the value of the bit by the primary encoding function (e.g., the MSB) is zero, and otherwise passes through to the first input of multiplexer 86 the N-bit symbol at its second input. In variations on the implementation described in the preceding sentence, another Boolean function (a Boolean function that does not simply look at the value of the inserted bit) is used as the selection criterion for multiplexer 85 .

Inverter 82 generates the complement of each (N+1)-bit code word that it receives. Multiplexer 81 has a first input coupled to receive each (N+1)-bit code word received by the FIG. 4 decoder, and a second input coupled to the output of inverter 82 to receive the complement of each such code word. Multiplexer 81 passes through to secondary decoding circuit 87 the code word at its first input when the current “disparity in ” value (to be describe below) is less than zero, and otherwise passes through to secondary decoding circuit 87 the code word at its second input. If the code word asserted to the input of circuit 87 belongs to the domain of the lookup table implemented by circuit 87 , circuit 87 asserts to a second input of multiplexer 86 the N-bit symbol (lookup table value) that corresponds to suc asserts a control bit (the “SEL” bit) with a “one” value to indicate that the output of circuit 87 is valid. This description assumes that each code word of the negative codebook is the complement of a corresponding code word of the positive codebook. Of course, if the code words of the negative codebook having zero disparity are identical to corresponding code words of the positive codebook, the decoding circuitry would be modified accordingly (so that the modified circuitry never complements zero disparity code words).

If the code word asserted to the input of circuit 87 does not belong to the domain of the lookup table implemented by circuit 87 , circuit 87 does not output a valid lookup table value, and asserts the SEL bit with a “zero” value to indicate that the output of circuit 87 is not valid. The SEL bit thus indicates whether or not the lookup table (implemented by circuit 87 ) includes a symbol determined by the most recent code word.

The SEL bit is asserted as a control signal to multiplexer 86 , to cause multiplexer 86 to select the N-bit symbol received at its first input from multiplexer 85 (if SEL has a “zero” value) or to select the N-bit symbol received at its second input from circuit 87 (if SEL has a “one” value).

A running digital sum (“disparity in ”) indicative of the accumulated disparity of the code words received by the FIG. 4 circuit is initially set to one (for decoding the first received code word) and then updated each time another code word is received. Disparity calculation circuit 83 calculates the disparity of each received code word (the sum of its “one” bits minus the sum of its “zero” bits) and asserts a value indicative of each calculated disparity to a first input of adder 88 . The current “disparity in ” value is asserted to the second input of adder 88 . The output of adder 88 is an updated disparity value (“disparity out ”) which replaces the current “disparity in ” value. The updated disparity value is asserted to the second input of adder 88 before circuit 83 processes the next received code word.

The current disparity in value, or a signal (generated by circuitry not shown) that is indicative of whether current disparity in value is less than zero, is asserted as a control signal to multiplexer 81 . In response, multiplexer 81 passes through the appropriate one of its inputs, as described above. If the current disparity in value is less than zero, multiplexer 81 passes through to circuit 87 an (N+1)-bit code word at its input that was generated by an encoding operation using the positive disparity codebook.

In cases in which a full lookup table implementation is practical, the FIG. 4 circuit can be replaced by a variation on the FIG. 4 circuit in which elements 80 , 84 , 85 , and 86 are omitted. Typically, the lookup table implemented by such a variation on the FIG. 4 circuit would be much larger than that implemented by circuit 87 of FIG. 4 since it would need to provide output values for all (rather than a small subset) of the code words in the relevant codebook.

The FIG. 4 decoder can decode the code words generated by the FIG. 3 encoder only if symbol framing has been established on the serial link over which the encoder transmits the code words to the decoder. For example, when the FIG. 3 encoder is included in circuit 32 of transmitter 10 of FIG. 1 and the FIG. 4 decoder is included in circuit. 43 of receiver 20 of FIG. 1, symbol framing must be established on channels 51 and 52 before circuit 32 commences transmission of code words over channel 51 to circuit 43 .

Symbol framing is “physical layer” framing that determines the boundaries of transmitted code words, so that physical layer circuitry can decode the code words to produce decoded symbols for processing by link layer circuitry. Typically, link layer circuitry recognizes that the decoded symbols (generated by decoding a sequence of code words generated in accordance with the invention) comprise cells of application data and control bits, the link layer circuitry forwards the application data (and at least some of the control bits) to higher layer circuitry, and the link layer circuitry typically also operates in response to at least some of the control bits. “Link layer” framing allows the link layer circuitry to determine the boundaries of blocks of application data (and blocks of control bits) within cells of the decoded symbol, where the blocks of application data (or control bits) are to be utilized by higher layer circuitry.

To establish both physical layer framing and link layer framing upon startup or after a link error during operation of typical implementations of the FIG. 1 system, transmitter 10 and receiver 20 transmit at least one special “link training” character (sometimes referred to herein as a training character “T”) and optionally also at least one special “synchronization” or “state exchange” character. State exchange characters are sometimes denoted herein as “Si” characters, where the notation “Si” indicates that there are “i” different state exchange characters. For example, the “i”th state exchange character can communicate the value “i” to the endpoint that receives it, in order to exchange state information. The endpoint that receives a state exchange character “Si” interprets its value “i” in a predetermined manner. For example, the value “i” can be a sequence number which takes on the values 0,1, . . . , 7. In typical cases, less than ten different “Si” characters would be needed.

Preferably, no link training (or state exchange) character appears in any valid stream of code words that is indicative of a cell (of application data and control bits), and each such special character is self-identifying. Preferably, each link training and state exchange special character includes a preamble used for link training (e.g., to establish framing) and also a discriminant pattern that distinguishes the character from other characters. The discriminant pattern can be indicative of state information (e.g., state information useful for recovery from a link error).

In a class of implementations of the FIG. 1 system, upon startup or after a link error, a communications endpoint (e.g., transmitter 10 upon startup, or receiver 20 after a link error) enters a link training phase (or training “mode” or “state”) having an initial handshake phase. In response to one or more special characters sent by one endpoint in the handshake phase, the other endpoint enters the link training phase and participates in the handshake phase. During the handshake phase (which is implemented at the physical level), the endpoints establish symbol alignment (typically by exchanging one or more link training characters). After the handshake phase (during or after the link training phase), the endpoints exchange state information and establish cell alignment.

In typical implementations in this class, at least one state exchange character is sent (potentially with redundancy to guard against link errors) after the handshake phase. Typically, both endpoints exchange state information after the handshake phase (i.e., each endpoint sends one state exchange character, or a number of state exchange characters, to the other endpoint). Ideally, each state exchange character contains the same preamble as does each link training character sent during the handshake phase, or has some other unique property that enables link training to occur.

In some implementations, each state exchange character indicates state information regarding the endpoint that sends it. For example, one state exchange character identifies the last cell successfully received (by the endpoint that sends the state exchange character) before the link training operation, or a sequence of state exchange characters (which need not all be identical) identifies the last cell successfully received (by the endpoint that sends the state exchange character) before the link training operation. For example, each state exchange character can include a preamble (for framing) and a sequence number indicative of the last cell successfully received (by the endpoint that sends the state exchange character) before the link training operation.

In other implementations in this class, at least one state exchange character sent (potentially with redundancy to guard against link errors) after the handshake phase indicates that the first cell of normal data to be transmitted after the link training operation contains state information to be exchanged, and optionally indicates a number of cells (after such first cell) that contain additional state information. Alternatively, some portion of the first cell indicates the total number of cells that contain state information.

In other implementations in this class, no state exchange character is sent after the handshake phase. Instead, by convention, the first cell (or each of the first few cells) sent after the handshake phase contains state information to be exchanged.

In some implementations, after the handshake phase of a link training operation, at least one endpoint sends a sequence of state exchange characters, rather than a single state exchange character, whenever it sends a state exchange character. For example, a first endpoint can send a sequence of a predetermined number of Si characters (e.g., X “Si” characters, each “Si” character including a sequence number indicative of the last cell received by the first endpoint from the second endpoint). Each such sequence can be indicative of arbitrary state information. For example, such a sequence can be indicative of the sequence number of the last cell received by the endpoint that sends the state exchange character sequence (e.g., if each state exchange character in the sequence is indicative of a binary “1” or “0” and the sequence consists of N characters, the sequence number of the cell can be an N-bit binary number determined by the N-character sequence).

We next describe specific examples of codebooks that are used in preferred embodiments of the invention. Positive and negative codebooks that implement an 9B/10B code are set forth as Tables 1, 4, and 5. Table 2 sets forth special characters that are suitable for use with the 10-bit code words set forth in Table 1. Positive and negative codebooks that implement a 7B/8B code are set forth as Table 3.

We first describe the 9B/10B code whose code words are set forth as Table 1.

The primary mapping for the 9B/10B code of Table 1 prepends a 0 bit to the input symbol so that disparity of the resulting code word (the number of “one” bits thereof minus the number of “0” bits thereof) is less than the disparity of the input symbol, and complements the resulting code word if its disparity is negative. This determines the 408 code words of the positive disparity codebook (set forth in Table 1 in the second column from the left) to which the input symbols are mapped by the primary mapping. Each code word in the positive disparity codebook (sometimes referred to as the “positive” codebook) has the non-negative disparity indicated (in the third column from the left in Table 1).

The complement of each code word of positive disparity codebook determines the code word of the negative disparity codebook to which the relevant input symbol maps. This determines the 408 code words of the negative disparity codebook (set forth in Table 1 in the fourth column from the left) to which the input symbols are mapped by the primary mapping. Each code word in the negative disparity codebook (sometimes referred to as the “negative” codebook) has the non-positive disparity indicated (in the second column from the right in Table 1).

The secondary mapping for the 9B/10B code of Table 1 determines those code words in each row of Table 1 in which there is no “Y” symbol in the right column. (The primary mapping for this code determines those code words in each row of Table 1 in which there is a “Y” symbol in the right column).

Each input symbol maps to both a code word in the positive disparity codebook and a code word in the negative disparity codebook. The choice of which code word is used to encode each input symbol (in a sequence of input symbols to be encoded) is determined by the cumulative disparity of the code words that have been used to encode the previous input symbols in the sequence. More specifically, the code word from the positive codebook is used if the cumulative disparity is less than zero, and the code word from the negative codebook is used if the cumulative disparity is greater than or equal to zero.

For example, if the first input symbol (in a sequence of input symbols to be encoded) is the symbol “0” (the binary word 000000000), this input symbol is mapped to the code word “1001000111” from the positive codebook. This code word is determined by the secondary mapping, so that typically, a lookup table (e.g., a lookup table implemented by circuit 61 of FIG. 3) is used to generate the code word in response to the input symbol.

If the next input symbol (in the same sequence) is the symbol “65” (the binary word 001000001), this input symbol is mapped to the code word “1110111110” from the positive codebook. This code word is determined by the primary mapping, so that typically, logic circuitry (e.g., circuit 60 of FIG. 3) is used to generate the code word in response to the input symbol.

If the third input symbol (in the same sequence) is also the symbol “65” (the binary word 001000001), this input symbol is mapped to the code word “0001000001” from the negative codebook (since the cumulative disparity of the two previously generated code words is a positive number, 6).

The code words of the 9B/10B code of Table 1 are selected so that each code word has disparity in the range of [−6, 6] (even values only), so that each sequence of the code words has a maximum run length of 7, a running digital sum variation of 10, a transition density of at least 30% (i.e. at least 3 transitions per code word), and so that only a relative small number of input symbols (i.e., 104 symbols of the total set of 512 symbols) do not have a successful primary mapping (i.e., each of the positive and negative codebooks has 104 symbols that are determined by the secondary mapping). The code of Table 1 has an average of 5.207 transitions per code word (over all legal code pairs). Error magnification is minimized so that only 16% to 17% of single bit errors result in a burst error of 6, 7, 8, or 9 bits in the decoded symbol.

The 9B/10B code of Table 1 has been compared with the 9B/10B code outlined in U.S. Pat. No. 6,198,413, and the two codes differ in several respects. For example, the 9B/10B code of Table 1 (but not the 9B/10B code outlined in U.S. Pat. No. 6,198,413) has a normalized DC offset of 7.1.

In some embodiments, the inventive code is a 9B/10B block code having positive and negative codebooks (and a maximum run length of 7), each of the positive and negative codebooks has not more than 104 symbols that are determined by the secondary mapping, each of the code words has disparity equal to one of 6, −6, 4, −4, 2, −2, and zero, none of the code words has a run of length greater than three at one end (or a run of length greater than four at its other end, or a run of length greater than seven away from its ends), and none of the code words has less than three transitions.

Table 2 sets forth examples of special characters (“out-of-band” or “OOB” characters) that can be inserted in a stream of code words generated in accordance with the 9B/10B code of Table 1 (or the 9B/10B code of Table 4 or Table 5, described below).

In Table 2, each special character consists of a 10-bit preamble followed by a 10-bit discriminant pattern. Each special character is thus a sequence of two, 10-bit words. The preamble contains a run of eight0s or 1s, which guarantees it never appears in a legal sequence of 9B/10B code words (assuming that the Table 1, Table 4, or Table 5 implementation of the 9B/10B code is employed). Thus, the preamble can be used to establish symbol alignment. The preamble is commonly referred to as the “comma,” “comma character,” or “comma symbol.”

The discriminant identifies the code type. Applications may assign logical meanings to the OOB codes as necessary. For example, one OOB code can be used as an “idle” character (of a type described elsewhere herein) for simplex or duplex flow control, another can be used as a “link training” character (of a type described elsewhere herein), and others can be used as “state exchange” characters (“Si”) of a type described elsewhere herein. A particular application may choose to use a subset of the possible OOB values in order to increase the Hamming distance between allowable codes, thereby reducing the probability of missing errors in the transmitted characters.

Each OOB code has a “positive” and “negative” version. “Positive” OOB codes are used when the current running disparity is positive. “Negative” OOB codes are used when the current running disparity is negative. This ensures that the maximum digital sum variation does not grow too large. OOB code bits are transmitted MSB first, where the MSB is depicted on the left in Table 2. It is an error to transmit or receive a sequence with a run of eight (or more) identical bits that does not match an OOB code, and it is also an error to transmit or receive a positive OOB code when current running disparity is negative or a negative OOB code when current running disparity is positive.

Since all the OOB codes start with a run of length two and end with runs of length no more than three, they may be inserted between any pair of 9B/10B code words (assuming that the 9B/10B code words begin and end with runs of length no greater than four in all cases) without producing a run of length greater than seven (except for the run of length eight within the preamble).

We next describe the 7B/8B code whose code words are set forth as Table 3.

The primary mapping for the 7B/8B code of Table 3 also prepends a 0 bit to the input symbol so that disparity of the resulting code word (the number of “one” bits thereof minus the number of “0” bits thereof) is less than the disparity of the input symbol, and complements the resulting code word if its disparity is negative. This determines the 98 code words of the positive disparity codebook (set forth in Table 3 in the second column from the left) to which the input symbols are mapped by the primary mapping. Each code word in the positive disparity codebook (sometimes referred to as the “positive” codebook) has the non-negative disparity indicated (in the third column from the left in Table 3).

The complement of each code word of positive disparity codebook determines the code word of the negative disparity codebook to which the relevant input symbol maps. This determines the 98 code words of the negative disparity codebook (set forth in Table 3 in the fourth column from the left) to which the input symbols are mapped by the primary mapping. Each code word in the negative disparity codebook (sometimes referred to as the “negative” codebook) has the non-positive disparity indicated (in the second column from the right in Table 3).

The secondary mapping for the 7B/8B code of Table 3 determines those code words in each row of Table 3 in which there is no “Y” symbol in the right column. (The primary mapping for this code determines those code words in each row of Table 3 in which there is a “Y” symbol in the right column).

Each input symbol maps to both a code word in the positive disparity codebook and a code word in the negative disparity codebook. The choice of which code word is used to encode each input symbol (in a sequence of input symbols to be encoded) is determined by the cumulative disparity of the code words that have been used to encode the previous input symbols in the sequence. More specifically, the code word from the positive codebook is used if the cumulative disparity is less than zero, and the code word from the negative codebook is used if the cumulative disparity is greater than or equal to zero.

The code words of the 7B/8B code of Table 3 are selected so that each code word has disparity in the range of [−4, 4] (even values only), so that each sequence of the code words has a maximum run length of 6, a running digital sum range of 16, a minimum transition density of 25% (i.e. at least 2 transitions per code word), and an average transition density of 4.181 transitions per code word (over all legal code word pairs), and so that only a relative small number of input symbols (i.e., 30 symbols of the total set of 128 symbols) do not have a successful primary mapping (i.e., each of the positive and negative codebooks has 30 symbols that are determined by the secondary mapping). The normalized DC offset is 4.75. Error magnification is minimized so that only 10% of single bit errors result in a burst error of 6 or 7 bits in the decoded symbol.

In some embodiments, the inventive code is a 7B/8B block code having positive and negative codebooks (and a maximum run length of 6), each of the positive and negative codebooks has not more than 30 symbols that are determined by the secondary mapping, each of the code words has disparity equal to one of 4, −4, 2, −2, and zero, none of the code words has a run of length greater than three at either end, none of the code words has a run of length greater than six away from its ends, and none of the code words has less than two transitions.

A 16B/18B code is determined by using the block code of Table 1 to encode a 9-bit fragment of each 16-bit input word as a 10-bit code word, using the block code of Table 3 to encode the remaining 7 bits of the input word as an 8-bit code word, and concatenating the 10 bit code word with the 8-bit code word. This 16B/18B code has a maximum run length of 7, a running digital sum variation of 15, and a transition density of 28% (i.e., at least 5 transitions per code word).

Different 16B/18B codes can be created using various 9B/10B codes generated in accordance with the invention (including those described with reference to Tables 4 and 5).

We next describe the 9B/10B code whose code words are set forth as Table 4.

In Table 4, the 512 code words set forth in the second column from the left determine the positive disparity codebook of the Table 4 code to which the input symbols map. Each code word in the positive disparity codebook (sometimes referred to as the “positive” codebook) has the non-negative disparity indicated (in the third column from the left in Table 4). The complement of each code word of positive disparity codebook determines the code word of the negative disparity codebook to wich the relevant input symbol maps. This determines the 512 code words of the negative disparity codebook (set forth in Table 4 in the fourth column from the left) to which the input symbols map. Each code word in the negative disparity codebook (sometimes referred to as the “negative” codebook) has the non-positive disparity indicated (in the second column from the right in Table 4).

The secondary mapping for the 9B/10B code of Table 4 determines those code words in each row of Table 4 in which there is an “N” symbol in the right column. (The primary mapping for this code determines those code words in each row of Table 4 in which there is a “Y” symbol in the right column).

The Table 4 code favors lower digital sum variation over higher transition density with the goal of providing better EMI characteristics for transmission of long distances. The code space is defined as follows:

each code word having disparity 0 has a run of length three or less on either end, and includes no run of length greater than six away from its ends;

each code word having disparity 2, −2, 4, or −4 has a run of length four or less on the left, a run of length three or less on the right, and includes no run of length greater than seven away from its ends;

no code word has disparity greater than 4 or less than −4; and

no code word has less than 2 transitions.

The code set forth in Table 4 differs from (and is improved in several respects over) the 9B/10B block code outlined in above-cited U.S. Pat. No. 6,198,413. The code of Table 4 has a maximum run length of 7, a maximum digital sum variation of 16, an average of 5.248 transitions per code word (over all legal code pairs), and a normalized DC offset of 4.9. Of the 512 code words in the positive codebook, only 116 are not determined by the primary mapping.

In variations on the code set forth in Table 4 (or Table 1 or 3), the positive and negative codebooks are not strictly complements of each other. Rather, the code words having nonzero disparity are identical to those of Table 4 (or Table 1 or 3), so that the code words of the negative codebook having nonzero disparity are complements of corresponding code words of the positive codebook, but the code words of the negative codebook that have zero disparity are identical to corresponding code words of the positive codebook. The code words having zero disparity can be either the zero-disparity code words of the positive codebook of Table 4 (or 1 or 3)or the zero-disparity code words of the negative codebook of Table 4 (or 1 or 3).

We next describe the 9B/10B code whose code words are set forth as Table 5.

In Table 5, the 512 code words set forth in the second column from the left mine the positive disparity codebook of the Table 5 code to which the input symbols map. Each code word in the positive disparity codebook (sometimes referred to as the “positive” codebook) has the non-negative disparity indicated (in the third column from the left in Table 5). The complement of each code word of positive disparity codebook determines the code word of the negative disparity codebook to which the relevant input symbol maps. This determines the 512 code words of the negative disparity codebook (set forth in Table 5 in the fourth column from the left) to which the input symbols map. Each code word in the negative disparity codebook (sometimes referred to as the “negative” codebook) has the non-positive disparity indicated (in the second column from the right in Table 5).

The secondary mapping for the 9B/10B code of Table 5 determines those code words in each row of Table 5 in which there is an “N” symbol in the right column. (The primary mapping for this code determines those code words in each row of Table 4 in which there is a “Y” symbol in the right column).

The Table 5 code favors higher transition density over lower digital sum variation with the goal of providing better clock data recovery performance for transmission over short distances. The code space is defined as follows:

each code word having disparity 0 has a run of length three or less on either end, and includes no run of length greater than six away from its ends;

each code word having disparity 2, −2, 4, −4, 6, or −6 that has a run of zeroes on the left has a run of zeroes of length two or less on the left;

each code word having disparity 2, −2, 4, −4, 6, or −6 that has a run of zeroes on the right has a run of zeroes of length three or less on the right;

each code word having disparity 2, −2, 4, −4, 6, or −6 that has a run of ones on the left has a run of ones of length three or less on the left;

each code word having disparity 2, −2, 4, −4, 6, or −6 that has a run of ones on the right has a run of ones of length four or less on the right;

no code word having disparity 2, −2, 4, −4, 6, or −6 has a run of zeroes of length greater than six away from its ends;

no code word having disparity 2, −2, 4, −4, 6, or −6 has a run of ones of length greater than seven away from its ends;

no code word has disparity greater than 6 or less than −6; and

no code word has less than 3 transitions.

These rules select 513 code words out of the 1024 possible 10-bit code words.

The code set forth in Table 5 differs from (and is improved in several respects over) the 9B/10B block code outlined in above-cited U.S. Pat. No. 6,198,413. The code of Table 5 has a maximum run length of 7, a maximum digital sum variation of 20, an average of 5.29 transitions per code word (over all legal code pairs), and a normalized DC offset of 6.9. Of the 512 code words in the positive codebook, only 113 are not determined by the primary mapping.

In variations on the code set forth in Table 5, the positive and negative codebooks are not strictly complements of each other. Rather, the code words having nonzero disparity are identical to those of Table 5 (the code words of the negative codebook having nonzero disparity are complements of corresponding code words of the positive codebook) but the code words of the negative codebook that have zero disparity are identical to corresponding code words of the positive codebook. The code words having zero disparity can be either the zero-disparity code words of the positive codebook of Table 5 or the zero-disparity code words of the negative codebook of Table 5.

For each of the Table 1 code, the Table 4 code, and the Table 5 code, the same prefixes for denoting control/out-of-band characters are used. In particular, when current running disparity is <0, the prefix is 0011111111. The prefix is 1100000000 when current running disparity is >0. A comma or control code contains a 10-bit code following this prefix so that the total disparity across the 20 bits is 0 and so that it does not end with a run of length greater than 3. This gives 25 possible combinations for each prefix, i.e. 25 possible 20-bit out-of-band characters. If one allows the OOB characters to be longer than 20 bits, one can have more possible values.

The exemplary codes described with reference to Tables 1, 3, 4, and 5 were generated in accordance with the invention using the above-described method in which guidelines for the desired spectral properties of the encoded data are established, and a positive codebook is then determined by using automated filtering to select candidate code spaces using the guidelines, determining a candidate mapping from input symbols to code words for each candidate code space, and evaluating the candidate mappings using a small set of metrics to select one code (consisting of a set of input symbols, a positive codebook, and a mapping between each input symbol to a different code word of the positive codebook). The negative codebook for each code was then determined from the positive codebook.

In the exemplary codes described with reference to Tables 1, 3, 4, and 5, all code words determined by the secondary mapping have zero disparity. This results in an optimization in the encoding and decoding circuitry typically employed for implementing the codes, in that the disparity of the code words output from the look up table (which implements the secondary mapping or its inverse) need not be stored or added to the input disparity.

However, other codes used or generated in accordance with the invention have code words that are determined by the secondary mapping but which have nonzero disparity. The circuitry employed for encoding data in accordance with codes of this type (or for decoding the code words) would typically require circuitry for storing indications of the disparity of the code words output from a look up table (which implements the secondary mapping or its inverse) and for adding the disparities of such code words to the input disparity during the encoding (or decoding).

In a class of embodiments, the invention is a method of encoding data, including the steps of generating N-bit input words; and encoding the input words in accordance with a block code to generate a code word sequence of (N+1)-bit code words. In some such embodiments, the block code is specified by a line code, the line code also specifies special characters, and the method also includes the step of generating encoded data such that the encoded data are a sequence of at least one of the special characters and the code words of the code word sequence. Preferably, “N” is an odd integer.

In another class of embodiments, the invention is a method of encoding data, including the steps of generating (N+M)-bit input words; and encoding the input words in accordance with a block code to generate a code word sequence of (N+M+2)-bit code words, by using a first block code to encode an N-bit fragment of each input word as an (N+1)-bit code word, using a second block code to encode the remaining M bits of the input word as an (M+1)-bit code word, and concatenating the (N+1)-bit code word with the (M+1)-bit code word. Preferably, “N” and “M” are odd integers. In some such embodiments, the block code is specified by a line code, the line code also specifies special characters, and the method also includes the step of generating encoded data such that the encoded data are a sequence of at least one of the special characters and the code words of the code word sequence.

Data encoded using an NB/(N+1)B block code can be used for many different purposes, some of which have been described with reference to FIGS. 1 and 2. Another exemplary use of NB/(N+1)B block coding is to concatenate (N−1)-bit input data words with single control bits (or single bits of a logical channel distinct from the input data channel) to generate N-bit input symbols, and then to encode the N-bit input symbols as (N+1)-bit code words. Another exemplary use of NB/(N+1)B block coding is to increase the deliverable bandwidth to the application by grouping the bits of (N−1)-bit input data words as N-bit input symbols (e.g., by concatenating a first (N−1)-bit input data word with the first bit of a second (N−1)-bit input data word, and so on), and then encoding the N-bit input symbols as (N+1)-bit code words.

A 9B/10B block code (or other NB/(N+1)B block code) is modular, in the sense that it does not have to be entwined with a particular protocol. Its interface could simply be to map between a fixed number of symbols and code words once every clock cycle.

The term “includes” as used in the claims denotes “consists of or includes.”

It should be understood that while certain forms of the present invention are illustrated and described herein, the invention is defined by the claims and is not to be limited to the specific embodiments described and shown. claims