Bus interface and method for coupling a bus device to a bus

The present invention relates to a bus interface as well as a method for connecting a bus device to a bus.

Bus interfaces and/or connecting methods are available, e.g., for a controller area network bus (CAN bus) in motor vehicles. Such a bus has a pair of bus lines, wherein one bus line has a signal level with a time characteristic that is complementary to that of the other bus line. The bus interfaces are used for coupling of bus devices in phase opposition, e.g., communication components, systems and/or subsystems, to the bus. A bus interface having a pair of driver circuits is known, wherein a first driver circuit with an output is connected to the first bus line and a second driver circuit which is complementary in operation to the first driver circuit which has an output that is connected to the second bus line. Each driver circuit has a switching element, one being implemented as a p-channel transistor and the other being implemented as an n-channel transistor.

In the case of such a bus interface, the inputs of both driver circuits are connected to the bus device. Triggering of the two driver circuits in phase opposition is accomplished with an inverting element at one of the two inputs. However, the triggering of the two driver circuits in phase opposition thus embodied results in phase displacement and asymmetry between the output signals of the two driver circuits because of differences in transit time, differences in the p- and n-channel transistors used and/or component tolerances. Consequently, there is the risk that the output signals are not sufficiently accurately in phase opposition, which results in increased high-frequency emission to the outputs and the bus lines.

U.S. Pat. No. 6,111,431 relates to a driver circuit for transmitting a differential signal to an external circuit. According to this embodiment, the driver circuit has a plurality of transistors P 21 , P 22 and P 33 . In the event of an output-end short circuit to the driver circuit, damage to transistors N 21 , N 22 is prevented by a component R 31 . Transistors N 11 and N 12 are protected from a short circuit in the driver circuit in a similar manner. Transistors P 21 and P 22 are controlled by a first operational amplifier OPAMP 1 , while transistors N 11 and N 12 are controlled by a second operational amplifier OPAMP 2 . Transistors N 22 , N 23 and transistors N 21 , N 24 are alternately turned on and off by the arrangement of two inverters IV 31 , IV 34 and NOR gates 31 , 34 and NOR gates 32 , 33 .

The bus interface according to an exemplary embodiment and/or method of the present invention may have the advantage over other designs wherein the use of the output signal of the first driver circuit for triggering the second driver circuit results in a more pronounced phase opposition of the two output signals. The voltage range of the output signals may be kept constant. High-frequency emissions are thus reduced.

The exemplary embodiment and/or method of the present invention also provides a voltage divider between the outputs of the driver circuits for triggering the second driver circuit and for tapping the center voltage. The second driver circuit may be configured as a regulating circuit which regulates the center voltage of the voltage divider at a predetermined level, in particular at half the supply voltage. The second driver circuit is advantageously formed by an operational amplifier. The bus may be a CAN bus, as is conventional in motor vehicles today, in particular a serial bus. The present invention also includes a method of connecting a bus device to a bus.

A differential amplifier having a differential output which is activated only by a received signal may also be used.

FIG. 1 is a view of a bus interface according to an exemplary embodiment and/or method of the present invention.

FIG. 2A is a time diagram of signal characteristics for a bus interface other than the exemplary embodiment and/or method of the present invention.

FIG. 2B is a time diagram of signal characteristics in the bus interface according to the exemplary embodiment and/or method of the present invention.

The bus interface according to FIG. 1 is intended to be switched between a bus device at input In 1 and a bus having lines H, L at outputs Out 1 , Out 2 .

The bus may be a serial controller area network bus such as that used in motor vehicles. The bus has two complementary lines H, L, which has signal levels that are to be in mutual phase opposition, i.e., when the signal on one bus line is at a low level, the signal on the other bus line is at a high level.

The phase opposition of the signals on the two bus lines H, L is ensured by two driver circuits 1 , 10 , 11 , 2 , 20 , 21 . First driver circuit 1 , 10 , 11 having switching element 1 and resistors 10 , 11 is connected to the input of the bus device. If switching element 1 is conducting, then output line Out 1 is at a high level. If switching element 1 is blocking, output signal Out 1 is at a low level accordingly. The input of second driver circuit 2 , 20 , 21 is not connected to the bus device but instead receives in input In 2 a signal coming from output Out 1 of first driver circuit 1 , 10 , 11 . The signal is picked up in the middle of a voltage divider which has resistors 3 , 4 and is connected between two outputs Out 1 and Out 2 .

The equilibrium level at the outputs is set via resistors 3 , 4 , 5 , 6 . U denotes the power supply voltage.

Second driver circuit 2 , 20 , 21 has an operational amplifier 2 which is wired to function as a regulating circuit. The regulating circuit is set via resistor 20 at the inverting input and voltage source 21 at the non-inverting input so that center voltage UM is regulated by the voltage divider, formed by two resistors 3 , 4 , at half of power supply voltage U/2. Thus, when output signal Out 1 increases, center voltage UM also increases. This center voltage UM is looped back to the inverting input of operational amplifier 20 . As a response to the increase in the input voltage at the inverting input, operational amplifier 20 lowers the voltage level at output Out 2 accordingly, so that level UM is set at half of power supply voltage U/2. If output signal Out 1 drops, the mechanism described here is reversed, and output signal Out 2 becomes a higher-level signal. This achieves a mutual phase opposition of the two output signals Out 1 and Out 2 .

Driver circuit 2 , 20 , 21 is controlled as a function of the signal at output Out 1 of first driver circuit 1 , 10 , 11 . This minimizes asynchronicity of the output signals such as that caused by differences in transit time and component tolerances in two driver circuits 1 , 10 , 11 and/or 2 , 20 , 21 . This results in a more pronounced phase opposition and a lower high-frequency emission of both bus lines H, L.

In FIGS. 2A , B, time characteristics of the voltage in a bus interface in other devices are compared with those of the bus interface according to the present invention.

FIG. 2A is a time diagram of signal characteristics in a bus interface in other devices. The time offset between signals Out 1 , Out 2 at the respective outputs of the bus interface is clearly visible; center voltage UM has high peaks accordingly. Furthermore, the voltage range of two output voltages Out 1 and Out 2 is different.

FIG. 2B illustrates time characteristics of the signals described here on the bus interface according to the exemplary embodiment of the present invention. Driver circuit 2 , 20 , 21 , which is configured as a regulator, regulates center voltage UM at a constant U/2; there is no time offset between the two output voltages Out 1 and Out 2 , and both output voltages Out 1 and Out 2 have the same voltage range.

According to the method of coupling a bus device to a bus having a pair of complementary bus lines H, L, the bus device is connected to input In 1 of a first driver circuit 1 , 10 , 11 and output Out 1 of first driver circuit 1 , 10 , 11 is connected to first bus line H of the pair of complementary bus lines. Output Out 2 of the second driver circuit which is complementary to first driver circuit 1 , 10 , 11 is connected to second bus line L of the pair of complementary bus lines H, L, input In 2 of second driver circuit 2 , 20 , 21 being connected to output Out 1 of first driver circuit 1 , 10 , 11 such that input In 2 of second driver circuit 2 , 20 , 21 is connected to output Out 1 of first driver circuit 1 , 10 , 11 via center tapping point UM of a voltage divider 3 , 4 which is connected between the two outputs Out 1 , Out 2 of the two driver circuits 1 , 10 , 11 ; 2 , 20 , 21 .