Power switching device

The invention relates to a power switching device having a power switching transistor connected in series in a load circuit with an inductive load portion, and having a commutation circuit, which is connected in parallel with the gate-drain or base-collector path of the transistor and has at least one Zener diode, which diode determines the clamping voltage of the power switching transistor during commutation, and a normal diode connected in series and in a manner oppositely biased with respect to the Zener diode.

Typical areas of application for power switching devices are, inter alia, synchronous rectifiers and switching regulators. In this case, such power switching devices, which have either a bipolar power switching transistor or a field-effect power switching transistor, are realized either in a so-called low-side configuration, where the power switching device is located on the side of the load with lower potential, or in a so-called high-side configuration, in which the power switching device is located on the side of the load with higher potential.

The increased integration density in integrated circuits leads, in MOS power field-effect transistors as well, to smaller chip areas for the same on resistance. This results, inter alia, in a reduction of the maximum energy strength during the commutation operation in load circuits with inductive loads.

The accompanying FIGS. 4 to 6 illustrate the prior art of power switching devices respectively on the basis of a low-side configuration and a high-side configuration. The power switching transistor T 1 , by way of example, is an NMOS field-effect transistor in this case. The power switching transistor T 1 is connected in series with an inductive load L 1 in a load circuit, to be precise in a low-side configuration in FIG. 4 and in a high-side configuration in FIG. 5. A current IL 1 flows between a supply voltage V bb and ground in the switched-on state of the power switching transistor T 1 . The current leads to a voltage U L1 across the load L 1 . The voltage is shown in FIG. 6 . The series circuit which comprises a Zener diode D 1 and a normal diode D 2 connected in a manner oppositely biased with respect thereto and is connected in parallel with the gate-drain diode of the power switching transistor T 1 forms a commutation circuit, wherein the Zener diode D 1 determines a clamping voltage U KL (FIG. 6 ), at which the transistor T 1 is turned on during commutation. The Zener value of the Zener diode D 1 is determined by the maximum operating voltage at V bb at which the transistor T 1 is permitted not to be turned on. In the switched-on state, the diode D 2 ensures that the gate-drain diode path is blocked. The commutation energy converted during the switch-off of the inductive load L 1 in the power switching transistor T 1 results from the value of the load current I L1 integrated over time multiplied by the voltage drop across the power switching transistor T 1 . This commutation energy leads to the heating of the power switching transistor T 1 , the maximum possible energy value resulting from the maximum possible destruction temperature of the power switching transistor T 1 and the absolute material volume (of the power switching transistor) in which the energy is converted.

It is accordingly an object of the invention to provide a power switching device, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows the commutation energy to be increased for a given chip area of the power switching transistor.

With the foregoing and other objects in view there is provided, in accordance with the invention, a power switching device, comprising:

a power switching transistor connected in series in a load circuit with an inductive load portion, the transistor having a gate-drain path or a base-collector path;

a commutation circuit connected in parallel with the gate-drain path or base-collector path of the transistor, the commutation circuit having:

at least one Zener diode determining a commutation clamping voltage for switching on the power switching transistor during a commutation; a normal diode connected in series with and oppositely biased with respect to the Zener diode; control elements for reducing, during a short time, the commutation clamping voltage at a beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle.

The principle according to the invention which achieves this object is based on the concept of dynamically varying the commutation voltage during the commutation operation by means of special circuitry.

In order to implement this concept, the commutation circuit of the power switching device according to the invention has control elements in order to reduce the commutation clamping voltage at the beginning of each commutation cycle or after an adjustable delay from the beginning of each commutation cycle, during a short time. The power converted in the power switching transistor is thus distributed over a longer time period, without the static commutation voltage being varied. This leads, at the first instant of commutation, to a lower power in the power switching transistor, as a result of which the temperature increase thereof is smaller. As a result, the energy can be better dissipated via the material.

In accordance with an added feature of the invention, the control elements of the commutation circuit comprise a second Zener diode, which is connected with a bias in the same direction as the first Zener diode and in series with the latter, and also a control transistor, which is connected in parallel with the second Zener diode and is turned on by a control pulse for the short time and, in the process, bridges the second Zener diode in low-impedance fashion. The Zener values of the two Zener diodes again determine, in total, the static Zener value crucial for the clamping voltage.

As already mentioned, the power switching transistor may be an NMOS field-effect transistor, for example. The control transistor may then be embodied as a PMOS field-effect transistor. As an alternative, the power switching transistor may also be a bipolar transistor, e.g. an IGBT.

In accordance with a cocomitant feature of the invention, the novel power switching device is either provided in a low side configuration, connected on a low-potential side of the load, or as a high side configuration, connected on a high-potential side of the load.

Other features which are considered as characteristic for the invention are set forth in the appended claims.

Although the invention is illustrated and described herein as embodied in a power switching device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.

FIG. 1 is a circuit diagram of a first exemplary embodiment of a power switching device according to the invention in a low-side configuration;

FIG. 2 is a circuit diagram of a second exemplary embodiment of the power switching device according to the invention in a high-side configuration;

FIG. 3 is a pulse timing diagram illustrating a first method of operation of the power switching devices according to the invention as illustrated in FIGS. 1 and 2 ;

FIG. 3A is a pulse timing diagram illustrating a second method of operation of the power switching devices illustrated in FIGS. 1 and 2 ;

FIG. 4 is a circuit diagram of a prior art power switching device in a low-side configuration (discussed in the introductory text);

FIG. 5 is a circuit diagram of a prior art power switching device in a high-side configuration (discussed in the introductory text); and

FIG. 6 is a pulse timing diagram illustrating the method of operation of the prior art power switching devices of FIGS. 4 and 5 .

Referring now once more to the figures of the drawing in detail and first, particularly, to FIGS. 1 and 2 thereof, there are shown two exemplary embodiments 1 and 1A of a power switching device according to the invention. They are respectively arranged in a low-side configuration and in a high-side configuration.

Elements and voltage and current values identical to those already used in FIGS. 4 to 6 , which describe the conventional power switching devices, have identical designations in FIGS. 1 to 3 . In both configurations illustrated in FIGS. 1 and 2 , the power switching transistor T 1 is an NMOS field-effect transistor, by way of example. The power switching device in FIG. 1 is designated generally by 1 and the power switching device in FIG. 2 is designated generally by 1 A. The commutation circuit used for both exemplary embodiments 1 and 1A of the power switching device is the same in each case. The Zener diode D 1 of the commutation circuit in accordance with FIGS. 4 and 5 is replaced in the exemplary embodiments 1 and 1A according to the invention by a series circuit of two Zener diodes D 1a and D 1b , which are connected in a manner biased the same and whose Zener values in total again define the static Zener value in accordance with FIGS. 4 and 5 and thus the clamping voltage required for switching on the power transistor during commutation. A control transistor T 2 is connected in parallel with the second Zener diode D 1a . The control transistor T 2 is realized as a PMOS field-effect transistor in the exemplary embodiments 1 and 1A. A momentary control pulse U ST is applied to the gate-source diode of the control transistor T 2 , which pulse, in accordance with FIG. 3 , directly follows the trailing edge of the input voltage U IN for the power switching transistor T 1 , that is to say comes directly at the beginning of the commutation cycle T ab . In accordance with FIG. 3A , the control pulse U ST is applied to the gate-source diode of the control transistor T 2 after an adjustable delay time T z following the trailing edge of the input voltage U IN . The pulse width of the control voltage U ST determines the short time T k during which the commutation voltage U KL is reduced by the Zener voltage U D1a across the second Zener diode D 1a . As a result, the temperature increase in the power switching transistor T 1 is smaller in this short time T k of the commutation cycle T ab , so that the energy can be better dissipated via the body of said transistor. During the short time T k , the control transistor T 2 bridges the second Zener diode D 1a in low-impedance fashion, so that, as represented in FIGS. 3 and 3 a , the energy stored in the inductive load L 1 , represented by the current I L1 , is distributed over a larger time period. This means that the steepness of the trailing edge of I L1 is smaller during the short time period T k than during the rest of the time.

The method of operation illustrated with reference to FIG. 3A , in which the commutation clamping voltage U KL is reduced only after the adjustable delay time T z after the trailing edge of the input voltage U IN for the short time period T K , results in another increase in the maximum commutation energy, since a high proportional energy is reduced at the start in the first time T z by virtue of the high commutation voltage. Only in the subsequent time period T K is the commutation protracted temporally.

It remains to be mentioned that the elements of the commutation circuit shown in FIGS. 1 and 2 , namely the additional diode D 1a and the control transistor T 2 , can easily be integrated in a space-saving manner in a chip of the power switching device together with the power switching transistor T 1 . Instead of using a field-effect transistor, for example an NMOS field-effect transistor as in FIGS. 1 and 2 , for the power switching transistor T 1 , it is also possible, without departing from the principle of the invention, to use a bipolar transistor. This is similarly true for the control transistor T 2 , such modifications and their varied parameter values being familiar to those of ordinary skill in the pertinent art.