System for selecting another processor to be the boot strap processor when the default boot strap processor does not have local memory

1. Field of the Invention

The present invention generally relates to the selection of a boot strap processor in a multi-processor environment.

2. Background Information

Some computer systems include more than one processor and each processor may have its own local memory. In multi-processor systems, typically, one of the processors comprises the “boot strap processor” (“BSP”). The BSP may be responsible for, among other activities, various initialization activities such as initializing input/output (“I/O”) subsystems, initializing user interfaces, and causing the operating system to be loaded on the various processors in the system. To perform the activities of a BSP, the BSP generally requires access to memory. If memory is not installed for the BSP, the system may fail to initialize correctly and/or may “crash.”

In accordance with at least some embodiments, a plurality of processors are coupled together. One of the processors may comprise a default boot strap processor (“BSP”). Further, the default BSP may determine whether the BSP has local memory and becomes the BSP for the system if the default BSP has local memory, or selects another processor to be the BSP for the system if the default BSP does not have local memory.

For a detailed description of the exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:

FIG. 1 shows an exemplary system having four processors in which one of the processors is a default boot strap processor and the boot strap processor includes local memory;

FIG. 2 shows an exemplary system in which the boot strap processor does not have local memory; and

FIG. 3 shows a flowchart of a process for selecting a boot strap processor in accordance with various embodiments of the invention.

Certain terms are used throughout the following description to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ”. Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.

Referring now to FIG. 1 , an electronic system 100 may comprise a plurality of processors 102 , 104 , 106 , and 108 . The system 100 may be representative of a wide variety of systems, such as, without limitation, a computer. Although four processors 102 – 108 are shown in the exemplary embodiment of FIG. 1 , in general, any number of processors may be included in the system. Each processor may have local memory 103 – 109 as shown associated with that processor. Thus, processor 102 may have memory 103 , while processors 104 , 106 and 108 may have local memory 105 , 107 , and 109 , respectively. Each memory 103 – 109 may be of the same or different capacity than the other memories. Other devices (not specifically shown) may be included as well and coupled to one or more of the processors and may include, without limitation, one or more input/output (“I/O”) devices such as a keyboard, mouse, display, network interface controller.

As shown in FIG. 1 , one of the processors 102 – 108 may be designated the default BSP (processor 108 ). This designation may be based on the location of the processors within the system. For example, the BSP may be whichever processor is electrically connected or coupled to the system's bridge device (e.g., “south” bridge), if such a device is included in the system. If, in fact, the default BSP (regardless how the default BSP is determined or selected) has its own local memory, then that processor may be permitted to function as the default BSP for the system.

FIG. 2 shows system 100 in which the default BSP 108 does not have any local memory 109 , as indicated by the dashed box around memory 109 . In this situation, another processor 102 – 106 may be selected to function as the BSP for the system. In some embodiments, of the remaining processors 102 – 106 that have local memory, the processor 102 , 104 , 106 that has the largest complement of local memory 103 , 105 , 107 may be selected to be the BSP.

FIG. 3 provides an example of this process for selecting a BSP. As shown in FIG. 3 , process 200 includes blocks 202 – 208 . In decision block 202 , it is determined whether memory is installed on the default BSP. This determination can be readily made by the default BSP 108 itself. If the default BSP has local memory, then that processor is used as the BSP in block 204 . If, however, the default BSP does not have local memory, then it may be determined which of the other processors in the system have local memory (block 206 ). In block 208 , the processor that has the largest memory capacity may be selected as the BSP.

Blocks 206 and 208 may be implemented in a variety of ways. In some embodiments, the default BSP may interrogate individually each of the other processors in the system for information regarding their local memory. In response, each processor may report whether it has local memory and, if so, how much local memory is present. The default BSP may use that information to select as the BSP for the system the processor that reports the largest amount of memory. In other embodiments, each processor in the system may determine whether it has local memory and, if so, the quantity of local memory without being prompted for such information by the default BSP. The results of each processor determining its own local memory may be related to the default BSP via any of a variety of techniques such as by setting flags indicative of the amount of local memory. Rather than individually prompting each processor to determine and report its local memory, the default BSP may read and process the flags.

In other embodiments of the invention, even if the default BSP 108 includes local memory, the processor 102 – 108 with the most local memory 103 – 109 in the system may be used as the default BSP. The default BSP may be used as the BSP if it has more memory than the other processors in the system, or may select another processor that has the most local memory to be the BSP.

In at least some situations, it may be possible for two or more processors to have an equal amount of memory that is larger than all other processors in the system. In this situation, as between the two or more processors having the most local memory in the system, a processor is selected to be the BSP that comports with any one of a variety of suitable criteria. For instance, each processor may be assigned a unique numerical or alphanumerical identifier (e.g., serial number) and the processor with identifier that ranks above the other processors may be selected as the BSP. The ranking may be based on the size of the identifier such that the largest, or smallest, identifier is selected as the BSP. The ranking may be based on examining a portion of the identifier and ranking them according to size. Further still, a mathematical formula or algorithm may be applied to the unique identifiers to generate another sortable value that is then used to select a BSP. Numerous other criteria may be implemented as well.

The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.