Integrated circuit anti-interference outline structure

(a) Field of the Invention

The invention relates to an integrated circuit anti-interference outline structure, and more particularly, to an anti-interference outline suitable for disposing within an integrated circuit; wherein two metal strips provided at the surface of the integrated circuit are applied with a positive voltage and connected to GND, respectively, so as to generate a significant parasitic capacitance at poly layers thereof in between, and to further control noises thereof within acceptable ranges; and a P-type substrate therein is provided with a deep N-well for connecting with an N-terminal of an N-well layer, so as to produce a positive voltage zone having a large area such that noises are disallowed to pass through and are instead overflowed through a ground terminal having a lower voltage, thereby shielding the integrated circuit from invasions and leaks of electromagnetic waves.

(b) Description of the Prior Art

Accompanied with advancement of technology, products that we use become better in quality and precision, and therefore it is essential that the integrated circuits contained therein have more exact designs. However, in the internal design of an integrated circuit, the structure therein is made up of electronic circuit layouts, and some noises that interfere with one another are inevitably produced. The phenomenon occurs even more frequently in an integrated circuit for that the integrated circuit is consisted of a great quantity of circuits, and hence it is important to minimize the interference signals. In a prior art, housing shielding and aperture shielding are generally used in combination for screening external noise interferences. However, such method is incapable of entirely eliminating external noise interferences, and only succeeds in isolating external noises but fails to isolate noise interferences at the interior thereof. Also, the internal structure of a prior integrated circuit lacks countermeasures and designs for resolving the aforesaid difficulty; and as closer the circuits in the integrated circuit get with one another, the more likely the noises generated will stray along the circuits, thus seriously affecting stability and quality of the integrated circuit.

In the view of the above shortcomings, the inventor has a patent application Ser. No. 10/189,495, “Domestic Priority Data as Claimed by Applicant”, wherein an integrated circuit anti-interference outline structure is provided for solving external and internal noise interferences, and two metal strips and PNP structures of varied amounts are employed to produce parasitic capacitance for isolating external noises, thereby forcing the internal noise currents to overflow through a ground terminal using a positive voltage zone produced, as well as preventing invasions of external noises and interferences of internal noises.

The object of the invention is to provide an integrated circuit anti-interference outline structure that surrounds a periphery of a partial circuit within an integrated circuit and comprises of a plurality of PNP structures. Wherein, two metal strips are connected to a metal layer and a surface layer of the integrated circuit for providing a positive voltage and a ground terminal, so that a parasitic capacitance is generated at poly layers therein for controlling noises thereof within acceptable ranges, and thereby elevating anti-interference effects against high frequency electromagnetic waves. In addition, a positive voltage zone having a large area is produced by connecting a deep N-well layer to an N-terminal of an N-well layer, so as to have noise currents overflow from the ground terminal and to further shield the integrated circuit from invasions and leaks of electromagnetic waves.

The other object of the invention is to provide an integrated circuit anti-interference outline structure that is formed according to internal circuits of the integrated circuit, and a length thereof is determined based upon the area required for anti-interference of the internal circuits, thus enhancing the anti-interference effects of the integrated circuit per inner unit area. Furthermore, the invention is provided specifically for generating anti-interference effects against electromagnetic waves by combining within CMOS integrated circuits for further utilization.

FIG. 1 shows a schematic view of the integrated circuit anti-interference outline structure according to the invention being combined with an integrated circuit.

FIG. 2 shows a top view of the integrated circuit anti-interference outline structure according to the invention.

FIG. 3 shows an exploded elevational view of the integrated circuit anti-interference outline structure according to the invention.

FIG. 4 shows a partial enlarged view of the labeled part of the integrated circuit anti-interference outline structure according to the invention illustrated in FIG. 3 .

FIG. 5 shows an enlarged sectional view of the integrated circuit anti-interference outline structure according to the invention.

Referring to FIG. 1 showing the integrated circuit anti-interference outline structure C according to the invention surrounding the periphery of a partial circuit B within an integrated circuit A, the partial circuit B is protected from interference and is a partial circuit C, wherein the integrated circuit anti-interference outline structure C may be laid-out along with the partial circuit B within the integrated circuit A.

Also referring to FIGS. 2 , 3 and 4 showing a top schematic view, an exploded elevational schematic view and an enlarged partial view of the labeled part in FIG. 3 , respectively, the integrated circuit anti-interference outline structure C according to the invention comprises a plurality of PNP structures 10 , a plurality of poly layers 92 , a P+ layer 91 ′, an N− layer 91 , a plurality of pairs of metal layers 50 and 50 ′, a Vcc metal strip 60 , a GND metal strip 60 ′, and a plurality of contact holes 911 , 911 ′, 921 , 61 and 61 ′. On top of a P-substrate layer 70 is formed with a deep N-well layer 80 that is further formed with an N-well layer 90 on the top thereof. The N-well layer 90 is provided with the positive-valence P+ layer 90 ′, the negative-valence N− layer 90 , and the poly layers 92 ; which are connected to the metal layer 50 (metal 1 ) and the deep N-well layer 80 using the contact holes 911 disposed at the negative-valence N− layer 90 , respectively, then are connected to the metal layer 50 using the contact holes 911 ′ disposed at the positive-covalence P+ layer 91 ′, and are further connected to the Vcc metal strip 60 (metal 2 ) using the contact holes 61 , and is applied with a positive voltage to form a source S and a drain D.

The poly layers 92 are disposed with contact holes 921 for connecting with the metal layer 50 ′, and are connected to the GND metal strip 60 ′ using the contact holes 61 ′ to form a gate G of the GND terminal. From the above, and referring to FIG. 5 , the Vcc metal strip 60 and the GND metal strip 60 ′ are able to provide operating powers required by the positive-valence P+ layer 91 ′ and the negative-valence N− layer 91 of the aforesaid PNP structures 10 by connecting to positive and negative pins of the power of the integrated circuit, respectively. Also, the Vcc metal strip 60 is provided with a plurality of contact holes 61 at the bottom thereof for connecting to the aforesaid metal layer 50 , so that the positive terminal of the power is induced into the metal layer 50 .

Furthermore, at the bottom of the GND metal strip 60 ′ is provided with a plurality of contact holes 61 ′ that connect another metal layer 50 ′ for inducing the negative terminal of the power to the metal layer 50 ′. By inducing the positive and negative terminals of the power into the metal layers 50 and 50 ′, the aforesaid PNP structures 10 , the positive-valence P+ layer 91 ′ and the negative-valence N− layer 91 become operable. That is, a supply from the positive terminal of the power is acquired by the source and drain represented by the positive-valence P+ layer 91 ′ and the negative-valence N− layer 91 , and the negative terminal of the power is induced into the poly layers 92 , thereby preventing invasion of electromagnetic waves. However, the unit area for the parasitic capacitance and anti-interference, and the magnitude of power supply for anti-interference are not limited to fixed numbers, but may be adjusted appropriately according the layout volumes and areas of the PNP structures 10 , the poly layers 20 , the positive-valence P+ layer 91 ′, the negative-valence N− layer 91 , the metal layers 50 and 50 ′, and the Vcc and GND metal layers 60 and 60 ′.

It is of course to be understood that the embodiment described herein is merely illustrative of the principles of the invention and that a wide variety of modifications thereto may be effected by persons skilled in the art without departing from the spirit and scope of the invention as set forth in the following claims.