Static random access memory system with compensating-circuit for bitline leakage

1. Field of the Invention

The present invention relates generally to a static random access memory(SRAM)system, and more particularly to a static random access memory system with a compensating-circuit.

2. Description of the Prior Art

As semiconductor devices, such as the Metal-Oxide-Semiconductor device, become highly integrated the area occupied by the device shrinks, as well as the design rule. With advances in the semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks in the deep sub-micron region, some problems described below are incurred due to the scaling down process. To meet customer demand for small size and low power products, manufacturers are producing newer integrated circuits (ICs) that operate with lower supply voltages and that include smaller internal sub-circuits. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include one or more SRAM cells for data storage. SRAMs cells are popular because they operate at a higher speed than dynamic random-access-memory (DRAM) cells, and as long as they are powered, they can store data indefinitely, unlike DRAM cells, which must be periodically refreshed.

Static random access memory (SRAM) cells typically provide memory storage for bits that can be rapidly read from and written to. Conventional structure of Static random access memory (SRAM) cell is a six-transistors SRAM cell, which means six transistors are used to form a SRAM cell. In general, advantages of six-transistors SRAM cell at least include high speed and possibility of low supply voltage. By unfortunately, one unavoidable disadvantage is that area of six-transistor SRAM cell is large, and the disadvantage is more serious and it is desired to overcome the disadvantage by either improving structure of six-transistors SRAM cell or providing a new SRAM cell. Therefore, four-transistors SRAM is present to replace the conventional six-transistors SRAM cell. Clearly, owing to number of used transistor is decreased, occupied area of four-transistors SRAM cell is less than six-transistors SRAM cell. Thus, four-transistors SRAM cell is more suitable for ICs whenever sizes of ICs are reduced, even four-transistors also meets some disadvantages such as higher off-state leakage current of PMOS. More introduction of four-transistors SRAM cell can be acquired by referring to IEEE IEDM 98-643 to IEDM 98-646, U.S. Pat. No. 5,943,269, U.S. Pat. No. 6,091,628, U.S. Pat. No. 6,044,011, U.S. Pat. No. 6,011,726, U.S. Pat. No. 5,751,044.

In a typical SRAM cell having six field effect transistors (FET transistors), there are a first inverter formed by two of the FET transistors and a second inverter formed by other two of the FET transistors between power and ground terminals. The first and second inverters are cross-coupled such that at a first storage node, the output of the second inverter is tied to the input of the first inverter, and at a second storage node, the output of the first inverter is tied to the input of the second inverter. The first and second cross-coupled inverters form latched wherein one of the storage nodes is pulled low and the other storage node is pulled high. The other two of the six transistors are pass FET transistors controlled by a wordline signal on a wordline conductor. One of the pass transistors is coupled between a bitline and the first storage node. The other pass transistor is coupled between a bitline# and the second storage node. With the pass transistors off, the first and second storage nodes are insulated from the bitline and bitline#, although there may be some leakage.

In a reading procedure, data and data# signals are precharged high on the bitline and bitline#, respectively. When the wordline is asserted, one of the storage nodes is low and the other is high. The low storage node begins to pull either the data or data# signal low depending on the state of the memory cell. A sense amplifier senses a difference between the data and data# signals and accelerates the fall of whichever of the data or data# signals corresponds to the low storage node until the storage node is low. The high storage node remains high and the sense amplifier may pin the storage node high through the data or data# signal (depending on the state of the memory cell). Accordingly, the reading procedure causes the storage nodes to remain at the same logic states after the wordline signal is de-asserted. The sense amplifier provides a signal indicative of the state.

In a writing procedure, circuitry in a sense amplifier causes one of the data or data# signals to be high and the other to be low in response to whether a high or low value has been written into a write buffer. When the wordline signal is asserted, if the current state of the first and second storage nodes is the same as that of the data and data# signals, the first and second storage nodes remains the same. If the current state of the first and second storage nodes is different than that of the data and data# signals, one of the storage nodes is pulled down while the other storage node is pulled up. When the states of the first and second storage nodes in the latch formed of the two cross-coupled inverters changes, the latch is said to flip states. Unlike dynamic random access memory (DRAM) cells, SRAM cells are not required to be refreshed to maintain their state. Rather, as long as the power is supplied to the power terminal and absent leakage, the voltage states of the first and second storage nodes are stable in the latch of the cross-coupled inverters.

As CMOS process technology progresses, the increasing leakage current is becoming critical and acts as a noise source for sense amplifier of memory. In the conventional SRAM, the increased bitline leakage current will induce read/write incorrect operation. The conventional SRAM leakage problem is shown below FIG. 1 , memory system 100 includes a column 120 with a plurality of memory cells 110 , wherein the column 120 is formed by a plurality of memory cells 110 coupled with a first bitline 130 A and a second bitline 130 B; a Bitline conditioning circuit 140 is coupled with the first bitline 130 A and the second bitline 130 B to precharge the first bitline 130 A and the second, bitline 130 B, individually; each memory cell 110 is coupled with a wordline 150 and each wordline 150 is also coupled with the first bitline 130 A and the second bitline 130 B, individually. As shown in FIG. 1 , it schematically illustrates a first state V 1 and a second state V 2 of each memory cell 110 in the column 120 .

First of all, the Bitline conditioning circuit 140 performs a pre-charge operation to make the first state V 1 becomes one (V 1 =1) and the second state V 2 becomes zero(V 2 =0)of every memory cell 110 , that is, the first state is higher than the second state of every memory cell 110 . If the first wordline 150 A is selected to perform a read/write procedure and other wordlines 150 are not selected, the first wordline 150 A will be ON to make the first state V 1 become zero (V 1 =0) and the second state V 2 become one (V 2 =1) in the first memory cell 110 A, but the first state V 1 becomes one (V 1 =1) and the second state V 2 becomes zero (V 2 =0) in other memory cells 110 , that is, in which for the first memory cell 110 A, the first state V 1 is lower and the second state V 2 is higher, but for other memory cells 110 , the first state V 1 is higher and the second state V 2 is lower. It will result in leakage with respect to the second bitline 130 B and the second state V 2 of all memory cells 110 will tend to balance. If amount of the memory cells 110 in the column 120 is larger more and more, the second state V 2 of the first memory cell 110 A will be becoming lower due to the leakage issue, and further, the leakage of the second bitline 130 B on the first memory cell 110 A is increased as time. When a normal access (read/write) operation happens, the second state V 2 of the first memory cell 110 A will be becoming “0” from “1” due to the leakage issue, and hence, that will be erroneous judgement to form “error”.

To keep leakage low, the threshold voltages have to be kept relatively high in the conventional SRAM process, and the threshold voltages of transistors of the memory cells may be higher than for transistors of other portions of the integrated circuits containing the memory cells. However, keeping the threshold voltage high also decreases the switching speed and effects cache performance thereof. For forming the SRAM process, this method that utilizes adjusting the threshold voltage in the SRAM process is difficult to be performed, and it also increases the process costs. In accordance with the above description, a new and improved method and the structure thereof for preventing the leakage in SRAM is therefore necessary in the deep sub-micron technology of semiconductors, so as to raise the performance of SRAM.

In accordance with the present invention, a method is provided that substantially overcomes the drawbacks of the above mentioned problems to avoid bitline leakage in SRAM.

Accordingly, it is one of objects in the present invention to provide a compensation circuit to compensate the bitlines leakage of SRAM. This invention can utilize a compensation circuit coupled with the SRAM to self-compensate bitlines leakage issue caused during read/write operation. Furthermore, the present invention can solve the issue of error judgment that is caused by voltage decay of bitlines resulted from this leakage problem of SRAM by a circuitry point of view, and thus it need not modify any special requirement in the process for forming the SRAM due to this circuitry point of view. Therefore, this invention can reduce the costs of the conventional process and hence correspond to economic effect.

Another object of the present invention is to provide a SRAM system with a compensation circuit for detecting the differential voltage level of bitlines by itself and compensate the leakage thereof. This invention couples a compensation circuit schemed by cross-coupling with a pair of symmetric sub-circuits with the SRAM, so as to detect the differential voltage level of bitlines by itself and compensate the voltage of bitlines immediately. When the abnormal voltage level of bitlines is detected, and one of the symmetric sub-circuits in the compensation circuit compensates to Vcc immediately.

Another object of the present invention is to provide a SRAM system with a compensation circuit. This invention utilizes a pair of complemental signals to simultaneously communicate the compensation circuit and the memory circuit coupled with that, so as to control the interaction between the compensation circuit and the memory circuit by way of the complemental signals. Furthermore, this invention also utilizes the pair of complemental signals to perform a new operational procedure of SRAM system, comprises: a pre-charge procedure, an access procedure and a compensating procedure.

In accordance with the purposes of the present invention, a new static random access memory system with a compensation circuit for bitlines leakage is disclosed. The memory system comprises a plurality of memory cells that are arranged for forming a column, and the plurality of memory cells are coupled with a first bitline and a second bitline individually; and further, the same bitline is located on the same side of the plurality of memory cells. Additionally, the memory system further comprises a bitline conditioning circuit that is coupled with the first bitline and the second bitline individually, so as to perform the pre-charge procedure thereof; and that comprises a plurality of wordlines, wherein each wordline is coupled with the first bitline and the second bitline individually. Furthermore, the memory system further comprises a compensating-circuit that is individually coupled with the first bitline and the second bitline between the first memory cell and the bitline conditioning circuit to keep the voltage that is requirement for the access procedure, wherein the bitline conditioning circuit and the compensating-circuit couple to receive a pair of complemental signals so as to control the interaction between the pre-charge procedure and the compensation procedure from each other.

First of all, a first complemental signal couples to enable to proceed with the pre-charge procedure so that the first state is higher than the second state in all memory cells, wherein a second complemental signal simultaneously coupled to disable to the compensating-circuit. If the first wordline belonged to the first memory cell is selected to proceed with the access procedure and other wordlines are not selected, the first wordline will be ON to make the first state to be lower than the second state in the first memory cell for performing the access procedure of the first memory cell, in which for the other memory cells, the first state is higher than the second state. The first complemental signal is coupled to enable the compensating-circuit so as to proceed with a compensation procedure during the access procedure of the first memory cell, and the second complemental signal is simultaneously coupled to disable to the bitline conditioning circuit, wherein the compensating-circuit is ON by itself to keep the second state of the first memory cell is higher than that of others, whereby the problems resulted from leakages of SRAM during the access procedure is avoided.

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 shows a circuitry of the conventional static random access memory (SRAM) system without compensating-circuit;

FIG. 2 shows a circuitry of the memory system that can keep Vcc for operating memory cell in accordance with the first embodiment of the present invention;

FIG. 3 shows a circuitry of the memory system that can keep Vcc needed during the access procedure in accordance with the second embodiment of the present invention;

FIG. 4 shows a circuitry of the static random access memory system that can compensate the voltages of the bitlines by itself in accordance with the third embodiment of the present invention;

FIG. 5 shows a circuitry of the static random access memory system with a compensating-circuit in accordance with the fourth embodiment of the present invention; and

FIG. 6 shows a circuitry of the static random access memory system with a compensating-circuit in accordance with the fifth embodiment of the present invention.

These preferred embodiments of the present invention are now described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.

As illustrated in FIG. 2 , in the first embodiment of the present invention, first of all, a memory system 200 is provided. The memory system 200 comprises: a memory cell region 210 that are coupled with at least one bitline region 220 ; a first sub-circuit 230 that is coupled with at least one bitline region 220 ; a second sub-circuit 240 that is coupled with at least one bitline region 220 , wherein the first sub-circuit 230 and the second sub-circuit 240 can keep Vcc that is necessary for operating the memory cell region 210 by coupling to proceed with the interaction; and further, the interaction is that the second sub-circuit 240 is enabled when the first sub-circuit 230 is disabled, and the second sub-circuit 240 is disabled when the first sub-circuit 230 is enabled.

Referring to FIG. 2 , in this embodiment, the operation of the memory system 200 is described as followings: first of all, the memory system 200 is coupled to enable the first sub-circuit 230 and simultaneously disable the second sub-circuit 240 so as to perform a pre-charge procedure, whereby the first sub-circuit 230 drives at least one bitline region 220 to make the memory cell region 210 to attain Vcc; After the memory cell region 210 attains Vcc, the memory system 200 is coupled to disable the first sub-circuit 230 to proceed with an access procedure, and the memory system 200 is coupled to enable the second sub-circuit 240 to proceed with a compensation procedure, wherein the memory system 200 can control the pre-charge procedure and the compensation procedure by the interaction between the first sub-circuit 230 and the second sub-circuit 240 . When Vcc of the memory cell region 210 is not enough to operate due to the leakage, the second sub-circuit 240 drives at least one bitline region 220 via the compensation procedure so as to keep Vcc for operating the memory cell region 210 .

As illustrated in FIG. 3 , in the second embodiment of the present invention, first of all, a memory system 300 is provided. The memory system 300 comprises: a first sub-circuit 310 , a first signal 320 A is coupled to enable the first sub-circuit 310 and a second signal 320 B is coupled to disable the first sub-circuit 310 , wherein the first signal 320 A and the second signal 320 B pair to form complemental signals from each other that the first signal 320 A is ON and the second signal 320 B is OFF; a second sub-circuit 330 , the first signal 320 A is coupled to enable the second sub-circuit 330 when the second signal 320 B is coupled to disable the first sub-circuit 310 , and the second signal 320 B is coupled to disable the second sub-circuit 330 when the first signal 320 A is coupled to enable the first sub-circuit 310 , wherein the first signal 320 A and the second signal 320 B are simultaneously communicated with the first sub-circuit 310 and the second sub-circuit 330 , individually, so as to perform a interaction between the first sub-circuit 310 and the second sub-circuit 330 , that is, when the first signal 320 A is coupled to enable the first sub-circuit 310 , the second signal 320 B is coupled to disable the second sub-circuit 330 ; and further, when the second signal 320 B is coupled to disable the first sub-circuit 310 , the first signal 320 A is coupled to enable the second sub-circuit 330 ; a third sub-circuit 340 , the third circuit 340 is individually coupled with the first sub-circuit 310 and the second sub-circuit 330 , wherein the third sub-circuit 340 can keep Vcc for operating that via the interaction between the first sub-circuit 310 and the second sub-circuit 330 .

Referring to FIG. 3 , in this embodiment, the operation of the memory system 300 is described as followings: first of all, the memory system 300 is coupled to enable the first sub-circuit 310 by the first signal 320 A to proceed with a pre-charge procedure and simultaneously disable the second sub-circuit 330 by the second signal 320 B, so as to make the third sub-circuit 340 to Vcc. After the third sub-circuit 340 attains Vcc, the memory system 300 is coupled to disable the first sub-circuit 310 by the second signal 320 B to proceed with an access procedure, and the memory system 300 is coupled to enable the second sub-circuit 330 by the first signal 320 A to proceed with a compensation procedure, wherein the memory system 300 can control the pre-charge procedure and the compensation procedure by the interaction between the first sub-circuit 310 and the second sub-circuit 330 . When Vcc of the third sub-circuit 340 is not enough to operate due to the leakage, the memory system 300 drives the second sub-circuit 330 via the compensation procedure so as to keep Vcc for operating the third sub-circuit 340 .

As illustrated in FIG. 4 , in the third embodiment of the present invention, first of all, a static random access memory system 400 is provided. The static random access memory system 400 comprises: a memory cell region 410 that is individually coupled with a first bitline 420 A and a second bitline 420 B; a first sub-circuit 430 that is individually coupled with the first bitline 420 A and the second bitline 420 B to control these bitlines 420 A/ 420 B; a second sub-circuit 440 that is individually coupled with the first bitline 420 A and the second bitline 420 B between the memory cell region 410 and the first sub-circuit 430 , wherein the second sub-circuit 440 consists of a first symmetric sub-circuit 440 A and a second symmetric sub-circuit 440 B, which are cross-coupled from each other, and each symmetric sub-circuit 440 A/ 440 B is coupled with each bitline 420 A/ 420 B between the memory cell region 410 and the first sub-circuit 430 , individually. Furthermore, the second sub-circuit 440 can detect the differential voltage level between the bitlines 420 A/ 420 B by itself due to cross-couple scheme of the first symmetric sub-circuit 440 A and the second symmetric sub-circuit 440 B so as to compensate to Vcc of bitlines 420 A/ 420 B immediately. Moreover, each symmetric sub-circuit 440 A/ 440 B further comprises a plurality of MOSs, such as PMOS or NMOS, and they 440 A/ 440 B are individually coupled with a power 450 (Vcc) and the ground terminals by using the MOSs.

Referring to FIG. 4 , in this embodiment, the first sub-circuit 430 and the second sub-circuit 440 individually and simultaneously communicate a pair of complemental signals 460 to perform a interaction, that is, when a first complemental signal 460 A is coupled to enable the first sub-circuit 430 , a second signal 460 B is coupled to disable the second sub-circuit 440 , and the memory cell region 410 attains to Vcc for operation; and further, when the second signal 460 B is coupled to disable the first sub-circuit 430 , the first signal 460 A is simultaneously coupled to enable the second sub-circuit 440 to keep Vcc for operating the memory cell region 410 .

Referring to FIG. 4 , in this embodiment, the operation of the static random access memory system 400 is described as followings: first of all, the static random access memory system 400 enables the first sub-circuit 430 by the first complemental signal 460 A to drive the bitlines 420 A/ 420 B and disable the second sub-circuit 440 by the second complemental signal 460 B, so as to perform a pre-charge procedure and attain Vcc for operating the memory cell region 410 . After the memory cell region 410 attains to Vcc, the static random access memory system 400 is coupled to disable the first sub-circuit 430 by the second complemental signal 460 B to proceed with an access procedure, and that system 400 is coupled to enable the second sub-circuit 440 by the first complemental signal 460 A to proceed with a compensation procedure, wherein that system 400 can control the pre-charge procedure and the compensation procedure by the interaction between the first sub-circuit 430 and the second sub-circuit 440 . The compensation procedure is described as followings: when the voltage level of the second bitline 420 B is abnormal, the first complemental signal 460 A is coupled to disable the first symmetric sub-circuit 440 A and enable the second symmetric sub-circuit 440 B to electrify the power 450 , so as to keep Vcc for operating the memory cell region 410 via the second bitline 420 B; on the contrary, when the voltage level of the first bitline 420 A is abnormal, the first complemental signal 460 A is coupled to disable the second symmetric sub-circuit 440 B and enable the first symmetric sub-circuit 440 A to electrify the power 450 , so as to keep Vcc for operating the memory cell region 410 via the first bitline 420 A.

As illustrated in FIG. 5 , in the fourth embodiment of the present invention, first of all, a static random access memory system 500 is provided. The static random access memory system 500 comprises: a memory cell region 520 having at least one memory column 510 , wherein at least one memory column 510 consists of a plurality memory cells 530 that are arranged in sequence therein; a first bitline 540 A and a second bitline 540 B that are individually coupled with the memory cells 530 of the memory column 510 , wherein the same bitline 540 A/ 540 B is coupled with the same side of the memory column 510 ; a plurality of wordlines 590 , wherein each wordline 590 is coupled with one of the memory cells 530 , the first bitline 540 A and the second bitline 540 B; a bitline conditioning circuit 550 that is coupled with the first bitline 540 A and the second bitline 540 B, individually; a compensating-circuit 560 that is coupled with the first bitline 540 A and the second bitline 540 B, individually, between the memory cell region 520 and the bitline conditioning circuit 550 ; a control sub-circuit 570 that is individually the bitline conditioning circuit 550 and the compensating-circuit 560 , the control sub-circuit 570 simultaneously communicates a pair of complemental signals to the bitline conditioning circuit 550 and the compensating-circuit 560 so as to control them 550 / 560 to perform a interaction thereof, wherein the pair of complemental signals include a first signal this is “ON” signal and a second signal that is “OFF” signal. The interaction is described as followings: when the control sub-circuit 570 communicates the first signal to enable the bitline conditioning circuit 550 and make the memory column 510 to Vcc for operation, the second signal is simultaneously communicated to disable the compensating-circuit 560 ; on the contrary, when the control sub-circuit 570 communicates the second signal to disable the bitline conditioning circuit 550 , the first signal is simultaneously communicated to enable the compensating-circuit 560 so as to keep Vcc for operating the memory cells 530 in the memory column 510 .

Referring to FIG. 5 , in this embodiment, the compensating-circuit 560 comprises: a first symmetric sub-circuit 560 A and a second symmetric sub-circuit 560 B, which are cross-coupled from each other, and each symmetric sub-circuit 560 A/ 560 B is coupled with each bitline 540 A/ 540 B between the wordlines 590 and the bitline conditioning circuit 550 , individually, wherein each symmetric sub-circuit 560 A/ 560 B further comprises a plurality of PMOSs and NMOSs; each symmetric sub-circuit 560 A/ 560 B is coupled with the power 580 by one of PMOSs P 1 /P 2 , and each that 560 A/ 560 B is individually coupled with each bitline 540 A/ 540 B by another of PMOSs P 3 /P 4 ; and further, each that 560 A/ 560 B individually electrifies the ground terminal by one of NMOSs N 1 /N 2 .

Referring to FIG. 5 , in this embodiment, the operation of the static random access memory system 500 is described as followings: first of all, the control sub-circuit 570 of the static random access memory system 500 communicates the first signal to enable the bitline conditioning circuit 550 so as to perform a pre-charge procedure and attain to Vcc for operating the memory column, and the second signal is simultaneously communicated to disable the compensating-circuit 560 . After the memory column 510 attains to Vcc, the control sub-circuit 570 of the static random access memory system 500 communicates the second signal to disable the bitline conditioning circuit 550 so as to proceed with an access procedure. If one of the memory cells 510 is selected to perform the access procedure and other memory cells 510 are not selected, the wordline 590 coupled with the one of the memory cells 510 is enabled to proceed with the access procedure thereof. The control sub-circuit 570 of the static random access memory system 500 communicates the first signal to enable the compensating-circuit 560 , so as to perform a compensation procedure during the access procedure, wherein that system 500 can control the pre-charge procedure and the compensation procedure by the interaction between the bitline conditioning circuit 550 and the compensating-circuit 560 . The compensation procedure is described as followings: when the voltage level of the second bitline 540 B is abnormal, the PMOS P 3 of the first symmetric sub-circuit 560 A couples to receive the first signal from the control sub-circuit 570 so as to disable that 560 A and enable the power 580 via the PMOS P 2 of the second symmetric sub-circuit 560 B to supply Vcc to the second bitline 540 B from the PMOS P 4 of that 560 B, whereby the memory cells 530 of the memory column 510 can keep Vcc for operation; on the contrary, when the voltage level of the first bitline 540 A is abnormal, the PMOS P 4 of the second symmetric sub-circuit 560 B couples to receive the first signal from the control sub-circuit 570 so as to disable that 560 B and enable the power 580 via the PMOS P 1 of the first symmetric sub-circuit 560 A to supply Vcc to the first bitline 540 A from the PMOS P 3 of that 560 A, whereby the memory cells 530 of the memory column 510 can keep Vcc for operation.

As illustrated in FIG. 6 , in the fifth embodiment of the present invention, first of all, a static random access memory system 600 is provided. The static random access memory system 600 comprises: a memory cell region having a memory column 610 , wherein the memory column 610 consists of a plurality memory cells 620 that are arranged in sequence therein; a first bitline 630 A and a second bitline 630 B that are individually coupled with the memory cells 620 of the memory column 610 , wherein the same bitline 630 A/ 630 B is coupled with the same side of the memory column 610 ; a plurality of wordlines 640 , wherein each wordline 640 is coupled with each memory cell 620 of the memory column 610 , the first bitline 630 A and the second bitline 630 B; a bitline conditioning circuit 650 that is coupled with the first bitline 630 A and the second bitline 630 B, individually; a compensating-circuit 660 that is coupled with the first bitline 630 A and the second bitline 630 B, individually, between a first wordline 640 A of the wordlines 640 and the bitline conditioning circuit 650 ; a control sub-circuit 670 that is individually coupled with the bitline conditioning circuit 650 and the compensating-circuit 660 , the control sub-circuit 670 simultaneously communicates a pair of complemental signals to the bitline conditioning circuit 650 and the compensating-circuit 660 so as to perform a interaction, wherein the pair of complemental signals include a first signal this is “ON” signal and a second signal that is “OFF” signal.

Referring to FIG. 6 , in this embodiment, the compensating-circuit 660 comprises: a first PMOS device 675 A and a second PMOS device 675 B whose sources are coupled with a power 690 ; a third PMOS device 675 C and a fourth PMOS device 675 D, the sources of the third PMOS device 675 C is coupled with the drain of the first PMOS device 675 A and the sources of the fourth PMOS device 675 D is coupled with the drain of the second PMOS device 675 B; a first NMOS device 680 A whose drain is coupled with the gate of the third PMOS device 675 C and source electrifies the ground terminal and gate is coupled with the drain of the third PMOS device 675 C to form a first node 685 A; a second NMOS device 680 B whose drain is coupled with the gate of the fourth PMOS device 675 D and source electrifies the ground terminal and gate is coupled with the drain of the fourth PMOS device 675 D to form a second node 685 B; a fifth PMOS device 675 E whose source is coupled with the gate of the second PMOS device 675 B on the first node 685 A and drain is coupled with the first bitline 630 A between the first wordline 640 A and the bitline conditioning circuit 650 ; a sixth PMOS device 675 F whose source is coupled with the gate of the first PMOS device 675 A on the second node 685 B and drain is coupled with the second bitline 630 B between the first wordline 640 A and the bitline conditioning circuit 650 . Furthermore, the first PMOS device 675 A, the third PMOS device 675 C, the fifth PMOS device 675 E, the first NMOS device 680 A and the first node 685 A construct a first symmetric sub-circuit 660 A, and the second PMOS device 675 B, the fourth PMOS device 675 D, the sixth PMOS device 675 F, the second NMOS device 680 B and the second node 685 B construct a second symmetric sub-circuit 660 B.

Referring to FIG. 6 , in this embodiment, the operation of the static random access memory system 600 is described as followings: first of all, the control sub-circuit 670 communicates the first signal to enable the bitline conditioning circuit 650 so as to perform a pre-charge procedure for the memory cells 620 of the memory column 610 , and the second signal is simultaneously communicated to disable the compensating-circuit 660 , wherein the second state, such as “0” signal, located on the second bitline 630 B are lower than the first state, such as “1” signal, located on the first bitline 630 A in all memory cells 620 when the memory cells 620 attain to Vcc. After memory cells attain to Vcc, the control sub-circuit 670 communicates the second signal to disable the bitline conditioning circuit 650 . If the first wordline 640 A coupled with the first memory cells 620 A is selected to perform the access procedure and other wordlines 640 coupled with other memory cells 620 are not selected, the first wordline 640 A is enabled to make the second state of the first memory cell 620 A, such as “1” signal, located on the second bitline 630 B higher than that of other memory cells 620 , such as “0” signal, and then the first state of the first memory cell 620 A, such as “0” signal, located on the first bitline 630 A lower than that of other memory cells 620 , such as “1” signal. When the voltage level of the second state in the first memory cell 620 A is abnormal, that is, “1” signal tends to become “0” signal due to the leakage, the control sub-circuit 670 enable the compensating-circuit 660 by communicating the first signal to perform a compensation procedure, and the first signal is simultaneously communicated to the gates of the fifth PMOS device 675 E and the sixth PMOS device 675 F, wherein the fifth PMOS device 675 E couple to enable the second PMOS device 675 B so that Vcc is guided into the second bitline 630 B from the power 690 via the second PMOS device 675 B, the fourth PMOS device 675 D, the second node 685 B and the sixth PMOS device 675 F in sequence so as to keep the second state of the first memory cell 620 A being higher than that of other memory cells 620 , whereby Vcc for operating the first memory cell 620 A during the access procedure can be maintained for avoiding the bitlines 630 A/ 630 B decayed as time going on resulted from serious leakage problems.

Due to process technology progresses, such as gate oxide thickness and gate length of transistors requirements of advanced process induced a complicated and difficult leakage problem such as standby current issue. For these leakage problems in the SRAM, the conventional method provides that a memory system having memory cells wherein pass transistors have lower threshold voltages (Vt) than do latch transistors, and wherein wordlines for non-selected memory cells are underdriven to reduce leakage in bitlines. But it needs to satisfy the requirement of the process and to modify. Therefore, this invention utilizes a leakage-compensation circuit to solve these leakage problems from a circuitry point of view. According to this invention, in the precharge operation, one of the complementary signals coupled into the bitline conditioning circuit is ON to precharge Vcc into the bitlines, and the other of the complementary signals coupled into the compensation circuit is OFF to be disabled. On the contrary, in the access operation, one of the complementary signals coupled into the compensation circuit is ON to be enabled, and the other of the complementary signals coupled into the bitline conditioning circuit is OFF to be disabled. When the signal of the worldline for the selected memory cell is ON, in the beginning, the bitlines are tri-state at Vcc. In the conventional SRAM, one of the bitlines will be decayed as time going on due to serious leakage problem, but this leakage problem is avoided by the leakage-compensation scheme of the present invention. Furthermore, the leakage-compensation circuit itself will detect the differential voltage level of bitlines due to cross-couple scheme, and compensate the voltage level of bitlines immediately. These embodiments of the present invention described as above, when the abnormal voltage level of bitlines is detected, and one of the symmetric sub-circuits in the leakage-compensation circuit compensates to Vcc immediately.

In these embodiments of the present invention, as discussed above, this invention can utilize a compensating-circuit to maintain Vcc for operating SRAM during the access procedure. Of course, it is possible to apply the circuitry scheme concerning SRAM system, and it is also possible for the present invention to be applied to the circuitry scheme in any memory system. Furthermore, at the present time, this invention that schemes a compensating-circuit to solve these leakage problems from a circuitry point of view has not been developed to apply the subject matter concerning preventing the leakage in the memory system. Therefore, the method of the present invention is the best method for avoiding the leakage on bitlines for deep sub-micron circuitry scheme.

Obviously, many modifications and variations of the present invention are possible in light of the above teachings. It is to be understood that within the scope of the appended claims, the present invention may be practiced other than as specifically described herein.

Although the specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.