Low power SRAM

1. Field of the Invention

This invention relates to the field of random access memories, and in particular to a low power static random access memory SRAM.

2. Description of Related Art

In a computer, two types of main memory can be used to provide random access circuits, namely static random-access memory (SRAM) and dynamic random-access memory (DRAM). A single memory chip is made up of several million memory cells. In a SRAM chip, each memory cell typically consists of a single flip-flop (for storing the binary digits 1 or 0) and several transistors for the reading and writing operations. The access time of an SRAM chip is faster than a DRAM chip. SRAM chips are typically used in cache memory.

Current mode SRAMs designs, as the name would suggest, perform read-write operations in current mode during read and write operations and therefore consume less power than voltage mode devices.

Designers of prior art current mode SRAM architectures and implementations have traditionally focused on high speed, low power and low-voltage. Examples of such current-mode architectures are found in Wang et al., Low-Power Embedded SRAM Macros with Current-Mode Read/Write Operations, Proceedings ISLPED98, which purports to disclose a fully current-mode SRAM that uses 30% less power than an SRAM with only current-mode read operation; Khellah and Elmasry, Circuit techniques for High-Speed and Low-Power Multi-Port SRAMs, 1998 IEEE; and Wang and Lee, A New Current-Mode Sense Amplifier for Low-Voltage Low-Power SRAM Design, 1998 IEEE. The contents of these papers are incorporated herein by reference.

However, such designs use separate bitlines for read and write in combination with current mode read bitlines and are not capable of offering ultra low power consumption.

According to the present invention there is provided a static random access memory (SRAM) comprising a plurality of bit cells for storing data in voltage mode at a data node; and a single bit line for respectively reading and writing a data bit to said data nodes in reference current controlled mode.

The data is stored in voltage mode, but during reading and write operations the data is accessed in reference current controlled mode.

In a preferred embodiment, each bit cell comprises first and second inverters. The second inverter has a tristatable output connected to an input of the first inverter to define the data node.

The novel SRAM employs a single bitline for read/write operations. This can be made very low swing offering the potential for ultra low power consumption. The voltage of the bit line is maintained very close to one of the supply rails. The voltage swing is less than one half of the voltage threshold of the associated MOSFET. The SRAM is preferably word based and includes a sense amplifier/line driver word control cell and a bit cell. The use of a tristatable inverter, which goes into tristatable during a writing operation, means that a much lower current is needed to change the state of the cell. It permits a change of cell data with minimal current consumption.

The novel SRAM architecture and method of operation can be applied to both single port SRAMs and multiport SRAMs.

In preferred implementation the SRAM comprises an ultra low power current mode single bitline read/write RAM bit cell, and ultra low power RAM word control cell, and an ultra low power current mode single bitline detect and single bitline drive RAM read detector and write driver cell.

Typically, the SRAM has a plurality of bit cells selectable by a multiplexer tree, which is connected to a write driver circuit and a read detector. Advantageously, the read detector comprises a pair of current sources and a current conveyor. When a selected bit cell sources current, one of the current sources pulls the voltage at an output node up toward supply voltage.

The read/write selection is preferably performed with a selection transistor that when turned on is configured so that its gate voltage is approximately equal to its threshold voltage. Advantageously the selection transistor also acts as a birectional voltage-to-current converter.

The invention also provides a method of storing a data bit in a static random access memory having a plurality of bit cells, comprising storing data in voltage mode at data node in each bit cell, and respectively reading and writing a data bit to said data nodes in reference current controlled mode using a single bit line.

The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an equivalent diagram illustrating a read operation in an exemplary SRAM in accordance with the invention;

FIG. 2 is a diagram illustrating a write operation;

FIG. 3 illustrates an ultra low power current mode single bit line read/write RAM bit cell;

FIG. 4 illustrates an ultra low power RAM word control cell RAM word control cell for the SRAM; and

FIG. 5 illustrates an ultra low power RAM read detector write driver cell for the SRAM.

The principle of operation of an exemplary SRAM in accordance with the invention is shown in FIGS. 1 and 2 . FIG. 1 shows a write operation and FIG. 2 shows a read operation.

FIG. 1 shows a bit cell 10 , a Mux tree 12 , and a read detector 14 . Each demultiplexed line 11 is connected to a bit cell 10 so that the read detector 14 can be selectively connected through the Mux tree 12 to a selected bit cell.

The state of the bit cell 10 is defined by the node n 1 which controls the polarity of the voltage-to-current converter 16 and generates the bit cell state current (I bc ). The value of the bit cell state current I bc is set by the combined select and current level signal I val-sel .The state current for the bit cell 10 is defined as I 1 , flowing into the bit cell 10 and I 2 flowing out of the bit cell 10 .

The bit cell current I affects the equilibrium of the read detector 14 such that if the bit cell 10 is sourcing current, the upper current source 18 will pull the output node n 3 up towards positive supply since the bit cell current applied to node n 2 will supply the current needed for the lower current source 20 and current conveyer 22 located between node n 2 and node n 3 sources the net current of the node n 2 into the node n 3 . A current conveyor is described, for example, in the Wang article referred to above.

FIG. 2 illustrates the write mode principle of operation. The device is shown as having the bit cell 10 , mux tree 12 , and write driver 24 . As in FIG. 1 , the mux tree selects a bit cell into which it is desired to write data.

In FIG. 2 , the bit cell 10 has a current source 26 generating a current I stth pulling node n 1 up towards positive supply with the current I stth where stth represents the state threshold for the bit cell 10 . The voltage-to-current converter 16 ′ has changed direction and is now directed towards the bit cell 10 rather than towards the mux tree 12 . The output of the voltage-to-current converter 16 , which will depend on a signal d in in the write driver, sinks a current I WT from the node n 1 . The data is thus stored in voltage mode. Read and write operations occur in reference current controlled mode.

In the configuration shown in FIG. 2 , if write signal din is high, the current I WT is greater than the current I stth , and the node n 1 is low. If the write signal d in is low, the current I WT less than the current I stth , and the node n 1 is high, or in other words if d in =High I WT >I stth and n 1 =Low else if d in =Low I WT <I stth and n 1 =High. It will be seen that the stored data value is the inverse of the actual data value determined by the input signal d in .

The preferred practical Implementation of the invention comprises three different parts, namely an ultra low power current mode single bitline read/write RAM bit cell shown in FIG. 3 , an ultra low power RAM word control cell shown in FIG. 4 and an ultra low power current mode single bitline detect and single bitline drive RAM read detector and write driver cell shown in FIG. 5 .

The ultra low power current mode single bit fine read/write RAM bit cell shown in FIG. 3 comprises two CMOS inverters, namely one ordinary two transistor inverter inv 1 and a second tristatable four transistor inverter inv 2 . This goes into tristate during write operations and thus enables a much lower current to change the state of the cell. The inverters inv 1 and inv 2 are configured such that the output of inyl is connected to the input of inv 2 and the output of inv 2 is connected to the input of inv 1 .

The bit line has a very line swing. It is typically maintained a voltage close to one of the power rails and has a voltage swing less than one half of the threshold voltage V t of the associated MOSFET.

Transistor M 1 acts a bidirectional bitselect/pass transistor and also as a voltage-to-current converter connecting the read/write bitline rwbl into the cell and particularly to the node n 1 , which defines the state of the cell.

During write operation, if the word in which the bit cell is located is selected, inverter inv 2 is turned off by signals wctrl and the wctrib. Transistor M 2 is weakly turned on, vgs˜Vt, (gate voltage approximately equals threshold voltage) and therefore sources a current I stth , where stth=state threshold, to node n 1 . The gate voltage Vgs is a therefore reference current controlled voltage.

The transistor M 1 is also weakly turned on, vgs˜Vt, and sinks either a large current I 1set , which is greater than the current I stth , or a low current I 0set , which is less than the current I stth , depending on the data to be written to the cell.

Depending on the current through the transistor M 1 , the node n 1 Is forced either low (I 1set ) or high (I 0set ). When the inverter inv 2 is again turned on and the transistors M 1 and M 2 are turned off, the inverters inv 1 and inv 2 latch the new value for node n 1 since the inverter inv 2 is forced to the state of node n 1 by the inverter inv 1 .

The capacitance C par for the node n 1 holds the new value for the node n 1 during control signal switching. To achieve a correct write function, the current rwbl through the transistor M 1 should be approximately equal to two times the current I stth (Irwbl˜2*I stth ) The required ratio between I stth and I rwbl is achieved by appropriate scaling of the transistors M 1 and M 2 together with the appropriate setting of the voltages w_vbp and rw_vbn.

The described device uses a very low supply current due to the fact that there is no drain of crowbar currents when writing a new state into the cell and the small voltage swings on the bitlines as a result of the current mode operation.

During a read operation and if the word in which the bit cell 10 is located is selected, the transistor M 1 is weakly turned on, vgs˜Vt, and hence opens a path through to the signal line rwbl for the positive or negative current, which is dependent on the state of the cell, from the inverter inv 2 output to the read detector 14 .

The ultra low power RAM word control cell is shown in FIG. 4 . This provides the bias voltages necessary for the bit cell read and write function and also acts as a cross point for row select signals (wselr and rwsel), bank select signal (bsel) and the word bias current (ibias) which is routed through the bank select network.

The transistors M 11 (M 11 a , M 11 b ) and Ml 2 (Ml 2 a , Ml 2 b ) form a current mirror, both generating the signal rw_vbn, which is equal to Vvss+Vtn+Veffn, from the diode connected transistor M 11 and a bias current for the diode connected transistor M 13 (Ml 3 a , M 13 b ), which generates the signal w_vbp. This is equal to Vvdd−Vtp−Veffp. The transistors M 14 to M 17 are switches which turn the current mirrors on and off.

During a RAM word write operation, if the row and the bank are selected, the signals wselr (tailing r for row), rwsel and bsel are high and a source current flows into the ibias signal source, namely transistor M 14 . The signal wselw (tailing w for word) is high and turns the tristatable inverters of the bit cells in the selected word off. The signals w_vbp and rw_vbn become active and hence turn on the current sources and current conveyers in the bit cells. To achieve a correct write function of the bit cells, the appropriate values of the w_vbp and rw_vbn voltages are set by proper scaling of the transistors M 11 a , M 11 b ; M 12 a , M 12 b ; and M 13 a , M 13 b . The tristatable inverters are placed in a tristate during a write operation. This helps to keep current consumption to an absolute minimum.

During RAM word read operation, if the row and the bank are selected rwsel is high and a sourcing current flows into the ibias signal line. The rw_vbn signal becomes active, turning on the current conveyers for the bit cells.

The ultra low power read detector and write driver is shown in FIG. 5 . The transistors M 21 , M 22 and M 23 act as current sources biased by the signal vbias and source the current I 0 . The transistors M 21 and M 22 source the currents into the current mirror formed by transistors M 24 , M 25 and M 26 , which acts as the current conveyer. The rwbl node acts as a current summing node. The transistors M 28 , M 29 and M 212 are control switches controlling read and write operation.

During a write operation the signal wsel is high, turning on the switch transistor M 212 and making vbias active, causing the three I 0 currents to be sourced into the current mirror consisting of transistors M 24 to M 26 and inverter M 27 . The inverter M 27 is inactive due to the fact that the switch M 28 is off and the switch M 29 defines the signal d out as being the inverse of a low state due to the fact that the signal line rsel is low.

The writing of the selected bit cell is done by either not pulling any current through rwbl, wherein d in is low “0” and M 213 is turned off, or pulling a large current through rwbl, wherein d in is high “1” and M 213 is turned on.

During a read operation rsel is high, which turns on the switch transistor M 28 and turns off the switch M 29 , hence making the inverter M 27 active. The signal vbias is active, causing the three I 0 currents to be sourced into the current mirror transistors M 24 to M 26 and inverter M 27 . The switch transistor M 212 is off due to the fact that wsel is low.

If input current iin is positive, sourcing current into the current summing node, the current through transistor M 6 will decrease respectively making Idsm M6 <I 0 and hence the difference current will pull the node n 1 towards the positive supply, causing the inverter M 27 output to go low and hence the d out inverse output to go a high state, indicating a detected “0”.

If iin is negative, pulling current through rwbl, the current through M 6 will increase respectively making Ids M6 <I 0 to and hence the difference current will pull node n 1 towards negative supply causing the inverter M 27 output to go high and hence the d out inverse output to low state, indicating a detected “1”.

The described SRAM can be made to have ultra low power consumption or run at very high speed. It is also fully scaleable and thus has a broad range of uses. It uses single bit line current mode read and write SRAM architecture with bias current controlled speed and supply current dissipation.

The bit line has very low swing signaling, being Vdsat of an nmos transistor. The gate drive voltage of the selection transistors is close to the threshold voltage Vt. The selection transistor also acts as a controlled bidirectional voltage to current converter. Word selection is also done in the current mode. The SRAM can be used in both single port and multi-port configurations.