Plasma display panel having specifically spaced holes formed in the electrodes

1. Field of the Invention

The present invention relates to a plasma display panel, and more particularly to a plasma display panel that is adaptive for improving the uniformity of discharge.

2. Description of the Related Art

Recently, there has been developed various flat panel display devices with possible reduction in their weight and size, the weight and size have been the disadvantage of cathode ray tubes CRT. Such flat panel display devices include a liquid crystal display LCD, a field emission display FED, a plasma display panel PDP and an electro-luminescence EL panel, etc.

The PDP among these flat panel display devices is a display device using gas discharge and has an advantage that it is easy to be made on a large scale. A typical PDP is a three-electrode AC surface discharge PDP that has three electrodes, as shown in FIG. 1 , and is driven by AC voltage.

Referring to FIG. 1 , a discharge cell of the three-electrode AC surface-discharge PDP includes a first electrode 12 Y and a second electrode 12 Z formed on an upper substrate 10 , and an address electrode 20 X formed on a lower substrate 18 .

The first and second electrodes 12 Y and 12 Z are formed of transparent material in order to transmit the light supplied from the discharge cell. On the rear surface of the first and second electrodes 12 Y and 12 Z, bus electrodes 13 Y and 13 Z of metal are formed in parallel with the first and second electrodes 12 Y and 12 Z. Such bus electrodes 13 Y and 13 Z are used in order to supply driving signals to the first and second electrodes 12 Y and 12 Z with high resistance value.

On the upper substrate 10 provided with the first and second electrodes 12 Y and 12 Z in parallel, there are deposited an upper dielectric layer 14 and a passivation film 16 . Wall charges generated upon plasma discharge are accumulated in the upper dielectric layer 14 . The passivation film 16 prevents a damage of the upper dielectric layer 14 caused by a sputtering during the plasma discharge and improves the emission efficiency of secondary electrons. This passivation film 16 is usually made from magnesium oxide (MgO).

A lower dielectric layer 22 and barrier ribs 24 are formed on the lower substrate 18 provided with the address electrode 20 X. The surfaces of the lower dielectric layer 22 and the barrier ribs 24 are coated with a phosphorus 26 . The address electrode 20 X is formed in a direction crossing the first electrode 12 Y and the second electrode 12 Z. The barrier ribs 24 are formed in parallel to the address electrode 20 X to prevent an ultraviolet ray and a visible light generated by a discharge from being leaked to the adjacent discharge cells.

The phosphorus 26 is excited by the ultraviolet ray generated during the plasma discharge to generate any one of red, green and blue visible light rays. There is an inactive gas for a gas discharge injected into a discharge space defined between upper/lower plates and the barrier ribs, wherein the inactive gas can be He+Ne, He+Xe or He+Ne+Xe etc.

In such a conventional PDP, the first and second electrodes 12 Y and 12 Z are formed parallel in each discharge cell. The first electrode 12 Y is supplied with a reset pulse, a scan pulse and a first sustain pulse. The second electrode 12 Y is supplied with a second sustain pulse.

When the reset pulse is applied to the first electrode 12 Y, the discharge cells are initialized. When the first electrode 12 Y is supplied with the scan pulse, the address electrode 20 X is supplied with data pulses synchronized with the scan pulses. At this moment, an address discharge is generated in the discharge cells which is supplied with a scan pulse and a data pulse.

After the address discharge is generated in the discharge cells, the first and second sustain pulses are alternately applied to the first and second electrodes 12 Y and 12 Z. When the first and second electrodes 12 Y and 12 Z are supplied with the first and second sustain pulses, there is a sustain discharge generated in the discharge cells where the address discharge is generated. In this sustain discharge, discharge time is determined by gray level values, and a picture is displayed in accordance with the gray level values.

On the other hand, the conventional first and second electrodes 12 Y and 12 Z occupy a broad area and are formed in parallel in the discharge cells. In this way, if the first and second electrodes 12 Y and 12 Z occupy a broader area, there is bigger power dissipation. Consequently, there is deterioration in the discharge efficiency of the PDP.

Referring to FIG. 3 , the PDP according to another embodiment of the prior art includes an address electrode 32 X, a first and a second electrode 31 Y and 31 Z formed in a direction crossing the address electrode, a first electrode 30 Y extended from the first bus electrode 31 Y, and a second electrode 30 Z extended from the second bus electrode 31 Z.

The first electrode 30 Y is extended in a ‘T’ shape from the first bus electrode 31 Y. The second electrode 30 Z is extended in a ‘T’ shape from the second bus electrode 31 Z. If the first and second electrodes 30 Y and 30 Z are formed in a ‘T’ shape, their total area can be reduced while keeping the electrodes long enough. Accordingly, the power dissipation decreases as much as the area of the first and second electrodes 30 Y and 30 Z is reduced, thereby improving the discharge efficiency. Also, in an example, the PDP with the ‘T’ shape electrode structure appears to be improved by about 15% in its light emitting efficiency.

Herein, in the conventional PDP with the ‘T’ shape electrode, the first and second electrodes 30 Y and 30 Z should be aligned between the barrier ribs 24 accurately. However, there occurs a movement of a few μm to several tens μm in the course of joining the upper and lower substrates 10 and 18 of the PDP. If there occurs any movement in the course of joining the upper and lower substrates 10 and 18 , the first and second electrodes 30 Y and 30 Z cannot be formed at the center of the discharge cell as in FIG. 4 .

And if the first and second electrodes 30 Y and 30 Z of a ‘T’ shape are not formed at the center of the discharge cell, the discharge is not uniformly generated for every cell. Also, there occur no normal address and sustain discharge. Additionally, there is a change caused in a discharge voltage characteristic, and a bad influence is given to a picture quality in the end.

In order to overcome these disadvantage, a PDP as in FIG. 5 has been proposed.

Referring to FIG. 5 , the PDP according to still another embodiment of the prior art has at least two holes 42 formed on the first and second electrodes 40 Y and 40 Z of transparent electrodes. The holes 42 are disposed at regular intervals on the transparent electrode and should not overlap with the bus electrodes 41 Y and 41 Z.

The PDP according to still another embodiment of the prior art has an advantage of easy alignment as compared with the PDP as in FIG. 3 where the ‘T’ shape electrode should be located at the center of the discharge cell. And, power dissipation is reduced as much as the area in which the holes 42 are formed, and discharge efficiency is improved accordingly.

However, when the first and second electrodes 40 Y and 40 Z according to still another embodiment of the prior art are formed in the PDP, the areas where the first and second electrodes 40 Y and 40 Z overlap with the address electrode 44 X are different from one another in the cells. In other words, the holes 42 as in FIG. 6 overlap with the address electrodes 44 X in a range of 100%˜a few % for each discharge cell. Further, it is possible for the holes 42 not to overlap with the address electrodes 44 X.

In this way, if the area where the address electrode 44 X overlap with the hole 42 is different for each discharge cell, there occurs a lack of uniformity in the address discharge.

Accordingly, it is an object of the present invention to provide a plasma display panel that is adaptive for improving the uniformity of discharge.

In order to achieve these and other objects of the invention, a plasma display panel according to an aspect of the present invention includes a first electrode and a second electrode made of transparent material and formed parallel to each other in the sub-pixel; bus electrodes formed parallel to the first and second electrodes on one sides of the first and the second electrodes; and a plurality of holes formed in the first and second electrodes, and wherein a distance between the holes is set to 1/n (n is an integer of 1 or more) of the pixel.

Herein, the holes do not overlap with the bus electrode.

Herein, there is an address electrode formed crossing the first and second electrodes, and an overlapping area between the address electrode and the holes is set the same in all the sub-pixels.

A plasma display panel according to another aspect of the present invention includes a first electrode and a second electrode made of transparent material and formed parallel to each other in the sub-pixel; bus electrodes formed parallel to the first and second electrodes on one sides of the first and the second electrodes; and a plurality of holes formed in the first and second electrodes, and wherein a distance between the holes is set to 1/n (n is an integer of 1 or more) of the sub-pixel.

Herein, the holes do not overlap with the bus electrode.

Herein, there is an address electrode formed crossing the first and second electrodes, and an overlapping area between the address electrode and the holes is set the same in all the sub-pixels.

A plasma display panel according to still another aspect of the present invention includes a first electrode and a second electrode made of transparent material and formed parallel to each other in the sub-pixel; and a plurality of holes formed in the first and second electrodes, and wherein a distance between the holes is set to 1/n (n is an integer of 1 or more) of the sub-pixel.

Herein, the distance between the holes disposed in each of a red sub-pixel, a green sub-pixel and a blue sub-pixel is set to 1/n of the sub-pixel where the holes are formed.

Herein, there is an address electrode formed crossing the first and second electrodes, and an overlapping area between the address electrode and the holes is set the same in all the sub-pixels.

A plasma display panel according to still another aspect of the present invention includes a first electrode and a second electrode made of transparent material and formed parallel to each other in the sub-pixel; and a plurality of holes formed in the first and second electrodes, and wherein a distance between the holes is set to 1/n (n is an integer of 1 or more) of the sub-pixel.

Herein, the distance between the holes disposed in each of a red sub-pixel, a green sub-pixel and a blue sub-pixel is set to 1/n of the sub-pixel where the holes are formed.

Herein, the widths of the holes are set to 1/i (i is an integer of 1 or more) of the address electrode.

Herein, the widths of the holes disposed in each of a red sub-pixel, a green sub-pixel and a blue sub-pixel are set to 1/i of the width of the address electrode formed in the sub-pixel where the holes are formed.

Herein, the address electrode is formed crossing the first and second electrodes, and an overlapping rate between the address electrode and the holes is set the same in all the sub-pixels.

These and other objects of the invention will be apparent from the following detailed description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a perspective view representing a conventional three electrode AC surface discharge plasma display panel;

FIG. 2 illustrates an electrode structure of the plasma display panel shown in FIG. 1 ;

FIGS. 3 and 4 illustrate plasma display panels according to another embodiment of the prior art;

FIGS. 5 and 6 illustrate an electrode structure of a plasma display panel according to another embodiment of the related art;

FIGS. 7 and 8 illustrate plasma display panels according to the first embodiment of the present invention;

FIGS. 9 and 10 illustrate plasma display panels according to the second embodiment of the present invention;

FIGS. 11 and 12 illustrate plasma display panels according to the third embodiment of the present invention;

Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

FIG. 7 illustrates a plasma display panel according to the first embodiment of the present invention. In the PDP shown in FIG. 7 , it is assumed that sub-pixels are the same in size regardless of phosphorus materials of red, green and blue.

Referring to FIG. 7 , the PDP according to the embodiment of the present invention includes a first electrode 50 Y, a bus electrode 51 Y formed on one side end of the first electrode 50 Y and applying a driving pulse to the first electrode 50 Y, an address electrode 54 X formed in a direction crossing the first electrode 50 Y, barrier ribs 52 formed parallel to the address electrode 54 X and preventing ultraviolet ray and visible light generated by a discharge from leaking to an adjacent discharge cell.

The first electrode 50 Y is only illustrated in FIG. 7 , however actually in a discharge cell, there is a second electrode (not shown) formed in the same shape as the first electrode as well as parallel to the first electrode.

There are a plurality of holes 56 formed in the first electrode 50 Y by the embodiment of the present invention. Since holes 56 are formed in the first electrode 50 Y, its power dissipation is reduced as much as the area where the holes 56 are formed and its discharge efficiency is improved accordingly.

On the other hand, the distance T 1 of the holes 56 is set to 1/n (n is an integer of 1 or more) of the sub-pixel, i.e., discharge cell of red, green or blue. In this way, if the distance T 1 between the holes 56 is set to 1/n of the sub-pixel, the area where the address electrode 54 X overlap with the first electrode 50 Y becomes identical in all discharge cells as in FIG. 7 .

In other words, if the distance T 1 between holes 56 is set to 1/n, the holes 56 are disposed at the rate of the sub-pixels. Accordingly, if the hole 56 is disposed partially overlapping with the address electrode 54 X in a specific cell, the hole 56 is disposed partially overlapping with the address electrode 54 X in all other cells. Also, if the hole 56 is disposed completely overlapping with the address electrode 54 X in a specific cell as in FIG. 8 , the hole 56 is disposed completely overlapping with the address electrode 54 X in all other cells.

Like this in the present invention, the area where the address electrode 54 X overlap with the first electrode 50 Y becomes identical in all discharge cells, thus the uniformity of the address discharge can be assured.

On the other hand, in the present invention, the distance T 1 between the holes 56 can be set to 1/n of a pixel consisting of discharge cells of red, green and blue. If the distance between the holes 56 is set to 1/n of the pixels, the area where the address electrode 54 X overlap with the first electrode 50 Y becomes identical in all discharge cells, thus the uniformity of the address discharge can be assured.

FIG. 9 illustrates a plasma display panel according to the second embodiment of the present invention.

Referring to FIG. 9 , a PDP according to the second embodiment of the present invention has the size of the sub-pixels R, G and B set differently for each of phosphorus materials of red, green and blue. The PDP of the present invention includes a first electrode 70 Y and a second electrode 70 Z; a first bus electrode 71 Y and a second bus electrode 71 Y and 71 Z formed on one side end of the first and second electrodes 70 Y and 70 Z and receiving a driving pulse from the outside; an address electrode 76 X formed in a direction crossing the first and second electrodes 70 Y and 70 Z; and barrier ribs 74 formed parallel to the address electrode 76 X and preventing the ultraviolet ray and visible light generated by a discharge from leaking to an adjacent discharge cell.

In the PDP of the present invention, the first and second electrodes 70 Y and 70 Z are formed parallel to each other. The first electrode 70 Y receives a reset pulse, a scan pulse and a first sustain pulse. The second electrode 70 Z receives a second sustain pulse.

There are discharge cells initialized when the reset pulse is applied to the first electrode. When the first electrode 70 Y is supplied with the scan pulse, the address electrode 76 X is supplied with a data pulse synchronized with the scan pulse. At this moment, the address discharge is generated in the discharge cells to which the scan pulse and the data pulse are applied.

After the address discharge being generated in the discharge cells, the first and second electrodes 70 Y and 70 Z are alternately supplied with the first and second sustain pulses. If the first and second electrodes 70 Y and 70 Z are supplied with the first and second sustain pulses, the sustain discharge is generated in the discharge cells where the address discharge has been generated. In such a sustain discharge, its discharge time is determined by a gray level value, and a picture is displayed in accordance with the gray level value.

In the second embodiment of the present invention, there are a plurality of holes 72 formed in the first and second electrodes 70 Y and 70 Z. Like this, since the holes 72 are formed in the first and second electrodes 70 Y and 70 Z, the power dissipation is reduced as much as the area where the holes 72 are formed, and there is an improvement in discharge efficiency accordingly.

On the other hand, a distance between the holes 72 is set to 1/n (n is an integer of 1 or more) of the sub-pixel of R, G and B.

In other words, the holes 72 formed in an R sub-pixel as in FIG. 7 are disposed with the distances T 1 therebetween being 1/n of the R sub-pixel. The holes 72 formed in a G sub-pixel are disposed with the distances T 2 therebetween being 1/n of the G sub-pixel. And, the holes 72 formed in an B sub-pixel are disposed with the distances T 3 therebetween being 1/n of the B sub-pixel.

If the holes 72 are disposed with the distance therebetween being 1/n of the sub-pixel in which they are formed, the area where the address electrode 76 X overlap with the first electrode 70 Y and/or the second electrode 70 Z becomes identical in all discharge cells.

In other words, if the distances T 1 , T 2 and T 3 between the holes 72 are set to 1/n of the sub-pixels where they are formed, the holes 72 are disposed at the rate of the sub-pixels. Accordingly, if the hole 72 is disposed overlapping with the address electrode 76 X in a specific cell, the hole 72 is disposed overlapping with the address electrode 76 X in all other cells.

On the other hand, the overlapping rate of the holes 72 and the address electrode 76 X is the same in all discharge cells even though there is any movement of the first electrode 70 Y and/or the second electrode 70 Z in the course of joining an upper substrate and a lower substrate (not shown). In other words, even though the first electrode 70 Y is moved within a specific μm in the course of joining the upper and lower substrates of the first electrode 70 Y, the overlapping rate of the first electrode 70 Y and the address electrode 76 X as in FIG. 10 are set the same in all the discharge cells.

In the second embodiment of the present invention, the area where the address electrode 76 X overlap with the first electrode 70 Y becomes identical in all discharge cells, thus the uniformity of the address discharge can be assured.

FIG. 11 illustrates a plasma display panel according to the third embodiment of the present invention.

Referring to FIG. 11 , a PDP according to the third embodiment of the present invention has the size of the sub-pixels R, G and B and the width of address electrodes 88 X, 90 X and 92 X set differently for each of phosphorus materials of red, green and blue. That is, the size of the sub-pixels are set in order of B sub-pixel>G sub-pixel>R sub-pixel. Similarly, the width of the address electrode 92 X formed in the B sub-pixel is set to be wider than that of the address electrode 90 X formed in the G sub-pixel. Also, the width of the address electrode 90 X formed in the G sub-pixel is set to be wider than the address electrode 88 X formed in the R sub-pixel.

There are a plurality of holes 82 , 84 and 86 formed in the first and second electrodes 80 Y and 80 Z of the PDP according to the second embodiment of the present invention. Since the holes 82 , 84 and 86 are formed in the first and second electrodes 80 Y and 80 Z in this way, its power dissipation is reduced as much as the area where the holes 82 , 84 and 86 are formed and there is an improvement in its discharge efficiency accordingly.

On the other hand, in this invention, the width of the holes 82 , 84 and 86 are set to 1/i (i is an integer of 1 or more) of the sub-pixel where they are formed. Accordingly, the width T 5 of the holes 84 disposed in the G sub-pixel is set to be wider than the width T 4 of the holes 82 disposed in the R sub-pixel. Also, the width T 6 of the holes 86 disposed in the B sub-pixel is set to be wider than the width T 5 of the holes 84 disposed in the G sub-pixel.

Herein, distances between the holes 82 , 84 and 86 are set to 1/n (n is an integer of 1 or more) of the sub-pixel where the holes are formed. In other words, the holes 82 formed in an R sub-pixel are disposed with the distances T 1 therebetween being 1/n of the R sub-pixel. The holes 84 formed in a G sub-pixel are disposed with the distances T 2 therebetween being 1/n of the G sub-pixel. And, the holes 86 formed in an B sub-pixel are disposed with the distances T 3 therebetween being 1/n of the B sub-pixel.

If the holes 82 , 84 and 86 are disposed with the distance therebetween being 1/n of the sub-pixel in which they are formed and if the sizes of the holes 82 , 84 and 86 are set correspondingly to the widths of the address electrodes 88 X, 90 X and 92 X where the holes are formed, the ratio that the first and second electrodes 80 Y and 80 Z overlap with the address electrodes 88 X, 90 X and 92 X becomes identical in all discharge cells.

On the other hand, the overlapping rate of the holes 82 , 84 and 86 and the address electrodes 88 X, 90 X and 92 X is the same in all discharge cells even though there is any movement of the first electrode 80 Y and/or the second electrode 80 Z in the course of joining an upper substrate and a lower substrate (not shown).

In other words, even though the first electrode 80 Y is moved within a specific μm in the course of joining the upper and lower substrates of the first electrode 70 Y, the overlapping rate of the first electrode 80 Y and the address electrode 88 X, 90 X and 92 X as in FIG. 12 are set the same in all the discharge cells.

As described above, in the plasma display panel according to the present invention, the distances between holes formed in the first and second electrodes are set to 1/n of the sub-pixel. If the distance between holes is set to 1/n of the sub-pixel, the area where the first and second electrodes overlap with the address electrode is the same in all the discharge cells. The present invention can assure the uniformity of the discharge by keeping the overlapping area of the first and second electrodes and the address electrode the same in all discharge cells.

Also, it is possible to assure the overlapping area of the first and second electrodes and the address electrode the same in all the discharge cells by having the width of the holes changed correspondingly to the width of the address electrode.

Although the present invention has been explained by the embodiments shown in the drawings described above, it should be understood to the ordinary skilled person in the art that the invention is not limited to the embodiments, but rather that various changes or modifications thereof are possible without departing from the spirit of the invention. Accordingly, the scope of the invention shall be determined only by the appended claims and their equivalents.