Electronic amplifier

1. Technical Field (Field of the Invention)

The present invention relates to electronic amplifiers. More particularly, the invention concerns an electronic amplifier that has fast DC settling for providing accurate amplification at low frequencies.

2. Description of Related Art

Power amplifiers are widely used electronic devices. Power amplifiers can be used, for example, as audio, servo (motor control), or instrumentation amplifiers. Ideally, a power amplifier produces an output signal at a load that is identical to an input signal, except that the power of the output signal is greater than the power of the input signal. (Pout=Vout*Iout)>(Pin=Vin*Iin). In many applications it is desirable to have a power amplifier that has a frequency response which is substantially flat down to DC, for amplifying signals that include very low frequencies (for example, frequencies below 20 Hz), or DC.

Amplifiers commonly utilize feedback to reduce errors caused, for example, by inaccurate components, component mismatches, and power supply issues. A prior art:design for an amplifier circuit 100 that utilizes feedback is illustrated in FIG. 1 . The amplifier circuit 100 has an input 101 and an output 102 , and includes an amplifier 103 , a resistor 104 , an operational amplifier 106 , a capacitor 108 , and an adder 109 . The amplifier 103 has an input 110 and an output 111 . The operational amplifier 106 has an inverting input 112 , a noninverting input 113 , and an output 114 . The adder 109 has an inverting input 116 , a noninverting input 118 , and an output 120 . The prior art amplifier circuit 100 utilizes feedback implemented with a DC servo loop that includes the resistor 104 , the operational amplifier 106 , and the capacitor 108 . To prevent degradation of the low frequency response of the amplifier circuit 100 , the frequency response of the servo loop must be considerably lower than the minimum frequency that is to be amplified by the amplifier circuit 100 . In many applications, for example audio amplifiers and servo amplifiers, this characteristic of DC servo loop feedback amplifiers and the general inability of DC servo loop feedback amplifiers to be used to amplify DC signals, is a serious disadvantage. The amplifier circuit 100 has the further disadvantage of producing a DC offset at the output 102 , in response to an AC input signal that has a DC component at the input 101 .

Feed-forward error correction is another technique that can be utilized in amplifier circuits to reduce output errors. However, a feed-forward amplifier circuit typically includes one or more filters to improve the AC characteristics of the amplifier. Filters are typically implemented with a capacitor or with another frequency dependent circuit element. A disadvantage of including a filter in an amplifier circuit is that the filter generally will degrade the low frequency response of the amplifier.

For circuits that can be implemented in integrated circuits, accurate component matching can be utilized to reduce errors caused by component mismatches. However this technique is not available for power amplifiers, due to voltage and current limitations of integrated circuits, which prevent implementing power amplifiers on integrated circuits.

In summary, existing designs are inadequate for implementing a power amplifier that can accurately amplify low frequency signals.

An illustrative embodiment of the present invention concerns an amplifier circuit that provides accurate amplification over a range of frequencies including very low frequencies, and DC. The amplifier circuit includes an input and an output, a voltage-to-current converter, a feed-forward resistive element, a buffer, an input resistive element, a feedback resistive element, and an operational amplifier. The voltage-to-current converter has an output, and an input that is coupled to the input of the amplifier circuit. The feed-forward resistive element has a first end and a second end. The first end of the feed-forward resistive element is coupled to the output of the voltage-to-current converter. The buffer has an output that is coupled to the output of the amplifier circuit, and an input that is coupled to the first end of the feed-forward resistive element. The input resistive element has a first end and a second end. The first end of the input resistive element is coupled to the input of the amplifier circuit. The feedback resistive element has a first end and a second end, and the first end of the feedback resistive element is coupled to the output of the amplifier circuit. The operational amplifier has an inverting input, a noninverting input, and an output. The inverting input is coupled to the second end of the input resistive element and to the second end of the feedback resistive element. The noninverting input is coupled to ground, an,d the output of the operational amplifier is coupled to the second end of the feed-forward resistive element.

Another aspect of the invention is a method for amplifying a voltage. Illustrative examples of various aspects of the invention are described in the sections below.

The invention provides a number of advantages, including the ability to accurately-amplify electronic signals that include very low frequency and DC components. The invention also provides a number of other advantages and benefits, which should be apparent from the following description.

FIG. 1 is a block diagram of an amplifier circuit in accordance with the prior art.

FIG. 2 is a block diagram of an amplifier circuit in accordance with an illustrative .embodiment of he invention.

FIG. 3 is a block diagram of an amplifier circuit in accordance with another illustrative embodiment of he invention.

FIG. 4 is a block diagram of an amplifier circuit in accordance with another illustrative embodiment of he invention.

FIG. 5 is a schematic diagram of a V/I converter in accordance with an illustrative embodiment of the invention.

FIG. 6 is another schematic diagram of a V/I converter in accordance with an illustrative embodiment of the invention.

FIG. 7 is a schematic diagram of a current mirror in accordance with an illustrative embodiment of the invention.

FIG. 8 is a schematic diagram of an output buffer in accordance with an illustrative embodiment of the invention.

FIG. 9A shows transistors Q 9 and Q 11 physically attached to each other, and FIG. 9B shows transistors Q 10 and Q 12 physically attached to each other, in accordance with an illustrative embodiment of the invention.

FIG. 10 is a flowchart of an operational sequence for amplifying a voltage in accordance with an illustrative embodiment of the invention.

FIG. 11 is a flowchart of another operational sequence for amplifying a voltage in accordance with an illustrative embodiment of the invention.

The nature, objectives, and advantages of the invention will become more apparent to those skilled in the art after considering the following detailed description in connection with the accompanying drawings.

A. First Example of Amplifier

One aspect of the invention concerns an electronic amplifier. As an example, the electronic amplifier may be embodied by the amplifier circuit 200 shown in FIG. 2 . The amplifier circuit 200 includes an amplifier input node 202 , which may be referred to as a power amplifier input, and an amplifier output node 204 , which may be referred to as a power amplifier output. The amplifier circuit also includes a voltage-to-current converter 206 that has an input 208 and an output 210 . The output 210 of the voltage-to-current converter 206 generates a current 11 that is proportional to the input voltage at the input 208 of the V/I converter 206 . The input 208 of the voltage-to-current converter 206 is coupled to the input node 202 . The voltage-to-current converter 206 may be referred to as a high voltage V/I converter. The amplifier circuit 200 also includes a feed-forward impedance element 212 that has a first end 214 and a second end 216 . The first end 214 of the feed-forward impedance element 212 is coupled to the output 210 of the voltage-to-current converter 206 . The voltage-to-current converter 206 may convert a relatively small voltage at the input 208 to the voltage-to-current converter 206 , into a relatively large current that flows through the feed-forward impedance element 212 , to produce a voltage V/I across the feed-forward impedance element 212 that is larger than the voltage at the input 208 to the voltage-to-current converter 206 .

The amplifier circuit 200 also includes a buffer 218 that has an input 220 and an output 222 . The output 222 of the buffer 218 is coupled to the amplifier output node 204 , and the input 220 of the buffer 218 is coupled to the first end 214 of the feed-forward impedance element 212 . The amplifier circuit 200 also includes an error amplifier input impedance element 224 having a first end 226 and a second end 228 . The first end 226 of the error amplifier input impedance element 224 is coupled to the input 208 of the voltage-to-current converter 206 . The amplifier circuit 200 further includes a feedback impedance element 230 having a first end 232 and a second end 234 . The first end 232 of the feedback impedance element 230 is coupled to the output 222 of the buffer 218 . The amplifier circuit 200 also includes an error amplifier 236 that has an inverting input 238 , a noninverting input 240 , and an output 242 . The inverting input 238 is coupled to the second end 228 of the error amplifier input impedance element 224 and to the second end 234 of the feedback impedance element 230 , and the output 242 of the error-amplifier 236 is coupled to the second end 216 of the feed-forward impedance element 212 . An error amplifier input voltage is produced at the inverting input 238 of the error amplifier 236 . An error amplifier output voltage V 2 is produced at the output 242 of the error amplifier 236 , which is feed-forward, through the feed-forward impedance element 212 , to the input 220 of the buffer 218 . Utilization of the error amplifier output voltage V 2 results in a reduction of distortion in the signal at the amplifier output node 204 . The total voltage at the input 220 of the buffer 218 is the sum of the voltage V 1 generated across the feed-forward impedance element 212 by the current I 1 , and the error amplifier output voltage V 2 .

Although not required, the noninverting input 240 of the error amplifier 236 is typically coupled to ground 244 , to optimize common mode rejection.

The amplifier circuit 200 may also include a buffer input node 246 coupled to the buffer input 220 , and an error amplifier output node 248 coupled to the output 242 of the error amplifier 236 .

The feed-forward impedance element 212 , the error amplifier input impedance element 224 , and the feedback impedance element 230 could be frequency-dependent capacitive or inductive components, but for most applications will have impedances that are substantially resistive with only parasitic capacitance and/or inductance. When the impedances are substantially resistive, the feed-forward impedance element 212 , the error amplifier input impedance element 224 , and the feedback impedance element 230 may be referred to respectively as the feed-forward resistive element, the error amplifier input resistive element, and the feedback resistive element. The feed-forward impedance element 212 , the error amplifier input impedance element 224 , and the feedback impedance element 230 are each typically resistors. When implemented with a resistor, the value of the feed-forward impedance element 212 may be in a range from about 500 ohms to about 20 k ohms, and will typically be in a range from about 1 k ohms to about 5 k ohms, and as an example, may have a value of about 2.2 k ohms. When implemented with a resistor, the value of the error amplifier input impedance element 224 may be in a range from about 1 k ohms to about 100 k ohms, and will typically be in a range from about 3 k ohms to about 30 k ohms, and as an example, may have a value of about 10 k ohms. When implemented with a resistor, the value of the feedback impedance element 230 may be in a range from about 2 k ohms to about 1M ohms, and will typically be in a range from about 3 k ohms to about 300 k ohms, and as an example, may have a value of about 68 k ohms.

When the feed-forward impedance-element 212 , the error-amplifier input impedance element 224 , and the feedback impedance element 230 are each substantially resistive, the amplifier circuit 200 does not include any filters or integrators (which can degrade performance), and consequently the amplifier circuit 200 provides the advantages of fast DC settling and accurate amplification of signals over a wide, frequency bandwidth, including low frequencies and DC. Consequently, the amplifier circuit 200 is well suited for many applications, including, for example, audio, servo, and instrumentation applications.

The error amplifier 236 typically is an operational amplifier, and, for example, may be a commercially available operational amplifier integrated circuit. Suitable operational amplifier integrated circuits include model number OPA 604 manufactured by Texas Instruments, and model number NE5532 which is generally available from several manufacturers. Alternatively, the operational amplifier may be implemented with discrete components. Thus, the amplifier circuit 200 may advantageously utilize a relatively inexpensive, low voltage, low power, operational amplifier having good AC and DC characteristics, to reduce the error in the output signal at the output 204 of the higher voltage, higher power, amplifier circuit 200 .

Although not required, typically the amplifier circuit 200 will be implemented as a power amplifier. The output of the buffer 222 may be configured to generate any value of output power generally realizable by an output buffer, and could generate, for example, about, 10, 50, 100, 200, 400, 1,000 or more watts of peak output power, and typically will be designed to generate between about 50 and about 300 watts peak of output power. Output voltages at the output 204 of the amplifier circuit 200 may range from about 20V peak to about 150V peak, however, smaller or larger peak voltages could be produced. The output current at the output 204 of the amplifier circuit 200 may range from about 1A peak to about 100A peak, however, smaller or larger peak currents could be produced. The input signal at the input 202 to the amplifier circuit 200 may range from about 10 mV peak to about 10V peak, and will typically be between about 1V peak and about 3V peak. The voltage gain of the amplifier circuit 200 may be, for example, in a range from about 10 to about 50, but also may be less than 10 or greater than 50. The amplifier circuit 200 of the present invention is characterized by a good low frequency response, and consequently, the −3 dB passband of the amplifier circuit 200 typically will include low frequencies, for example, 0 Hz (DC), 1mHz, 0.1 Hz, 1 Hz, 10 Hz, 15 Hz and/or 20 Hz. As an example, the −3 dB passband of the amplifier circuit 200 may be from about 1 Hz to about 130 KHz.

The voltage at the input node 202 may be referred to as V 1 , the voltage at the output node 204 may be referred to as Vout, the voltage generated by the current I 1 at the buffer input node 246 may be referred to as V 1 , the voltage at the error amplifier output node 248 may be referred to as V 2 , the transconductance of the voltage-to-current converter 206 may be referred to as −k, and the gain of the buffer 218 may be referred to as G. The value of k may be in a range from about 1 mA/V to about 50 mA/V, and as an example, may be about 10 mA/V. The value of G may be in a range from about 0.5 to about 30, and as an example, may be about 1. The input impedance of the buffer 218 will generally be much larger than the resistance Rg of the feed-forward impedance element 212 . The output 242 of the error amplifier 236 , the output 210 of the voltage-to-current converter 206 , the input 220 of the buffer 218 , and the feed-forward resistive element 212 interact such that V 1 is effectively added to V 2 so that the voltage at the buffer input node 246 is the sum of the voltages V 1 and V 2 . The output buffer 218 generates an output voltage at the power amplifier output 204 that is substantially proportional to the sum of the voltages V 1 and V 2 . Herein the word “proportional” is used broadly to include a signal having the same magnitude, larger magnitude, or smaller magnitude, and/or the same or different phase. An output signal at the output 204 of the amplifier circuit 200 will have a phase that is substantially opposite to the phase of an input signal at the input 202 to the amplifier circuit 200 .

With reference to FIG. 2 :

I 1 =− k*V in

V 1 =(− I 1 * Rg )+ V 2

V out= G*V 1 =−( G*I 1 * Rg )+( G*V 2 )=−( G*k*V in* Rg )+( G*V 2 )

Also, V out=−( R 2 / R 1 )* V in

So, −( R 2 / R 1 )* V in=−( G*k*V in* Rg )+( G*V 2 )

And if, R 2 / R 1 =* G*Rg

Then, V 2 =0

Due to the imperfections of circuit components, the voltage-to-current converter 206 and/or the buffer 218 may introduce errors into the output signal at the output node 204 of the amplifier circuit 200 . These errors can include gain errors, DC offset, distortion, and/or other types of errors. These errors can be modeled as an error current Ie added to I 1 . In this case:

I 1 =(− k*V in)+ Ie

V 1 =(− I*Rg )+( Ie*Rg ) +V 2

V out= G*V 1 =−( G*I 1 * Rg )+( G *(( Ie*Rg )+ V 2 ))=−( G*k*V in* Rg )+( G *(( Ie*Rg )+ V 2 ))

Also, V out=−( R 2 / R 1 )*Vin

So, −( R 2 / R 1 )* V in=−( G*k*V in* Rg )+( G *(( Ie*Rg )+ V 2 )

And if, R 2 / R 1 = G*k*Rg

Then V 2 =− Ie*Rg

Consequently, the architecture of the amplifier circuit 200 reduces the error in the output signal at the output node 204 of the amplifier circuit 200 , while providing good AC and DC characteristics.

The amplifier circuit may also include a correction limiting resistive element 350 that has a first end 352 and a second end 354 , as illustrated by the amplifier circuit 300 in FIG. 3 . In some embodiments the element 350 may be replaced with a combination of resistive and non resistive elements, for example, capacitive, inductive, and/or active elements. The first end 352 of the correction limiting resistive element 350 is coupled to the output 210 of the voltage-to-current converter 206 , and the second end 354 of the correction limiting resistive element 350 is coupled to ground 244 . The correction limiting resistive element 350 provides an alternative current path to ground 344 and thereby limits the amount of error correction caused by the error amplifier output voltage V 2 .

B. Second Example of Amplifier

The amplifier circuit 400 illustrated in FIG. 4 is an example of another embodiment of the invention. The amplifier circuit 400 includes an amplifier input node 402 , which may be referred to as an input node or as a power amplifier input, and an amplifier output node 404 , which may be referred to as an output node or as a power amplifier output. The amplifier circuit 400 includes a first voltage-to-current converter 406 that has an input 408 and an output 410 . The input 408 of the first voltage-to-current converter 406 is coupled to the input node 402 . The output 410 of the first voltage-to-current converter 406 generates a current I 41 (which may be referred to as a first intermediate current), that is proportional to the input voltage V 41 at the input node 402 . The amplifier circuit 400 also includes a first current mirror 412 that has an input 414 and an output 416 . The input 414 of the first current mirror 412 is coupled to the output 410 of the first voltage-to-current converter 406 . The output 416 of the first current mirror 412 generates a current I 43 that is proportional to the input voltage at the input node 402 , wherein the, current I 43 has a polarity that is opposite to the polarity of the current I 41 . The amplifier circuit 400 also includes a second voltage-to-current converter 418 that has an input 420 and an output 422 . The input 420 of the second voltage-to-current converter 418 is coupled to the input node 402 . The output 422 of the second voltage-to-current converter 418 generates a current I 42 (which may be referred to as a second intermediate current), that is proportional to the input voltage at the input node 402 . The polarity of the current I 42 is opposite to the polarity of the current I 41 . The amplifier circuit 400 also includes a second current mirror 424 that has an input 426 and an output 428 . The input 426 of the second current mirror 424 is coupled to the output 422 of the second voltage-to-current converter 418 . The output 428 of the second current mirror 424 generates a current I 44 that is proportional to the input voltage at the input node 402 , wherein the current I 44 has a polarity that is opposite to the polarity of the current I 42 and opposite to the polarity of the current I 43 . This arrangement of using two current mirrors in a balanced circuit configuration beneficially,reduces power dissipation and reduces even-order distortion.

Additionally, the amplifier circuit 400 includes a feed-forward resistive element 430 that has a first end 432 and a second end 434 , and a buffer 436 that has an input 437 and an output 438 . The buffer 436 may also be referred to as an output buffer. The output 438 of the buffer 436 is coupled to the amplifier output node 404 , and the input 437 of the buffer 436 is coupled to the first end 432 of the feed-forward resistive element 430 . The output 416 of the first current mirror 412 and the output 428 of the second current mirror 424 are coupled to the first end 432 of the feed forward resistive element 430 and to the input 437 of the buffer 436 . Currents I 43 ′ and I 44 ′ flow through the feed-forward resistive element 430 to generate a voltage V 43 at the first end 432 of the feed-forward resistive element 430 that is proportional to I 43 ′ minus I 44 ′. Due to some current loss at the input 437 of the buffer 436 , current I 43 ′ is slightly smaller than current I 43 , and current I 44 ′ is slightly smaller than current I 44 .

The amplifier circuit 400 further includes an input resistive element 442 that has a first end 444 and a second end 446 . The first end 444 of the input resistive element 442 is coupled to the input node 402 . The amplifier circuit 400 also includes a feedback resistive element 448 that has a first end 450 and a second end 452 . The first end 450 of the feedback resistive element 448 is coupled to the output 438 of the buffer 436 . The amplifier circuit 400 further includes an operational amplifier 454 that has an inverting input 456 , a noninverting input 458 , and an output 460 . The inverting input 456 is coupled to the second end 446 of the input resistive element 442 and to the second end 452 of the feedback resistive element 448 , and the noninverting input 458 is coupled to ground 462 . An error amplifier input voltage is produced at the inverting input 456 of the operational amplifier 454 . The output 460 of the operational amplifier 454 is coupled to the second end 434 of the feed-forward resistive element 430 . An error correction voltage V 42 is generated at the output 460 of the operational amplifier 454 . The total voltage at the input 437 of the buffer 436 is the sum of the voltage V 43 generated across the feed-forward impedance element 430 by the currents I 43 ′ and I 44 ′, and the error correction voltage V 42 . The amplifier circuit 400 may also include a buffer input node 464 coupled to the buffer input 437 , and an error amplifier output node 466 coupled to the output 460 of the operational amplifier 454 .

The amplifier circuit 400 may also include an inverting input buffer 468 . The inverting input buffer 468 includes an input buffer operational amplifier 470 that has an inverting input 472 , a noninverting input 474 , and an output 476 . The inverting input buffer 468 also includes a feedback resistor 478 that has a first end 480 that is coupled to the output 476 of the input buffer operational amplifier 470 , and that has a second end 482 that is coupled to the inverting input 472 of the input buffer operational amplifier 470 . The inverting input buffer 468 also includes an input resistor 484 that has a first end 486 that is coupled to an input buffer input node 490 , and a second end 488 that is coupled to the inverting input 472 of the input buffer operational amplifier 470 . The noninverting input 474 of the input buffer operational amplifier 470 is coupled to ground 462 . The output 476 of the input buffer operational amplifier is coupled to the amplifier input node 402 . The inverting input buffer 468 buffers the input to the amplifier circuit 400 , and also inverts the input signal so that the signal at the output 404 of the amplifier circuit 400 will not be inverted with respect to the signal at the inverting input buffer input node 490 .

The amplifier circuit 400 may also include a correction limiting resistive element (not shown) that has a first end coupled to the first end 432 of the feed-forward resistive element 430 , and a second end coupled to ground 462 .

C. Voltage-to-Current Converter

An illustrative embodiment of a voltage-to-current converter (V/I converter) 500 is illustrated in FIG. 5 . V/I converter 500 includes an operational amplifier 502 , a resistor R 1 , a transistor Q 1 , and a voltage reference source Vref. As an example, the operational amplifier 502 may be a model number NE5532, the resistor R 1 may have a value of about 2 k ohms, and the value of the reference voltage Vref may be about 0.5 Vcc. Transistor Q 1 is chosen to have sufficient beta, and as an example, is a Darlington transistor. As an example, Vcc may be between about 9V and about 15V, however, smaller or larger voltages could be used. In balanced circuits, a negative supply voltage Vee may also be used, which may be between about −9V and about −15V, however, smaller or larger voltages could be used.

Additional details of an illustrative embodiment of a V/I converter are shown in the V/I converter 600 illustrated in FIG. 6 . V/I converter 600 includes resistors R 2 , R 3 , and R 4 , and transistors Q 2 , Q 3 , Q 4 , and Q 5 . As an example, resistor R 2 may have a value of about 10 k ohms, resistor R 3 may have a value of about 5 k ohms, and resistor R 4 may have a value of about 2 k ohms, and the value of the voltage reference Vref may be about 0.5 Vcc. The transistors are chosen to have sufficient beta, and as an example, transistors Q 2 and Q 3 are a matched pair and are each Darlington transistors. Alternatively, JFET transistors could be used.

For best performance in the V/I converter circuits, Vref=½ Vcc, and Vin<Vref; then, I 1 =Vref/R 1 .

D. Current Mirror

An illustrative embodiment of a current mirror circuit 700 is illustrated in FIG. 7 . Current mirror 700 includes resistors R 5 and R 6 , and transistors Q 6 , Q 7 , and Q 8 . As an example, resistors R 5 and R 6 may have values from about 0 ohms to about 1 k ohms, and may have the same value. The voltages across resistors R 5 and R 6 are substantially equal when the value of resistor R 5 equals the value of resistor R 6 . Current gain can be provided if the values of the resistors R 5 and R 6 are not the same. The transistors are chosen to have sufficient beta, and as an example, transistors Q 7 and Q 8 are a matched pair. Transistor Q 6 is included to reduce beta errors. As an example, Vee may be about −25V to about −150V, however smaller or larger voltages could be used. The current ratio is: I 1 *R 1 =I 2 *R 2 ; and I 2 /I 1 =R 1 /R 2 .

E. Output Buffer

An illustrative embodiment of an output buffer circuit 800 is illustrated in FIG. 8 . Output buffer 800 is shown coupled to first current mirror 802 and second current mirror 804 . Output buffer 800 includes resistors R 7 , R 8 , R 9 , R 10 , R 11 , R 12 , R 13 , R 14 , R 15 , R 16 , and R 17 , and transistors Q 9 , Q 10 , Q 11 , Q 12 , Q 13 , and Q 14 . An output 806 of the first current mirror 802 is coupled to a first current input 808 of the output buffer 800 . The first current input 808 is coupled to the collector of transistor Q 9 and to the base of transistor Q 11 . An output 810 of the second current mirror 804 is coupled to a second current input 812 of the output buffer 800 . The second current input 812 is coupled to the collector of transistor Q 10 and to the base of transistor Q 12 . In the example of the output buffer 800 shown in FIG. 8, the first current mirror 802 and the second current mirror 804 are coupled to an example of bias circuitry in the output buffer 800 . The bias circuitry includes transistors Q 9 and Q 10 , and resistors R 7 , R 8 , and R 9 . However, in other embodiments the outputs 806 , 810 of the current mirrors 802 , 804 do not have to be coupled to bias circuitry, and as shown in the amplifier circuit 400 in FIG. 4, can be coupled to the first end 432 of the feed forward resistive element 430 . In some embodiments, bias circuitry can be omitted, or alternatively, bias circuitry can be included but is not coupled to the current mirror outputs. When the outputs 806 , 810 of the current mirrors 802 , 804 are coupled to bias circuitry, a small portion of the output currents I 3 and I 4 from the current mirrors 802 , 804 are used in the bias circuitry, leaving the remaining portion of the currents from the current mirrors 802 , 804 to flow through the feed forward resistive element 430 , after flowing through the input Vin of the output buffer.

As an example, R 7 may have a value of about 200 ohms, R 8 may have a value of about 5 k ohms, R 9 may have a value of about 200 ohms, R 10 may have a value of about 200 ohms, R 11 may have a value of about 15 ohms, R 12 may have a value of about 15 ohms, R 13 may have a value of about 200 ohms, R 14 may have a value of about 0.15 ohms, R 15 may have a value of about 0.15 ohms, R 16 may have a value of about 0.15 ohms, and R 17 may have a value of about 0.15 ohms. Transistors Q 9 and Q 10 function as bias transistors, transistors Q 11 and Q 12 function as drivers, and transistors Q 13 and Q 14 are output power transistors. All of the transistors are chosen to have sufficient beta. As an example, transistors Q 11 and Q 12 are medium power driver transistors. As an example, output transistors Q 13 and Q 14 are high voltage, high power transistors. Additional output power transistors may be included in parallel with transistors Q 13 and Q 14 . As an example, Vhcc may be between about 25V and about 150V, and Vhee may be between about −25V and about −150V, however, larger or smaller voltages could be used.

As an example, transistors Q 9 and Q 11 are the same part number and are chosen to be as identical as possible. Similarly, as an example, transistors Q 10 and Q 12 are the same part number and are chosen to be as identical as possible. Transistors Q 9 and Q 11 may be physically attached to each other, and transistors Q 10 and Q 12 may be physically attached to each other, so that the temperatures of the attached transistors will be about the same when the transistors heat up during operation, so that the temperature-dependent performance characteristics of the attached transistors will be about the same at any time during operation, such that the operating point of the output stage remains sufficiently constant. FIG. 9A shows an illustrative example of transistors Q 9 and Q 11 physically attached to each other, and FIG. 9B shows an illustrative example of transistors Q 10 and Q 12 physically attached to each other.

A. First Example of Operation

In addition to the various hardware embodiments described above, a different aspect of the invention concerns a method for amplifying an electronic signal. FIG. 10 shows a sequence 1000 for a method for amplifying a voltage, to illustrate one example of the method aspect of the present invention. For ease of explanation, but without any intended limitation, the example of FIG. 10 is described in the context of the amplifier circuit 200 described above, and wherein the feed-forward impedance element 212 , the feedback impedance element 230 , and the error amplifier input impedance element 224 are all resistors. The sequence 1000 , is initiated with step 1002 , wherein an input voltage is coupled to the amplifier input 202 . In step 1004 , a first current is generated by the V/I converter 206 that is proportional to the input voltage. In step 1006 , a first voltage V/I is generated that is proportional to the first current. The first voltage V 1 is generated at the first end 214 of the feed-forward impedance element 212 , by the current I 1 from the output 210 of the V/I converter 206 flowing through the feed-forward impedance element 212 . The first voltage V 1 and the input voltage at the input node 202 may have opposite polarity. In step 1008 , the amplifier input 202 is coupled to the amplifier output 204 through the error amplifier input impedance element 224 and the feedback impedance element 230 , wherein the second end 228 of the error amplifier input impedance element 224 and the second end 234 of the feedback impedance element 230 are connected at the inverting input 238 of the error amplifier 236 . In step 1010 , an error amplifier input voltage is generated at the inverting input 238 of the error amplifier 236 by a current flowing through the error amplifier input impedance element 224 and the feedback impedance element 230 . In step 1012 an error amplifier output voltage V 2 is produced, wherein the error amplifier output voltage is proportional to the error amplifier input voltage. In step 1014 the error amplifier output voltage V 2 is added to the first voltage V 1 , wherein the first voltage V 1 is the voltage generated across the feed-forward impedance element 212 by the current I 1 . In step 1016 , an output voltage is produced by the buffer 218 at the amplifier output 204 , wherein the output voltage is substantially proportional to the sum of the error amplifier output voltage V 2 and the first voltage V 1 .

B. Second Example of Operation

FIG. 11 shows a sequence 1100 for another method for amplifying a voltage, to illustrate another example of the method aspect of the present invention. For ease of explanation, but without any intended limitation, the example of FIG. 11 is described in the context of the amplifier circuit 400 described above. The sequence 1100 , is initiated with step 1102 , wherein an input voltage is coupled to the amplifier input node 402 .

The sequence 1110 may also include step 1104 , in which the input voltage is inverted by utilizing the inverting input buffer 468 .

The sequence 1100 may also include steps 1106 and 1108 described as follows. In step 1106 , a first intermediate current I 41 is generated by the first V/I converter 406 , wherein the first intermediate current I 41 is proportional to the input voltage. In step 1108 , a second intermediate current I 42 is generated by the second V/I converter 418 , wherein the second intermediate current I 42 is proportional to the input voltage.

In step 1110 a first current I 43 that is proportional to the input voltage, is generated by the first current mirror 412 . The polarity of the first current I 43 is opposite to the polarity of the first intermediate current I 41 . In step 1112 , a second current I 44 that is proportional to the input voltage, is generated by the second current mirror 424 . The polarity of the second current I 44 is opposite to the polarity of the first current I 43 , and is opposite to the polarity of the second intermediate current I 42 . In step 1114 , a first voltage V 43 is generated that is substantially proportional to the first current I 43 minus the second current I 44 . The first voltage V 43 is generated at the first end 432 of the feed-forward resistive element 430 , by the current I 43 ′ minus the current I 44 ′ flowing through the feed-forward resistive element 430 . In step 1116 , the amplifier input node 402 is coupled to the amplifier output node, 404 through the input resistive element 442 and the feedback resistive element 448 , wherein the second end 446 of the input resistive element 442 and the second end 452 of the feedback resistive element 448 are connected at the inverting input 456 of the operational amplifier 454 . In step 1118 an error amplifier input voltage is generated at the inverting input 456 of the operational amplifier 454 , by a current flowing through the input resistive element 442 and the feedback resistive element 448 . In step 1120 , an error amplifier output voltage V 42 (the output voltage of the operational amplifier 454 ) is produced at the output 460 of the operational amplifier 454 , wherein the error amplifier output voltage is proportional to the voltage at the inverting input 456 of the operational amplifier 454 . In step 1122 , the error amplifier output voltage V 42 is added to the first voltage V 43 , by applying the error amplifier output voltage V 42 to the second end 434 of the feed-forward resistive element 430 . In step 1124 , an output voltage is produced by the buffer 436 at the amplifier output node 404 , wherein the output voltage is substantially proportional to the sum of the error amplifier output voltage V 42 and the first voltage V 43 .

While the foregoing disclosure shows a number of illustrative embodiments of the invention, it will be apparent to those skilled in the art that various changes and modifications can be made herein without departing from the scope of the invention as defined by the appended claims. Furthermore, although elements of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.