Simultaneous bidirectional signal subtraction

Data may be transmitted between devices using many signaling protocols. According to a simultaneous bidirectional signaling protocol, a first device transmits signals to a second device over a signal line and also receives signals from the second device over the signal line. Since the same signal line carries both signals, each device requires a technique to distinguish the signal transmitted by the device from the signal transmitted to the device.

A device may distinguish a first signal transmitted by the device from a second signal transmitted to the device by subtracting the first signal from a composite signal that is present on the signal line. According to this technique, the device receives the composite signal from the signal line, subtracts a duplicate version of the first signal from the composite signal using capacitor-based subtraction circuits, and outputs the result of the subtraction. The result is intended to be substantially identical to the second signal transmitted to the device.

However, the above-mentioned capacitor-based subtraction circuits yield approximately 6 dB of attenuation and are often unable to operate at desired data rates.

FIG. 1 is a diagram illustrating a single-ended simultaneous bidirectional signaling system according to some embodiments.

FIG. 2 is a diagram of a subtraction circuit according to some embodiments.

FIG. 3 is a diagram of a current driver adapted to transmit a single-ended data signal according to some embodiments.

FIG. 4 is a diagram illustrating a differential-mode simultaneous bidirectional signaling system according to some embodiments.

FIG. 5 is a diagram of a subtraction circuit according to some embodiments.

FIG. 6 is a diagram of a current driver adapted to transmit a differential-mode data signal according to some embodiments.

FIG. 7 is a block diagram of a system according to some embodiments.

Single-Ended Example

FIG. 1 is a diagram illustrating a single-ended simultaneous bidirectional signaling system according to some embodiments. FIG. 1 shows transceiver 10 coupled to transceiver 20 via signal line 30 . In some embodiments, transceiver 10 and transceiver are located within respective integrated circuit packages. Each of transceiver 10 and transceiver 20 may be elements of any system adapted to communicate according to a simultaneous bidirectional signaling protocol. As described above, transceiver 10 is therefore adapted to transmit signals to transceiver 20 and to receive signals from transceiver 20 over signal line 30 . Transceiver 20 is also adapted to transmit signals to transceiver 10 and to receive signals therefrom over signal line 30 .

Turning to the illustrated elements of transceiver 10 , transmitter 11 is adapted to receive data to be transmitted. The data is binarily-encoded in a voltage signal according to some embodiments, and transmitter 11 comprises a voltage-to-current converter to convert the voltage signal to a current signal. The current signal is transmitted to signal line 30 and contributes to voltage signal V line across termination resistor 31 . In this regard, an impedance of termination resistor 31 may match an impedance of signal line 31 so as to reduce reflections within signal line 30 .

Replica driver 12 also receives a voltage signal that binarily encodes the data to be transmitted. Replica driver 12 is, in some embodiments, a voltage-to-current converter substantially identical to transmitter 11 . Accordingly, replica driver 12 is adapted to convert the received voltage signal to a current signal and to output the current signal, which in turn develops voltage signal V data across resistor 13 . Voltage signals V line and V data thereby both represent the data to be transmitted.

Voltage signal V line also represents data transmitted to transceiver 10 by transceiver 20 over signal line 30 . Specifically, transceiver 20 also transmits a current signal encoding binary data over signal line 30 . The transmitted current signal contributes to a voltage across resistor 31 as does the current signal transmitted by transmitter 11 . Voltage signal V line therefore represents both the data transmitted by and the data transmitted to transceiver 10 .

Subtraction circuit 14 is adapted to receive voltage signals V line and V data . More particularly, subtraction circuit 14 is adapted to convert V line to a first current signal, to convert V data to a second current signal, and to generate an output signal based on the second current signal and the first current signal. Since V line represents data transmitted by transceiver 10 as well as data transmitted by transceiver 20 , and since V data substantially represents the data transmitted from transceiver 10 , the generated output signal substantially represents the data transmitted by transceiver 20 . In other words, subtraction circuit 14 decodes V line so as to substantially obtain a signal representing data transmitted by transceiver 20 . The data transmitted by transceiver 20 may therefore be determined in some embodiments from the generated output signal.

Receiver 15 is adapted to receive the output signal from subtraction circuit 14 . Receiver 15 may comprise a latch to store the output signal and to output the signal in response to a clock pulse. Receiver 15 may also be adapted to amplify the output signal to a desired signaling level.

Although the elements of transceiver 20 appear identical to the elements of transceiver 10 , in some embodiments transceiver 20 may comprise any system adapted to provide simultaneous bidirectional signaling services.

FIG. 2 is a diagram of subtraction circuit 14 according to some embodiments. Subtraction circuit 14 comprises bias current source 40 coupled to resistor 41 and resistor 42 . Resistor 41 and resistor 42 are also coupled, respectively, to a source terminal of p-channel metal oxide semiconductor (PMOS) transistor 43 and PMOS transistor 44 . A gate terminal of transistor 43 is coupled to an output line of transmitter 11 . Accordingly, voltage signal V line is applied to the gate terminal of transistor 43 . A reference voltage signal V ref is applied to a gate terminal of transistor 44 .

By virtue of the illustrated configuration, current signals are output via drain terminals of transistors 43 and 44 . The current signal output via the drain terminal of transistor 44 represents the data that is represented by voltage signal V line . The current signal output via the drain terminal of transistor 43 also represents data that is represented by voltage signal V line , but is reverse-polarized with respect to the current signal output via the drain terminal of transistor 44 and a value of bias current source 40 .

Subtraction circuit 14 also includes bias current source 50 . Bias current source 50 is coupled to resistor 51 and resistor 52 , which are respectively coupled to a source terminal of PMOS transistor 53 and PMOS transistor 54 . A gate terminal of transistor 53 is coupled to an output line of replica transmitter 12 . Accordingly, voltage signal V data is applied to the gate terminal of transistor 53 . A reference voltage signal V ref is applied to a gate terminal of transistor 54 .

Drain terminals of transistors 53 and 54 output current signals corresponding to voltage signal V data . As described above with respect to voltage signal V line , the current signal output via the drain terminal of transistor 54 represents data that is represented by voltage signal V data . The current signal output via the drain terminal of transistor 53 is a reverse-polarized version of the current signal output via the drain terminal of transistor 54 , and therefore also represents data that is represented by voltage signal V data .

The drain terminal of transistor 44 is coupled to the drain terminal of transistor 53 at a node and line 60 is in turn coupled to the node. Since combining two currents onto a single line results in an addition of the two currents, line 60 carries a current signal equal to a sum of the two current signals output from the drain terminal of transistor 44 and the drain terminal of transistor 53 . Moreover, because the current signal output from the drain terminal of transistor 53 is a reverse-polarized representation of the current signal output via the drain terminal of transistor 54 , the current signal carried by line 60 is substantially equal to a difference between the current signal output from the drain terminal of transistor 44 and the current signal output via the drain terminal of transistor 54 .

The current signal output via the drain terminal of transistor 54 represents the data input to transmitter 12 , and the current signal output from the drain terminal of transistor 44 represents both the data input to transmitter 11 and the data transmitted by transceiver 20 . Accordingly, a difference between these two current signals is a current signal representing the data transmitted by transceiver 20 .

Line 65 carries a sum of the two current signals output from the drain terminal of transistor 43 and the drain terminal of transistor 54 . Again, the current signal output from the drain terminal of transistor 43 is a reverse-polarized current signal converted from voltage signal V line (encoding the data input to transmitter 11 and the data transmitted by transceiver 20 ), while the current signal output from the drain terminal of transistor 54 is a current signal converted from voltage signal V data (encoding the data transmitted from transceiver 20 ). Consequently, the summed current signal carried by line 65 is a reverse-polarized current signal that represents the data transmitted by transceiver 20 .

Lines 60 and 65 are coupled to receiver 15 . Receiver 15 may comprise a current latch adapted to amplify the currents received from lines 60 and 65 to an appropriate signaling level. As such, receiver 15 amplifies a difference between the two received currents. The amplified difference output from receiver 15 therefore represents the data transmitted by transceiver 20 . In some embodiments, receiver 15 comprises subtraction circuit 14 .

FIG. 3 illustrates a current driver adapted to transmit a single-ended data signal according to some embodiments. The illustrated current driver may be used by transmitter 11 and/or replica driver 12 . Of course, other current drivers may be used in accordance with some embodiments.

The illustrated current driver includes bias current source 70 coupled to a source terminal of PMOS transistor 71 . A voltage signal of binarily-encoded data to be transmitted is applied to a gate terminal of transistor 71 , and resistor 72 is coupled to a drain terminal. Similarly, a source terminal of PMOS transistor 73 is coupled to bias current source 70 , a gate terminal of transistor 73 is coupled to a reference voltage signal V ref , and a drain terminal is coupled to resistor 74 . Each of resistors 72 and 74 are also coupled to ground.

Upon application of a voltage signal representing data to the gate terminal of transistor 71 , a corresponding current signal is emitted from the drain terminal of transistor 71 . In a case that FIG. 3 illustrates transmitter 11 , resistor 72 corresponds to resistor 31 and voltage signal V line is developed at node 75 . Similarly, resistor 72 corresponds to resistor 13 and voltage signal V data is developed at node 75 in a case that FIG. 3 illustrates replica transmitter 12 .

Differential-Mode Example

FIG. 4 illustrates a differential-mode simultaneous bidirectional signaling system according to some embodiments. FIG. 4 shows transceiver 100 coupled to transceiver 200 via differential signal lines 300 and 305 . As described with respect to FIG. 1 , transceiver 100 and transceiver 200 may be located on respective integrated circuit packages and may be elements of any system adapted to communicate according to a simultaneous bidirectional signaling protocol.

Transmitter 110 of transceiver 100 is adapted to receive data to be transmitted. The data is encoded in two voltage signals carried by respective differential signal lines to transmitter 110 . In some embodiments, transmitter 110 comprises a voltage-to-current converter to convert the voltage signals to differential current signals that also encode the data. The current signals are transmitted to signal lines 300 and 305 , and therefore develop voltage signals V line and V line# across respective termination resistors 310 and 315 . As mentioned above, impedances of termination resistors 310 and 315 may match impedances of the signal line to which they are respectively coupled so as to reduce reflections within the signal line.

Replica driver 120 is adapted in some embodiments to receive the differential voltage signals encoding the data, to convert the received voltage signals to differential current signals encoding the data, and to output the current signals. The output current signals develop voltage signals V data and V data# across respective resistors 130 and 135 . Differential voltage signal pairs (V line , V line# ) and (V data , V data# ) thereby both represent the data to be transmitted. Voltage signal pair (V line , V line# ), however, also represents data transmitted to transceiver 100 by transceiver 200 over signal lines 300 and 305 .

Subtraction circuit 140 is adapted to receive differential voltage signal pairs (V line , V line# ) and (V data , V data# ). Subtraction circuit 140 is further adapted to convert V line to a first current signal, to convert V data to a second current signal, to convert V line# to a third current signal, and to convert V data# to a fourth current signal, and to generate two differential-mode current output signals respectively based on the first and second current signals and on the third and fourth current signals. The two output signals, in conjunction with one another, represent the data transmitted by transmitter 110 . As similarly described with respect to FIG. 1 , the voltage signal pair (V line , V line# ) represents data transmitted by transceiver 100 as well as data transmitted by transceiver 200 . Since voltage signal pair (V data , V data# ) substantially represents the data transmitted from transceiver 100 , the differential-mode current output signal pair (V line -V data , V line# -V data# ) substantially represents the data transmitted by transceiver 200 .

Receiver 150 is adapted to receive the differential-mode output signals from subtraction circuit 140 . Receiver 150 may comprise a latch to amplify the output signals to a desired signaling level, to store the output signals and to output the signals in response to a differential-mode clock.

FIG. 5 is a diagram of subtraction circuit 140 according to some embodiments. Subtraction circuit 140 comprises bias current source 400 coupled to resistor 410 and to resistor 420 , which are respectively coupled to a source terminal of PMOS transistor 430 and PMOS transistor 440 . A gate terminal of transistor 430 is coupled to an output line of transmitter 110 such that voltage signal V line is applied to the gate terminal of transistor 430 . A gate terminal of transistor 440 is coupled to another output line of transmitter 110 , therefore voltage signal V line# is applied to the gate terminal of transistor 440 .

The illustrated circuit outputs current signals from drain terminals of transistors 430 and 440 . The current signal output via the drain terminal of transistor 440 represents voltage signal V line , and the current signal output via the drain terminal of transistor 430 is a reverse-polarized representation of voltage signal V line# .

Bias current source 500 of subtraction circuit 140 is coupled to resistor 510 and resistor 520 , which are respectively coupled to a source terminal of PMOS transistor 530 and PMOS transistor 540 . A gate terminal of transistor 530 is coupled to an output line of replica transmitter 120 such that voltage signal V data is applied to the gate terminal. Another output line of transmitter 110 is coupled to a gate terminal of transistor 540 , and voltage signal V data# is therefore applied to the gate terminal of transistor 540 .

Drain terminals of transistors 530 and 540 output current signals corresponding to voltage signals V data and V data# . Specifically, the current signal output via the drain terminal of transistor 530 represents voltage signal V data# , and the current signal output via the drain terminal of transistor 540 is a reverse-polarized representation of voltage signal V data .

The drain terminal of transistor 430 is coupled to the drain terminal of transistor 530 at a node and line 600 is in turn coupled to the node. Accordingly, line 600 carries a current signal equal to a sum of the two current signals output from the two drain terminals. The current signal output from the drain terminal of transistor 430 is a reverse-polarized current signal converted from voltage signal V line# , which represents one differential portion of the data input to transmitter 110 and the data transmitted by transceiver 200 , while the current signal output from the drain terminal of transistor 530 is a current signal converted from voltage signal V data# (representing one differential portion of the data transmitted by transceiver 200 ). Consequently, the summed current signal carried by line 600 is a reverse-polarized current signal that represents one of the differential data signals transmitted by transceiver 200 .

Line 650 carries a sum of the two current signals output from the drain terminal of transistor 440 and the drain terminal of transistor 540 . Again, the current signal output from the drain terminal of transistor 440 is converted from voltage signal V line (representing a second differential portion of the data input to transmitter 110 and the data transmitted by transceiver 200 ), while the current signal output from the drain terminal of transistor 540 is a current signal converted from voltage signal V data (representing a second differential portion of the data transmitted by transceiver 200 ). The summed current signal carried by line 650 is therefore a current signal representing a second one of the differential data signals transmitted by transceiver 200 . As a result, lines 600 and 650 carry current signals that represent the differential data transmitted by transceiver 200 .

Lines 600 and 650 are coupled to receiver 150 . As described above, receiver 150 may comprise a current latch adapted to amplify a difference between the currents received from lines 600 and 650 to an appropriate signaling level, and may output the amplified signals in accordance with an input differential clock signal. The amplified difference thereby represents the data transmitted by transceiver 200 .

FIG. 6 illustrates a current driver adapted to transmit a differential-mode data signal according to some embodiments. The illustrated current driver may be used by transmitter 110 and/or replica driver 120 . Of course, other differential-mode current drivers may be used in accordance with some embodiments.

The illustrated current driver includes bias current source 700 coupled to a source terminal of PMOS transistor 710 . Resistor 720 is coupled to a drain terminal of transistor 710 . A source terminal of PMOS transistor 730 is also coupled to bias current source 700 , and a drain terminal is coupled to resistor 740 . Each of resistors 720 and 740 are also coupled to ground.

Voltage signals that represent differential-mode data are applied to gate terminals of transistors 710 and 730 . The gate terminal of transistor 710 receives a voltage signal encoding data, while the gate terminal of transistor 720 receives a voltage signal encoding data#. Consequently, a current signal representing data# is emitted from the drain terminal of transistor 710 , and a current signal representing data is emitted from a drain of transistor 730 . In a case that FIG. 6 illustrates transmitter 110 , resistor 720 corresponds to resistor 310 and resistor 740 corresponds to resistor 315 . Voltage signal V line is therefore developed at node 760 , with voltage signal V line# being developed at node 750 . If FIG. 6 illustrates replica transmitter 120 , resistor 720 corresponds to resistor 130 , resistor 740 corresponds to resistor 135 , voltage signal V data is developed at node 760 , and voltage signal V data# is developed at node 750 .

FIG. 7 illustrates a block diagram of system 800 according to some embodiments. System 800 includes integrated circuit 802 comprising sub-blocks such as arithmetic logic unit (ALU) 804 , on-die cache 806 and transceiver 100 of FIG. 4 . Integrated circuit 802 may be a microprocessor or another type of integrated circuit. Integrated circuit 802 may also communicate with system memory 808 through transceiver 100 , a host bus and chipset 810 . According to some embodiments, integrated circuit 802 also communicates with off-die cache 812 through transceiver 100 . Other off-die functional units, such as graphics controller 814 and Network Interface Controller (NIC) 816 , may communicate with integrated circuit 802 via appropriate busses or ports.

Thus, embodiments may reduce attenuation of received data signals in simultaneous bidirectional signaling schemes.

The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known current drivers, voltage-to-current converters, transmitters and/or receivers. Moreover, the ground-referenced PMOS transistors described herein may be substituted with V cc -referenced n-channel metal oxide semiconductor transistors. Therefore, persons skilled in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.