Apparatus for measuring capacitance of a semiconductor device

1. Technical Field

The present invention relates to capacitance measurements in general, and in particular to an apparatus for measuring capacitance. Still more particularly, the present invention relates to an apparatus for measuring capacitance of a semiconductor device.

2. Description of the Related Art

Fundamentally,

C=Q/V   (1)

where

C=capacitance of a capacitor;

Q=charge within the capacitor; and

V=voltage across the capacitor.

Thus, if a known amount of charge is placed within a capacitor, the capacitance of the capacitor can be determined by measuring the voltage across the capacitor. However, if charges are placed on the capacitor and are then dumped to ground in a cyclical fashion, a discharge current can be formed as follows:

I=QF   (2)

where

I=discharge current;

Q=charge within the capacitor; and

F=frequency of the charge/discharge cycle.

By combining equations (1) and (2),

C=I /( VF )  (3)

Hence, an accurate capacitance measurement of a capacitor can be obtained by monitoring the discharge current if the voltage and frequency are maintained constant.

A circuit for measuring capacitance of a semiconductor device typically includes a pair of transistors driven by a stable frequency oscillator. The pair of transistors are turned on and off alternately, with one transistor being arranged to charge the semiconductor device to a known voltage and the other transistor being arranged to discharge the semiconductor device to zero voltage. The discharge current is monitored to provide a measure of the capacitance of the semiconductor device.

However, the capacitance of the semiconductor device being measured may be influenced or overshadowed by the parasitic elements, such as parasitic capacitance, parasitic inductance and/or parasitic resistance, which inherently existed between the capacitance measuring circuit and the semiconductor device. As a result, the capacitance measurement may not be as accurate as it should be. Consequently, it is desirable to provide an improved apparatus for measuring capacitance of a semiconductor device.

In accordance with a preferred embodiment of the present invention, a capacitance measuring circuit includes a signal source circuit, a first transistor, a second transistor, and bypass capacitor. The first transistor is connected in series with the second transistor, and the second transistor is connected in series with a device under test. The bypass capacitor connected in parallel with the first and second transistors. Coupled to the first and second transistors, the signal source circuit generates a first signal and a second signal to alternately turn on said first and second transistors such that a discharge current is generated to flow through the first and second transistors.

All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a first embodiment of the present invention;

FIG. 2 is a circuit diagram of the signal source circuit within the apparatus from FIG. 1, in accordance with a preferred embodiment of the present invention;

FIG. 3 is a circuit diagram of the delay circuit within the signal source circuit from FIG. 2, in accordance with a preferred embodiment of the present invention;

FIG. 4 is a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a second embodiment of the present invention; and

FIG. 5 is a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a third embodiment of the present invention.

Referring now to the drawings and, in particular, to FIG. 1, there is depicted a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a first embodiment of the present invention. As shown, a signal source circuit 11 , an n-channel transistor Q 1 , a p-channel transistor Q 2 , and a device under test (DUT) C 1 are formed within a single semiconductor structure 10 . The current passing through transistors Q 1 and Q 2 is measured by a current meter 12 located external to semiconductor structure 10 . Similarly, the frequency output from signal source circuit 11 is measured by a frequency meter 13 located external to semiconductor structure 10 .

Signal source circuit 11 generates signals S 1 and S 2 for turning transistors Q 1 , Q 2 on and off alternately. The frequency of signal S 1 or signal S 2 should be the same as the frequency of signal F. Signals S 1 and S 2 preferably have some or all of the following properties:

1. square waves that are 180 degrees out of phase from each other;

2. underlapped from each other so that transistors Q 1 , Q 2 are never turned on at the same time;

3. the high value of signals S 1 and S 2 is different than the supply voltage VCC_BAR (higher for better drive, lower for process limits); and

4. the low value of signals S 1 and S 2 is lower than that of supply voltage VCC_BAR (to reduce leakage of current through an “off” device).

Initially, DUT C 1 is charged to a supply voltage VCC_BAR by having transistor Q 2 turned on and transistor Q 1 turned off. Transistor Q 2 acts as a resistor when DUT C 1 is being charged. After DUT C 1 has reached the supply voltage VCC_BAR, transistor Q 2 is turned off and transistor Q 1 is turned on to allow the charges stored within DUT C 1 to be drained to ground. The above-mentioned charge/discharge cycle is repeated many times per second to provide a steady discharge current that can be measured by current meter 12 .

With reference now to FIG. 2, there is depicted a circuit diagram of signal source circuit 11 , in accordance with a preferred embodiment of the present invention. As shown, signal source circuit 11 includes an NAND gate 16 and six inverters 21 - 26 serially connected in a ring oscillator configuration. NAND gate 16 includes an Enable input to initiate an oscillation within signal source circuit 11 . Signal source circuit 11 also includes an NOR gate 19 to yield signal S 2 , and an NAND gate 17 along with buffers 27 - 28 to yield signal S 1 . As mentioned previously, signals S 1 and S 2 turn transistors Q 1 and Q 2 (from FIG. 1) on and off in an alternate but non-overlapping manner. Buffers 27 and 28 can be adjusted for proper alignment of signals S 1 and S 2 .

A delay segment 20 , which includes inverters 21 - 22 and a capacitor C 3 , determines how long DUT C 1 (from FIG. 1) should be charged or discharged per cycle. The resistor-capacitor (RC) time constant formed by inverter 21 and capacitor C 3 (RC ro ) should be much greater than the RC time constant formed by transistor Q 2 and DUT C 1 or transistor Q 1 and DUT C 1 (RC dut ). Inverter 21 and capacitor C 3 can be adjusted to allow many RC dut time constants to lapse before inverter 22 flips.

The performance of delay segment 20 can be improved by the configuration as shown in FIG. 3 . Basically, inverter 22 in FIG. 2 is substituted by inverters 22 a - 22 b and a multiplexor 15 . Inverter 22 a is for charging capacitor C 3 ,inverter 22 b is for discharging capacitor C 3 , and multiplexor 15 is for selecting the appropriate output signal according to the input signal to inverter 21 . Thus, inverters 22 a - 22 b can be considered as high and low switch point inverters, respectively. The closer the switch points are to the supply voltage, the more time can be elapsed for a given RC ro . This keeps inverter 21 and capacitor C 3 reasonable small. Inverter 22 a can be greater than 90% of the supply voltage and inverter 22 b can be less than 10% of the supply voltage.

With reference now to FIG. 4, there is depicted a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a second embodiment of the present invention. As shown, signal source circuit 11 , n-channel transistor Q 1 , p-channel transistor Q 2 , DUT C 1 and a bypass capacitor C 2 are formed within a single semiconductor structure 10 ′. Bypass capacitor C 2 and transistors Q 1 -Q 2 are connected in parallel with a voltage meter (or voltmeter) 14 . Bypass capacitor C 2 provides additional charge for the switching transients that occur when DUT C 1 is being charged or being discharged. The capacitance of bypass capacitor C 2 is preferably 100 times greater than the capacitance of DUT C 1 . It is also important that bypass capacitor C 2 does not have a high charge leakage because any charge leakage will be manifested in current meter 12 .

Also, in FIG. 1, the voltage that DUT C 1 can achieve will not be as high as the supply voltage VCC_BAR because DC current will be flowing through the parasitic resistor inherently occurred along the interconnects between transistor Q 2 and current meter 12 . The configuration in FIG. 4 can avoid the above-mentioned problem by measuring the voltage across capacitor C 2 because the voltages of DUT C 1 and capacitor C 2 should be equalized at the end of each charge/discharge cycle. Voltage meter 14 preferably has an internal resistance of greater than 100 GΩ. Hence, the current flowing through the parasitic resistances within the interconnects between capacitor C 2 and voltage meter 14 should be negligible as long as the voltage of capacitor C 2 is stable. However, the size of capacitor C 2 can be prohibitive large in order to make the voltage of capacitor C 2 completely stable. One solution to such problem is by selectively sampling the voltage on capacitor C 2 as shown in FIG. 5 .

Referring now to FIG. 5, there is depicted is a block diagram of an apparatus for measuring capacitance of a semiconductor device, in accordance with a third embodiment of the present invention. As shown, signal source circuit 11 , n-channel transistor Q 1 , p-channel transistor Q 2 , DUT C 1 , bypass capacitor C 2 , capacitor C 3 and a switch SW are formed within a single semiconductor structure 10 ″. Bypass capacitor C 2 , capacitor C 3 and transistors Q 1 -Q 2 are connected in parallel with voltage meter 14 . Switch SW is connected between bypass capacitor C 2 and capacitor C 3 . The operation of switch SW is controlled by signal source circuit 11 . For example, switch SW is opened when transistor Q 2 is turned off while transistor Q 1 is turned on, and switch SW is closed when transistor Q 2 is turned on while transistor Q 1 is turned off.

The voltage on bypass capacitor C 2 dips when capacitor C 1 is being charged though transistor Q 2 . At some point during a charge/discharge cycle, the voltages on capacitor C 1 and bypass capacitor C 2 equal to each other. At the end of the charge/discharge cycle, switch SW is closed to connect capacitor C 3 to bypass capacitor C 2 . If the voltage on capacitor C 3 is different than the stabilized voltage between capacitor C 1 and bypass capacitor C 2 , charge will be re-distributed and current will flow through current meter 12 . Eventually, the charge re-distribution settles down and the voltage on capacitor C 3 becomes the stabilized voltage on capacitor C 1 and bypass capacitor C 2 (even though the voltage in between fluctuates). The stabilized voltage is then measured by voltage meter 14 .

Capacitor C 3 should be of a low leakage type, though it is not as important as in bypass capacitor C 2 because capacitor C 3 is not always connected to all the components. Preferably, the size of capacitor C 3 should be large enough to prevent a voltage dip due to current leakage through voltage meter 14 , switch SW or itself. On the other hand, if the size of capacitor C 3 is too large, it may take a long time to reach a stabilized voltage.

As has been described, the present invention provides an improved apparatus for measuring capacitance of a semiconductor device. Although a single DUT is utilized to illustrate the present invention, the capacitance measuring circuit of the present invention is capable of measuring multiple DUTs simultaneously. In fact, signal source circuit 11 , bypass capacitor C 2 (which can be the second DUT), switch SW and capacitor C 3 can be arranged in the same configuration when multiple DUTs are being measured. However, it is important to guarantee that the leakage of too many transistors Q 2 /Q 1 does not compromise all the required measurements. Although a single signal source circuit 11 can be used for measuring more than one DUT, additional bypass capacitor C 2 , switch SW, and capacitor C 3 will be needed at some point. The accuracy of capacitance measurement can be further enhanced by reducing the leakage through transistor Q 1 and transistor Q 2 . Leakage can be reduced by using high threshold V t transistors. Such transistors leak less when they are turned off. Another option is to bias the body of transistor Q 1 negatively and the body of transistor Q 2 positively. Such body bias would also reduce the “off” state leakage current.

While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.