DC-to-DC converter

1. Field of the Invention

The present invention relates in general to a power converter. In particular, the present invention relates to a DC-to-DC converter with high efficiency and power density.

2. Description of the Related Art

FIG. 1 shows a resonant reset dual switch forward DC-to-DC converter. In the converter 10 , a switch Q 101 turns on to divide the DC input voltage into square wave voltage according to a predetermined duty ratio. The square wave voltage is then transformed to secondary winding of the transformer T 101 , and is rectified into a DC voltage to output to load by a rectifying device composed of an inductor L 101 and a capacitor C 101 . The converter needs a large input rectifying device and an output rectifying device because the converter has a non-continuous input current and a large output voltage ripple.

Consequently, the size and cost of the converter may increase. In addition, the transformer T 101 is reset by the inductor L 101 and the capacitor C 101 such that the voltage stress of the switch Q 101 is very high, and also has high electromagnetic interference (EMI) because the converter Q 101 usually operates in a hard switching condition.

FIG. 2 shows a DC-to-DC converter 20 with a synchronous rectifying resonant reset forward circuit. The converter 10 shown in FIG. 1 may have a low power efficiency due to consumption of diodes D 101 and D 102 when the converter 10 is applied to low input voltage, for example below 12 volts. As shown in FIG. 2, the diodes D 101 and D 102 of the converter 20 are replaced by synchronous rectifiers Q 102 and Q 103 to increase power efficiency. The synchronous rectifiers Q 102 and Q 103 are driven by the induced voltage across the secondary winding N 102 of the transformer T 101 .

FIG. 3 illustrates the key operating waveform of the converter 20 shown in FIG. 2 . As shown in FIG. 3, the first synchronous rectifier Q 102 is always turned on when the switch Q 101 is turned on (t1 to t2), and the synchronous effect is ideal. The second synchronous rectifier Q 103 , however, is not turned on when the switch Q 101 is turned off (t3 to t4), thus the synchronous effect is less than ideal. This problem may affect whole efficiency of the converter 20 when the converter is applied to low output voltage. Although the converter 20 has a simple structure, the synchronous effect is not ideal, and the input current ripple and the output voltage ripple are high. Thus, the converter 20 also needs a large rectifier.

It is an object of the invention to provide a novel and improved DC-to-DC converter that can overcome the above-mentioned disadvantages of the related art.

In the present invention, the converter has three inductors, two capacitors, a first switch and a second switch, a first rectifier and a second rectifier, and a transformer with a primary winding and a secondary winding.

The first switch and the second switch are turned on alternately according to a controlling signal, and a current may flow through the primary winding of the transformer thereby transferring energy to the second winding. The first rectifier and the second rectifier operate according to the energy transferred from the primary winding to obtain a solid current through the third inductor, and a solid DC output voltage is output to the load.

FIG. 1 shows a resonant reset dual switch forward DC-to-DC converter.

FIG. 2 shows a DC-to-DC converter with a synchronous rectifying resonant reset forward circuit.

FIG. 3 illustrates the key operating waveform of the converter of FIG. 2 .

FIG. 4 shows a DC-to-DC converter of the present invention.

FIG. 5 shows operating wave of the DC-to-DC converter 40 of the present invention.

FIG. 6 shows the analysis mode of the DC-to-DC converter shown in FIG. 4 .

FIG. 7 shows another aspect of converter according to the second embodiment of the present invention.

FIG. 8 shows another aspect of converter according to the third embodiment of the present invention.

FIGS. 9 A˜ 9 H illustrate Operation of the converter shown in FIG. 4 .

FIG. 10 shows another aspect of converter according to the fourth embodiment of the present invention.

FIG. 11 shows another aspect of converter according to the fifth embodiment of the present invention.

FIGS. 12 A˜ 12 D show other aspects of the converter according to the present invention.

FIGS. 13 A˜ 13 C show other aspects of the converter according to the present invention.

[The First Embodiment]

The present invention provides a DC-to-DC converter 40 , also called a tapping transformer boost half bride DC-to-DC converter. As shown in FIG. 4, the DC-to-DC converter 40 of the present invention has three inductors L 1 ˜L 3 , two capacitors C 1 ˜C 2 , a first switch Q 1 and a second switch Q 2 , a first rectifier Q 3 and a second rectifier Q 4 , and a transformer T 1 having a primary winding and a secondary winding, and each primary winding and secondary winding has two ends and a tapper (Tp 1 and Tp 2 ). The first winding has a first primary winding N 1 and a second primary winding N 2 , and the second winding has a first secondary winding N 3 and a second secondary winding N 4 . Each of the switches Q 1 ˜Q 2 and the rectifiers Q 3 ˜Q 4 has a MOS transistor and a parasitical diode, and the first switch Q 1 and second switch Q 2 operate according to a control signal S 1 . A DC input voltage Uin, for example is a battery or an external DC voltage source.

The first terminal of the first switch Q 1 is connected to the second terminal of the second switch Q 2 , a first end of the first capacitor C 1 is connected to the first end of the second switch Q 2 , and the second end of the first capacitor C 1 is connected to a first end of the second capacitor C 2 . A second end of the second capacitor C 2 is connected to the second terminal of the first switch Q 1 , and the first end of the second capacitor C 2 is connected to the second end of the primary winding (N 1 and N 2 ). Two ends of the first inductor L 1 are connected between the DC input voltage Uin and the tapper Tp 1 of the primary winding (N 1 and N 2 ), and two ends of the second inductor L 2 are connected between the second end of the second switch Q 2 and the first end of the primary winding (N 1 and N 2 ).

The first rectifying device Q 3 has a first terminal connected to the first end of the secondary winding (N 3 and N 4 ), and a control terminal connected to the second end of the second winding. The second rectifying device Q 4 has a first terminal connected to the second end of the secondary winding, a control terminal connected to the first end of the secondary winding, and a second terminal connected to the second terminal of the first rectifying device Q 3 . The output capacitor C 5 has a first end connected to the second terminal of the first rectifying device Q 3 , and a second end. The output capacitor C 5 smoothes down the output voltage of the converter. Two ends of the third inductor L 3 are connected to the tapper Tp 2 of the secondary winding (N 3 and N 4 ) and the first end of the output capacitor C 5 .

The operating wave of the DC-to-DC converter 40 of the present invention is shown in FIG. 5, the first switch Q 1 and the second switch Q 2 are turned on alternately, and the converter of the present invention has eight operating modes in one period.

Steady-state Analysis of DC-to-DC converter of the present invention is performed as shown in FIG. 4 and FIG. 5 . As to loop Uin-L 1 -N 2 -C 2 -Uin, because the average voltage across the inductor L 1 and the second primary winding N 2 in steady-state operating must be zero, the voltage V C2 across the second capacitor C 2 may equal the DC input voltage Uin. As to loop Uin-L 1 -N 2 -L 2 -Q 1 -Uin, the duty ratio is assumed to be D Q1 . Because the average voltage across the first inductor L 1 , the second primary winding N 2 and the second inductor L 2 in steady-state operating must be zero, the relation between the voltage U C1 across the first capacitor C 1 and DC input voltage Uin may equal the relation between the output voltage and the input voltage of the converter 40 shown in FIG. 4 when the first switch Q 1 is turned off. That is U C1 = Uin 1 - D Q1 ( 1 )

[1] t1<t< 1 2

As shown in FIG. 9A, the first switch Q 1 is turned on and the second switch Q 2 is turned off, the DC input voltage Uin stores energy into the first inductor L 1 through loop Uin-L 1 -N 1 -L 2 -Q 1 -Uin, and the voltage V C2 stored in the second capacitor C 2 may discharge through loop C 2 -N 2 -N 1 -L 2 -Q 1 -C 2 to transform energy to the secondary winding (N 3 and N 4 ). At this time, the first secondary winding N 3 induces a positive voltage to turn on the first rectifying device Q 3 and to feed energy to the load.

In this time interval, the voltage across the first inductor L 1 is V  ( L 1 ) = Uin × N 2 N 1 + N 2 = Uin × N 2 n 1 ( 2 )

The positive voltage induced across the first secondary winding N 3 of the transformer T 1 is V  ( N 3 ) = Uin × N 3 N 1 + N 2 = Uin × N 3 n 1 ( 3 )

The driven voltage of the first rectifying device Q 3 is Vg     s  ( Q 3 ) = Uin × ( N 3 + N 4 ) N 1 + N 2 = Uin × n 2 n 1 ( 4 )

where n1=N 1 +N 2 , and n2=N 3 +N 4 .

[2] t2<t<t3

As shown in FIG. 9B, in this time interval, both the first switch Q 1 and the second switch Q 2 are turned off, and the second rectifying device Q 3 and the fourth rectifying device Q 4 are turned on, and the secondary winding (N 3 and N 4 ) feeds energy to the load. The drain-to-source voltage Vds(Q 1 ) of the first switch Q 1 is increased slowly due to the third capacitor C 3 and the fourth capacitor C 4 , such that the switching loss of the first switch Q 1 is minimized. Thus, the first switch Q 1 is turned off in soft switching condition.

[3] t3<t<t4

As shown in FIG. 9C, both the first switch Q 1 and the second switch Q 2 are turned off, the voltage V C3 across the third capacitor C 3 increases to be clamped to the voltage V C1 such that the parasitic diode of the second switch Q 2 is turned on. At this time, one portion of the energy stored in the first inductor L 1 charges the first capacitor C 1 through loop L 1 -N 1 -L 2 -Q 2 -C 1 -C 2 -Uin-L 1 , and the other portion transforms to the secondary winding (N 3 and N 4 ) through the loop L 1 -N 2 -C 2 -Uin-L 1 . At the same time, the second secondary winding N 4 induces a positive voltage to feed energy to the load.

In the time interval, the voltage difference between the voltage V C1 and the voltage V C2 of the primary winding of the transformer T 1 is V  ( N 1 + N 2 ) = V C1 - V C2 = Uin ( 1 - D Q1 ) = Uin × D Q1 ( 1 - D Q1 ) ( 5 )

The voltage stored in the first inductor L 1 is V  ( L 1 ) = N 2 N 1 + N 2 × V  ( N 1 + N 2 ) = N 2 n 1 × D Q1 × Uin 1 - D Q1 ( 6 )

The voltage induced across the second secondary winding N 4 of the transformer T 1 is V  ( N 4 ) = N 4 N 1 + N 2 × D Q1 × Uin 1 - D Q1 = N 4 n 1 × D Q1 × Uin 1 - D Q1 ( 7 )

The driven voltage of the second rectifying device Q 4 is Vgs  ( Q 3 ) = ( N 3 + N 4 ) N 1 + N 2 × D Q1 × Uin 1 - D Q1 = n 2 n 1 × D Q1 × Uin 1 - D Q1 ( 8 )

[4] t4<t<t5

As shown in FIG. 9D, the first switch Q 1 is turned off, and the second switch Q 2 is turned on under a zero voltage condition because the parasitic diode of the second switch Q 2 has turned on. The energy stored in the first inductor L 1 charges the first capacitor C 1 through the loop L 1 -N 1 -L 2 -Q 2 -C 1 -C 2 -Uin-L 1 .

[5] t5<t<t6

As shown in FIG. 9E, the first switch Q 1 is turned off, and the second switch Q 2 is turned on. The energy stored in the inductor L 1 does not offer to the secondary winding (N 3 and N 4 ), and the voltage V C1 across the first capacitor C 1 may discharge through the loop C 1 -Q 2 -L 2 -N 1 -N 2 -C 2 -C 1 to feed energy to the secondary winging of the transformer T 1 .

[6] t6<t<t7

As shown in FIG. 9F, both the first switch Q 1 and the second switch are turned off. The drain-to-source voltage Vds(Q 2 ) of the second switch Q 2 is increased slowly due to the third capacitor C 3 and the fourth capacitor C 4 , such that the switching loss of the second switch Q 2 is minimized. Thus, the second switch Q 2 is turned off in a soft switching condition.

[7] t7<t<t8

As shown in FIG. 9G, both the first switch Q 1 and the second switch Q 2 are turned off. The parasitic diode of the second switch Q 2 is turned on because the inductor current may flow continuously and the voltage VC 3 across the third capacitor C 3 may discharge to zero.

[8] t8<t<t9

As shown in FIG. 9H, the first switch Q 1 is turned on under zero voltage condition and the second switch Q 2 is turned off. One operating period of the circuit shown in FIG. 4 is disclosed above. In the circuit, the total turns of the primary winding and of the secondary winding are n1 and n2 respectively. From the mentioned above, the output voltage is V  ( C 5 ) = V  ( N 3 ) × D Q1 + V  ( N 4 ) × ( 1 - D Q1 ) = N 3 n 1 + Uin × D Q1 + N 4 n 1 × D Q1 × Uin 1 - D Q1  ( 1 - D Q1 ) = N3 + N4 n1 × D Q1 × Uin = n2 n1 × D Q1 × Uin  ( 9 )

Therefore, the duty ratio D Q1 of the switch Q 1 can be designed to exceed 50% in the present invention, and the output voltage V(C 5 ) only relates to the total number of turns of the primary winding and the secondary winding of the transformer T 1 , but not to the tapping point of the transformer T 1 .

Voltage-second across the first inductor L 1 is V     S = Uin × N 2 n 1 × D Q1 × 1 fs ( 10 )

Consequently, the voltage stress of the first inductor L 1 may equal voltage-second and relates to the tapping position of the transformer T 1 , namely the turns of the second primary winding N 2 . That is to say, the voltage stress (voltage-second) of the first inductor L 1 can be adjusted by adjusting the tapping position of the transformer T 1 . The voltage stress of the first inductor L 1 is increased as the turns of the second primary winding N 2 increase, and vice versa.

FIG. 6 shows the analysis mode of the converter 40 shown in FIG. 4 . As mentioned above, the induced voltage of the primary winding (N 1 and N 2 ) does not relate to the turns of the first primary winding N 1 or to the second primary winding N 2 . That is to say, the voltage-seconds of the primary winding (N 1 and N 2 ) does not relate to the connection position in which the first inductor L 1 connects to the primary winding of the transformer T 1 . Briefly, it assumes that both the input current Iin and output current Io are DC current, and turns of the first secondary winding N 3 equal to the second secondary winding N 4 (N 3 =N 4 =n2/2), and the transform efficiency of the converter 40 is 100%, therefore input current is I i     n = n 2 n 1 × D Q1 × I 0 ( 11 )

As shown in FIG. 6, inducing inductors Lm 1 and Lm 2 correspond to the first primary winding N 1 and the second primary winging N 2 respectively. Because the capacitors C 3 and C 4 cannot have any DC component, such that the DC current component through the inducing inductor Lm 2 equals that through the primary winging (N 1 and N 2 ), namely I  ( L m2 ) = n 2 2 n 1 × ( 2  D Q1 - 1 ) × I 0 = n 2 2  n 1 × ( 2  D Q1 - 1 ) × I 0 ( 12 )

Consequently, the DC current component through the inducing inductor Lm 1 equals the difference between the DC current component through the inducing inductor Lm 2 and the input current Iin, namely I  ( L m1 ) = I  ( L m2 ) - I0 = n2 2  n1 × ( 2  D Q1 - 1 ) × I0 - n2 n1 × D Q1 × I0 = n2 2  n1 × I     o  ( 13 )

Therefore, the ampere turns of the induced inductors of the transformer T 1 is I  ( m1 ) × N1 + I  ( m2 ) × N2 = n2 2  n1 × I0 × N1 + n2 2  n1 × ( 2  D Q1 - 1 ) × I0 × N2 = n2 2  n1 × I0 × ( N1 + ( 2  D Q1 - 1 ) × N2 ) = n2 2  n1 × I0 × ( n1 - 2  N2 × ( 1 - D Q1 ) )  ( 14 )

As mentioned above, the ampere turns of the inductors (Lm 1 and Lm 2 ) of the transformer can be minimized by adjusting the connection position of the first inductor L 1 and the primary winding (N 1 and N 2 ) of the transform T 1 according to different duty ratio.

Therefore, the present invention has many advantages as follows:

1. Driving the output synchronous rectifying devices is easy and effective.

2. Adjustment of the voltage stress between the inductor and the transformer can be made by modifying the turns of the second primary winding N 2 , such that each magnetic element can operate in the best condition.

3. The duty ratio D Q1 of the switches can be designed exceeding 50%, suitable for wide input voltage operations.

4. Switching loss of the switches is small because all switches of the circuit operate under a soft switching condition.

5. Only a small input inductor is needed because of operation under continuous current mode (CCM).

6. Only a small output inductor is needed because of the small output voltage ripple.

[The Second Embodiment]

As shown in FIG. 7, the first inductor L 1 is connected between the second end of the transformer T 1 and the DC input voltage Uin, and the second inductor L 2 is connected between the tapper Tp 1 of the transformer T 1 and the second terminal of the second switch Q 2 , with other elements the same as shown in FIG. 4 . In this embodiment, the voltage stress between the inductors and the transformer can be adjusted, and does not influence the output characteristic of the converter. The operation of the circuit is omitted because it is the same as shown in FIG. 4 .

[The Third Embodiment]

As shown in FIG. 8, the first inductor L 1 is connected between the second end of the transformer T 1 and the input voltage Uin, the second inductor L 2 is connected between the first end of the transformer T 1 and the second terminal of the second switch Q 2 , one end of the second capacitor C 2 is connected to the tapper Tp 1 of the transformer T 1 , and other elements are the same as shown in FIG. 4 . In this embodiment, the voltage stress between the inductors and the transformer can be adjusted, and does not influence the output characteristic of the converter. Operation of the circuit is omitted because it is the same as shown in FIG. 4 .

[The Fourth Embodiment]

As shown in FIG. 10, the third inductor L 3 is connected between the first terminal of the first rectifying device Q 3 and the output capacitor C 5 , the fourth inductor L 4 is connected between the first terminal of the second rectifying device Q 4 and the output capacitor C 5 , and other elements are the same as shown in FIG. 4 . In this embodiment, the first rectifying device Q 1 , the second rectifying device Q 2 , the first inductor L 3 , the second inductor L 4 and the secondary winding (N 3 and N 4 ) of the transformer compose a synchronous output current double rectification circuit, and the secondary winding (N 3 and N 4 ) does not need a tapper such that the transformer structure is simplified. Operation of the circuit is omitted because it is the same as shown in FIG. 4 .

[The Fifth Embodiment]

As shown in FIG. 11, the third inductor L 3 is connected between the first terminal of the first rectifying device Q 3 and the output capacitor C 5 , and other elements are as the same as shown in FIG. 4 . In those embodiments, the first rectifying device Q 1 , the second rectifying device Q 2 , the first inductor L 3 , and the secondary winding (N 3 and N 4 ) of the transformer compose a synchronous half-wave rectification circuit, and the secondary winding (N 3 and N 4 ) does not need a tapper such that the transformer structure is simplified. Operation of the circuit is omitted because it is the same as shown in FIG. 4 .

[The Sixth Embodiment]

As shown in FIGS. 12 A˜ 12 C, the first rectifying device Q 3 and the second rectifying device Q 4 replace the first diode D 1 and the second diode D 2 , and other elements are as the same as shown in FIG. 4 . In those embodiments, the first diode D 1 , the second diode D 2 , the first inductor L 3 , and the secondary winding (N 3 and N 4 ) of the transformer compose a non-synchronous rectification circuit, and the transformer structure is simplified and the cost of the whole converter is thus minimized. Operation of the converter shown in FIGS. 12 A˜ 12 C is omitted because operation thereof is same as shown in FIG. 4 .

As shown in FIG. 12D, the first rectifying device Q 3 and the second rectifying device Q 4 replace the first diode D 1 and the second diode D 2 , and further have a third diode D 3 and a fourth diode D 4 , with other elements the same as shown in FIG. 4 . In this embodiment, the first diode D 1 , the second diode D 2 , the third diode D 3 , the fourth diode D 4 , the first inductor L 3 , and the secondary winding (N 3 and N 4 ) of the transformer compose a non-synchronous rectification circuit, and the transformer structure is simplified and the cost of the whole converter is minimized. Operation of the converter shown in FIG. 12D is omitted because it is the same as shown in FIG. 4 . In addition, the secondary winding structure of the transformer also can be modified as shown in 13 A˜ 13 C.

Finally, while the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.