Silicon-based high speed optical wiring board

The present invention relates to optical wire boards. More particularly, the present invention relates to a high speed (e.g., 40 Gb/s) optical wiring board incorporating a silicon substrate into both the optical subassembly and the electrical RF transmission circuit.

Due to the rise of the Internet, cellular phones, virtual private networks, and the like, there is a growing need for faster and faster communication systems to handle the tremendous increase in information being transmitted. One of the areas where this demand is the greatest is in the area of optical communications.

Optical transmission systems in the 10 Gb/s range are already becoming commonplace; systems operating at 40 Gb/s (and higher) are now in development. However, the production of high speed transmitters and receivers in the 40 Gb/s range has been greatly hampered due to limitations in the materials used to create the wiring boards on which these components sit.

Traditionally, optical components for these high speed systems have been integrated on a substrate such as aluminum oxide (Al 2 O 3 ), wherein active alignment must be used to align the optical elements on the wire board. As an alternative, a combination of a silicon optical bench (SiOB) for the optical devices, and an Al 2 O 3 -based high speed electrical circuit board has been used, incorporating ribbon bonding, flip-chip soldering and/or flex cables to interconnect the two components.

However, these systems of the prior art have significant disadvantages. The active optical alignment required by conventional Al 2 O 3 wire boards is expensive and cost prohibitive. The active alignment of optical fibers to laser diodes or photodetectors is a time consuming process, which makes automated production extremely difficult. Moreover, the facilities needed to manufacture these systems require a considerable investment with a reasonably large volume production.

As a result, a silicon optical bench (SiOB) is preferable as a substrate for the optical elements. The use of silicon as a substrate allows for the passive alignment of the laser/photodiode (i.e., “active optical device”) to the optical fiber, such as through the use of arrays of etched V-grooves in the silicon, reducing production costs. For example, a wafer-scale package process may be used for volume production of hybrid integrated optical components, by using the passive alignment of the precisely cleaved laser diode and semiconductor waveguide onto a micro-machined silicon optical bench.

Alternatively, a batch transporting technique can be employed, in which a micro-machined silicon guiding plate may be used as a processing unit through the entire manufacturing procedure from die bonding to hermetic sealing. Such a system is disclosed in Jan-Jun Koh, et al., On - Wafer Process for Mass Production of Hybridly Integrated Optical Components Using Passive Alignment on Silicon Motherboard , the 51 st Electronic Components and Technology Conference, Lake Buena Vista, Fla., May 29-Jun. 1, 2001, page 6.

Unfortunately, however, conventional silicon-based wire boards have not been considered as a good choice for the electrical circuit components in high speed optical wire boards, primarily due to excessive RF insertion loss in the silicon.

Accordingly, a system is needed which provides a stable and accurate passive alignment of the optical components on the optical sub-assembly of a high speed optical wire board, while simultaneously achieving satisfactory RF-performance of the electrical circuit mounted on the same substrate.

The present invention is directed to an optical wire board incorporating a silicon substrate, such as a silicon optical bench (SiOB), as a base for both the optical subassembly and the RF transmitting electrical circuit. An optical element (such as a lens) is preferably passively aligned to the active optical device (which can be, for example, a laser diode or a photodetector) using a V-groove etched into the silicon. An integrated circuit (IC) for coupling the active device to external contacts is preferably flip-chip mounted to the SiOB upon pads disposed around a cavity etched beneath the integrated circuit. The inclusion of a cavity below the integrated circuit serves to minimize the dielectric loading effect of the silicon substrate on the IC (due to the close proximity between the silicon substrate and the IC), thus minimizing the potential for RF performance degradation (detuning) of the network.

Biasing circuitry may also be provided on the silicon substrate and connected to the electrical transmission circuit for operating the active optical device in conjunction with the integrated circuit; the external contacts may be provided on the wire board for connecting the electrical transmission circuit to additional (external) electrical components.

Other and further aspects of the present invention will become apparent during the course of the following discussion and by reference to the accompanying drawings.

Referring now to the drawings, where like numerals represent like parts in several views:

FIG. 1 is an isometric drawing of a preferred embodiment of an optical wire board of the present invention;

FIG. 2 is a graph of insertion loss per unit length as a function of frequency for both a prior art 50Ω transmission line and an equivalent 50Ω transmission line formed on the optical wire board of the present invention;

FIG. 3 is a top view of a preferred embodiment of an optical wire board of the present invention; and

FIG. 4 is a cross-sectional view of the optical wire board of FIG. 4 , taken along line 3 — 3 .

The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of preferred embodiments of the invention, which, however, should not be taken to limit the invention to a specific embodiment, but are for explanation and understanding only.

FIG. 1 is an illustration of a preferred embodiment of the optical wire board of the present invention. As shown, substrate board 1 contains integrated circuit 2 , optical cavity 3 , active optical device 4 , electronic biasing components 5 , RF transmission line 6 , and an optical element 7 (in this example, a ball lens). RF transmission line 6 is provided for propagating RF signals between integrated circuit 2 and external circuitry (not shown), such as a signal amplifier or the like, which are well-known in the art.

Active optical device 4 may comprise any one of a number of well-known high speed sources or detectors, such as a laser or LED (as sources), or a PIN or uni-traveling-carrier (UTC) photodiode (as a detector). The operation of these various active optical devices is well-known to those of ordinary skill in the art and will not be elaborated upon here. Active optical device 4 is aligned using visual systems and fiducial alignment markings on both active device 4 and optical wire board 1 . Optical cavity 3 is used to couple light between active optical device 4 and an optical fiber (shown in phantom) mounted in optical cavity 3 . Optical element 7 is typically a ball lens, but is not limited thereto. Optical element 7 is preferably attached to cavity 3 using AlO bonding, but alternative methods of attachment can also be used.

Optical cavity 3 preferably contains a V-shaped groove for accurate passive alignment of ball lens 7 (and the associated optical fiber) with active optical device 4 . Those of ordinary skill in the art will appreciate that systems for passive alignment of the optical fiber to active device 4 are not particularly limited, and may comprise any passive alignment mechanism capable of being mounted on substrate board 1 .

Substrate board 1 is preferably comprised of a silicon optical bench (SiOB) structure. The use of a silicon substrate in the manner of the present invention for the mounting of both the optical components and the electrical circuit provides significant advantages over the prior art, including improved RF performance and reduced transmission line insertion loss. In particular, proper processing of the silicon during the manufacture of the SiOB can reduce insertion loss to approximately 0.3 dB/mm at 40 GHz. This can be achieved, for example, by using advanced CMOS oxidation techniques and post-processing hydrogen annealing to minimize interface states. A conventional high resistivity (˜5 kΩ-cm) silicon substrate is highly lossy at microwave frequencies, where the loss can be attributed to fixed charges that exist along the interface between the silicon substrate and the overlying oxide insulation layer. These interface states induce an inversion layer in the silicon that causes increased attenuation in the transmitted signal. Using advanced CMOS oxidation techniques, such as a multiple number of clean/rinse cycles, followed by oxidation in a combined O 2 /N 2 ambient, have been found to improve the quality of the oxide layer and reduce the number of interface states between the silicon substrate and the oxide. FIG. 2 contains a graph illustrating the reduction in insertion loss that can be attributed to using an oxide layer formed using advanced CMOS techniques. Curve A in FIG. 2 illustrates the insertion loss per unit length versus frequency of a co-planar waveguide (CPW) transmission line formed on a silicon substrate. This CPW structure included a conventionally grown oxide layer of a thickness of approximately 5000 Å. As shown, at an operating frequency of 10 GHz, the insertion loss per unit length has increased to approximately 1.1 dB/mm. The loss further increases to approximately 1.5 dB/mm at 40 GHz. In comparison, curve B in FIG. 2 is associated with a similar CPW transmission line structure, this time including an oxide grown using the advanced CMOS processing techniques mentioned above. It is evident that the insertion loss per unit length in such a structure is significantly reduced, falling to a value of only approximately 0.1 dB/mm at 10 GHz, and to roughly 0.3 dB/mm at 40 GHz.

Because of the precision with which silicon can be etched, the use of a silicon board (in contrast to Al 2 O 3 ) in the manner of the present invention provides the significant advantage that optical element 7 can be passively aligned with active optical device 4 , such as through the use of the aforementioned V-groove, providing a significant savings in production costs. Moreover, the optical components may be mounted on the same substrate as the electrical components, providing further significant savings in product cost.

In addition, since silicon is thermally well-matched with indium phosphide (InP) laser diodes, photodetectors and/or integrated circuits (as well as gallium arsenide (GaAs) integrated circuits), significantly improved thermal conductivity while minimizing thermal stresses can be achieved, with precise features, by using conventional photolithographic processes. The use of silicon in the manner of the present invention also allows for precise micro-machining for optical element placement, as well as multiple metalization systems that are compatible with soldering, RF transmission, AlO bonding, wire bonding, and epoxy bonding with integrated passive electrical components.

Referring back to FIG. 1 , electrical biasing components 5 are included for properly biasing active optical device 4 and integrated circuit 2 . For example, biasing components 5 may include integrated RF bypass capacitors and resistors for noise filtering of active optical device 4 and integrated circuit 2 . In the preferred embodiment of the present invention, the metalization preferably comprises titanium (Ti), titanium nitride (TiN), platinum (Pt), gold (Au) and/or chromium (Cr). Titanium and aluminum (Al) are preferably used for AlO bonding, and SiO 2 is preferably used for RF transmission, formed using the advanced CMOS processing techniques discussed above.

In accordance with the present invention, tantalum nitride may be used to form the integrated resistors and resistor passivation in biasing components 5 . The integrated capacitor elements within components 5 may include a-SiOH:H and/or a-SiN:H as the dielectric material. It will be apparent to those skilled in the art that additional materials such as Ta 2 O, BuTiO 3 , and others, could also be used as the capacitor dielectric. Furthermore, other resistive materials—such as nichrome—could be used as the resistor.

FIG. 3 contains a top view of a preferred embodiment of the optical wire board of the present invention, and the mounting of the integrated circuit thereon. FIG. 4 is a cross-sectional view of the optical wire board as taken along line 4 — 4 of FIG. 3 . As shown in FIGS. 3 and 4 , integrated circuit 2 is preferably flip-chip mounted over integrated circuit cavity 8 atop bond pads 9 . “Flip-chip” mounting is a technique well-known in the art for bonding the top, active surface of an integrated circuit to a substrate, the bonding comprising the plurality of electrical interconnections required between the integrated circuit and other components on the board. Flip-chip mounting of the integrated circuit onto the silicon substrate minimizes the parasitic inductance associated with this interconnection, which leads to improved RF performance. The use of bond pads 9 and a silicon substrate in the manner of the present invention provides the significant advantage of allowing for more precise placement of integrated circuit 2 over a more accurately etched cavity 8 . The use of SiO 2 in the manner of the present invention provides the distinct advantage over Al 2 O 3 wire boards in that reactive ion etching (RIE) can be used to achieve this extremely precise etching of integrated circuit cavity 8 .

In the preferred embodiment of the invention, the optical wire board has specific dimensions for each of the aforementioned components. These dimensions provide the substantially optimal RF characteristics for the device. For example, the stray electromagnetic fields induced by the presence of an RF signal on the underside of integrated circuit 2 will extend downward toward silicon substrate 1 . The depth of field penetration into the silicon substrate will depend largely upon the dimensions of the transmission line structure on the integrated circuit, as well as the type of transmission line structure (e.g., co-planar waveguide or microstrip). The close proximity of silicon substrate 1 to integrated circuit 2 will increase the effective dielectric constant of the resultant structure, thus potentially degrading (i.e., detuning) the RF performance if the field penetration into the silicon substrate is substantial. The depth of cavity 8 , therefore, can be properly determined by knowing the dimensions and type of transmission line structure used on integrated circuit 2 , where in the best case, most of the stray electromagnetic fields will be confined to the “air gap” created by the cavity, and will not reach into the underlying silicon substrate. For integrated circuit 2 utilizing co-planar waveguide transmission lines, the thickness of the IC is typically greater than 200 μm thick, while the thickness of an IC using microstrip transmission lines is typically less than 100 μm thick. Bond pads 9 are preferably 100 μm square and allow integrated circuit 2 to be flip-chip mounted directly over integrated circuit cavity 8 .

The minimum thickness for silicon substrate 1 is determined by the depth of optical cavity 3 and the size of optical element 7 . It is also a function of the dimensions and structure of RF transmission line 6 . The preferred embodiment for RF transmission line 6 , as shown in FIG. 1 , is a co-planar waveguide structure. In this structure, the penetration depth of electromagnetic fields into silicon substrate 1 is approximated by taking the sum of one-half the width of the center electrode plus the gap to the adjacent ground plane lines. For optimal performance of RF transmission line 6 , the thickness of silicon substrate 1 is preferably greater than this value.

Integrated circuit cavity 8 is preferably approximately 100 μm deep (depending on the dimensions and type of transmission line on the integrated circuit, as well as the substrate dielectric) and is preferably substantially co-extensive with the exposed area of integrated circuit 2 , so that integrated circuit cavity 8 is etched essentially everywhere except under bond pads 9 . It is preferred that bond pads be within 10 μm, and more preferably within 1 μm, of the sidewalls of integrated circuit cavity 8 . While the sidewalls of cavity 8 are shown as slanted in FIG. 3 , it is preferred that the sidewalls be substantially perpendicular to the top and bottom surfaces of board 1 .

Although this invention has been described with reference to particular embodiments, it will be appreciated that many variations may be resorted to without departing from the spirit and scope of this invention, as defined in the following claims.