Digital filter realization

This invention relates to the realization of a digital filter, in particular to the realization of a digital FIR filter of order N which comprises a modified digital filter of order 1 operating with a higher sampling rate. Further, the invention relates to a method to filter a M-times multiplexed input signal with such a digital FIR filter.

A digital filter of order 2N which receives a M-times multiplexed input signal which comprises a modified filter of order 1 in which 2N filter coefficients get periodically switched with a clock frequency that equals to M·2N-times the sampling rate of the input signal to set the filter periodically into M·2N internal filter states in each of which an internal output value is calculated before outputting one complete sample of the M-times multiplexed output signal is described in the European Patent Application EP 98 114 111.2 of the Applicant which content is herewith incorporated into this specification.

A special cost effective realization of such a filter is described in the Applicant's European Patent Application “Memory and Gate Effect Realization of a Digital Filter” which content is herewith incorporated into this specification.

These both documents show digital filters, preferably IIR filters, which have a clock frequency that equals to the sampling rate·number of multiplexes·filter order. Therefore, depending on the input signal and the wanted filter order it might be necessary to operate the respective filter with a comparatively high clock rate which results in a high needed processing power on the chip on which the filter is realized.

Therefore, it is the object underlying the present invention to provide an enhanced digital filter and method to filter a M-times multiplex input signal with a digital filter which require a reduced calculation power.

The digital FIR filter of order N receiving a M-times multiplexed input signal with a predetermined sampling rate and outputting a M-times multiplexed output signal with said predetermined sampling rate according to the present invention comprises: a combining unit which receives the input signal, holds the last N input signal samples of each input signal multiplex, at least combines at least two of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter which have to be subjected to equal filter coefficients, and outputs a combined output signal comprising all not combined input signal samples of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter and all combined input signal samples thereof during the time in which the actual input sample is supplied to the digital filter; one multiplier receiving the combined output signal and multiplying each sample thereof with a respective corresponding filter coefficient; and one integrator receiving the multiplied samples of the combined output signal, integrating them during a first time period in which the actual input sample is supplied to the FIR filter, and providing the actual output sample at the end of said first time period.

Therewith, according to the present invention a FIR filter is realized which needs only a reduced calculation power taking advantage of the symmetrie of the impulse response of FIR filters.

Preferably, in the digital filter according to the present invention, for even N said combining unit combines the first N/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in the order of reception with the last N/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in time inverted order of reception.

Alternatively or additionally, in the digital filter according to the present invention, for odd N said combining unit combines the first (N−1)/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in the order of reception with the last (N−1)/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in time inverted order of reception, and doubles the (N+1)/2 sampling value.

Of course, the order of combination of the input samples can also be time inverted together with the provision of the coefficients in the respective corresponding order.

Therefore, in the digital filter according to the above described embodiments of the present invention, said combining unit preferably comprises a first buffer which receives the input signal and outputs each of the second half of the last N received input samples of each input signal multiplex in the time inverted order of reception during the time in which the actual input sample is supplied to the FIR filter, a second buffer which receives the input signal and outputs each of the first half of the last N received input samples of each input signal multiplex in the order of reception during the time in which the actual input sample is supplied to the FIR filter, and a first adder ( 3 ) receiving and adding the simultaneously output samples of the first and second buffer to output a respective sample of the combined output signal. In this notation the first half of the last N received input samples means the first N/2 samples for even N and the first (N+1)/2 samples for odd N. Further, the second or last half of the last N received input samples means the last N/2 samples for even N and the last (N+1)2 samples for odd N; the second half includes the newest (actually supplied) sample. Therefore, in case of odd N the middle sample, i.e. the sample (N+1)/2 is doubled.

In this embodiment,

said first buffer preferably comprises: a first switch receiving the input signal at a first fixed terminal and providing the output samples of the first buffer at a variable terminal thereof, a first delay element connected to said variable terminal of said first switch and providing delayed input samples to the second buffer, and a second delay element connected to the output of the first delay element and providing further delayed input samples to a second fixed terminal of said first switch, and

said second buffer preferably comprises: a second switch receiving the delayed input samples at a first fixed terminal and providing the output samples of the first buffer at a variable terminal thereof, a third delay element connected to a variable terminal of said second switch and providing the output samples of the second buffer which are additionally supplied to a second fixed terminal of said second switch,

wherein said variable terminal of said first switch and said variable terminal of said second switch are connected to the respective first fixed terminal during a second time period for loading a new input signal sample and are connected to the respective second fixed terminal during a third time period to calculate and output said combined output signal.

Further, in the digital filter according to the above described embodiments of the present invention, said integrator preferably comprises: a second adder receiving the multiplied samples of the combined output signal as respective first summands and providing the actual output sample at the end of said first time period, a fourth delay element receiving to the output signal of said second adder, and a third switch which variable terminal provides respective second summands to the second adder, which receives a zero signal at a first fixed terminal and the delayed output signal of said second adder at a second fixed terminal, wherein said variable terminal of said third switch is connected to the first fixed terminal during a second time period for loading a new input signal sample and is connected to the respective second fixed terminal during a third time period to calculate and output said actual output sample.

The method to filter a M-times multiplexed input signal with a digital filter of order N which comprises a modified FIR filter of order 1 operating with a higher sampling rate according to the present invention comprises the steps of: holding the last N input signal samples of each input signal multiplex, at least combining at least two of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter which have to be subjected to equal filter coefficients, multiplying each not combined and each combined input signal sample with a respective corresponding filter coefficient, and integrating the multiplied samples during a first time period in which the actual input sample is supplied to the FIR filter, and providing the actual output sample at the end of said first time period.

In the method according to the present invention, preferably for even N the first N/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in the order of reception are combined with the last N/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in time inverted order of reception.

Alternatively or additionally, in the method according to the present invention, preferably for odd N the first (N−1)/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in the order of reception are combined with the last (N−1)/2 of the last N received input signal samples of the input signal multiplex which comprises the input sample actually supplied to the FIR filter in time inverted order of reception, and the (N+1)/2 sampling value is doubled.

Further alternatively or additionally in the method according to the present invention, preferably said combining comprises an adding of corresponding input signal samples.

A computer program product according to the present invention comprises computer program means adapted to embody the digital filter as defined in anyone of the above embodiments of the present invention when said computer program product is executed on a computer, digital signal processor or the like.

Further, a computer program product according to the present invention comprises computer program means adapted to carry out the method steps as defined in anyone of the above embodiments of the present invention when said computer program product is executed on a computer, digital signal processor or the like.

Therefore, according to the present invention, a digital filter realization is proposed that consists of only one multiplier, i. e. which operates with a higher clock rate and changes coefficient at the multiplier each clock cycle, but in which the clock rate of the multiplier is reduced in comparison to prior art filters by considering equal filter coefficients, e. g. based on the symmetry of FIR filter coefficients. According to the present invention preferably the samples belonging to equal filter coefficients are added in advance in order to reduce the number of multiplications, which concludes in a reduced clock rate for the filter, a reduced needed calculation power, and therefore a reduced power consumption.

In such a particular preferred embodiment of a digital filter according to the present invention which might realize a digital FIR filter, the symmetry of FIR filter coefficients can easily be considered. As defined in general terms above, two ring buffers are supplied to provide the right samples at the right time. Both store “about half” of the needed samples for the filter coefficients. To take advantage of the symmetry and provide the right samples rotating in the buffer, one of the ring buffers provides the samples in “time inverted” order.

The storage of “about half” of the needed samples for the filter coefficients is to be understood in the sense that in case of an even filter order N, i. e. an even number N of filter coefficients, each of the buffers provides N/2 samples, one in the order of reception, i. e. the first sample, the second sample, the third sample, . . . , the N/2 th sample, and the other in time inverted order, i. e. the N th sample, the (N/−1) th sample, . . . , the (N/2+1) th sample. However, in case of an odd filter order N, i. e. of an odd number N of filter coefficients, each of the buffers stores (N+1)/2 samples of the input signal so that the (N+1)/2 th sample is stored in both buffers, i. e. the buffer storing the samples in the order of reception provides the first sample, the second sample, the third sample, . . . , the (N+1)/2 th sample, and the buffer storing the samples in time inverted order stores and outputs the N th sample, the (N−1) th sample , . . . , the (N+1)/2 th .

Due to this technique, a particular easy realization for both cases, i. e. even and odd filter order N is achieved under consideration that the (N+1)/2 th filter coefficient has to be divided by 2 in case of an odd filter order N.

Further features and advantages of the digital filter and the method to filter a M-times multiplexed input signal with a digital filter according to the present invention will become apparent from the following description of exemplary embodiments thereof taken in conjunction with the accompanying figures, in which:

FIG. 1 shows a block diagram of a digital FIR filter realization according to the present invention for a filter of odd filter order,

FIG. 2 shows a block diagram of a digital FIR filter realization according to the present invention for a filter of even filter order, and

FIG. 3 shows a block diagram of a digital FIR filter structure according to the present invention for a filter of odd filter order and a M-times multiplexed input signal.

In the following exemplary preferred embodiments of digital filters according to the present invention are described. Since digital filters used e. g. in digital receivers are often realized on an ASIC, it is wishful to make the filter circuits as small as possible to reduce the costs. This means, that the filters should be realized with as few elements as possible.

Therefore, the exemplary preferred embodiments of digital FIR filter realizations comprise only one multiplier to realize a FIR filter of order N. Similar to the realizations of the above-identified European Patent Applications which content is included into this specification by reference, the realization of a FIR filter of order N with one multiplier is based on the usage of a higher clock rate for the actual filter and a provision of the filter coefficients in a special order at the multiplier. Further, according to the present invention calculation power requirements in respect to a needed clock rate are reduced due to the combining of samples subjected to equal filter coefficients.

According to the described preferred embodiments of the present invention which only consider the symmetry of FIR filter coefficients, the clock rate for a filter of odd order N is (N+1)/2·f s ·M, with f s being the sampling rate of the input signal and M being the number of multiplexes of the input signal. In case of an even filter order N the clock rate is N/2·f s ·M.

Since the symmetry of a FIR filter is used to reduce the number of multiplications, two ring buffers are used to provide the right samples at the right time. One of the ring buffers provides the samples in receiving order and the other provides the samples in time inverted order. Then, the samples which have to be applied to symmetric coefficients are added in advance to reduce the number of multiplications corresponding samples. To avoid an overflow, preferably the input samples are resealed.

After the added samples are subjected to their filter coefficients, i. e. multiplied by the respective filter coefficient, an integrator which gets initialized for each new output sample builds the sum of the (N+1)/2 in case of an odd filter order N and N/2 in case of an even filter order N combined and weighted input samples.

FIG. 1 shows a block diagram of the FIR filter structure according to the present invention for a filter of odd filter order N.

The input signal which is not multiplexed is supplied to a combining unit comprising a first ring buffer 1 , a second ring buffer 2 , and an adder 3 which holds at least the last N received input samples, combines them so that input samples which have to be subjected to equal filter coefficients based on the FIR filter coefficient symmetry are added, and provides the last N combined input samples, i. e. (N+1)/2 input samples, during the time at which the actual input sample is supplied to the whole FIR filter to the multiplier 4 which correspondingly switches (N+1)/2 filter coefficients to perform a respective weighting of the combined input samples. All (N+1)/2 combined and weighted input samples are fed to an integrator 5 at which output the correspondingly filtered input signal is available after all (N+1)/2 combined and weighted input samples are added.

The first ring buffer 1 comprises a first switch S 1 which receives the input signal at its first fixed terminal S 10 and supplies the output signal of the first ring buffer 1 to the adder 3 at its variable terminal. This output signal is also input to a first delay element D 1 with a delay of 2 clock cycles which supplies its output signal to the input of the second ring buffer 2 and to a second delay element D 2 of the first ring buffer 1 with a delay (N−1)/2. The second delay element D 2 supplies its output signal to the second fixed terminal S 11 of the first switch S 1.

The second ring buffer 2 comprises a second switch S 2 which receives the input signal of the second ring buffer 2 at its first fixed terminal S 20 and supplies the input signal of a third delay element D 3 at its variable terminal. The third delay element D 3 has a delay (N−1)/2 and supplies the output signal of the second ring buffer 2 to the first adder 3 . The output signal of the third delay element D 3 is further input to the second fixed terminal S 21 of the second switch S 2 .

The first adder 3 adds the output signal of the first ring buffer 1 and the output signal of the second ring buffer 2 and supplies a combined output signal to the multiplier 4 . The output signal of the first ring buffer 1 comprises the second half of the last N input samples in time inverted order, i. e. S 1 , S 2 , . . . , S (N+1)/ 2. The output signal of the second ring buffer 2 supplies the first half of the last N input samples in their incoming order, i. e. S N , S N−1 , . . . , S (N+1)/2 . In this notation S 1 is the newest sample, i.e the sample actually supplied to the combining unit, i.e. the first ring buffer 1 , and the sample S N is the oldest sample considered for the current filtering process.

The multiplier 4 weights each of the samples of the combined output signal with a corresponding filter coefficient a 1 , a 2 , . . . , a (N−1)/2 , and—since the middle sample of the odd N input samples, i. e. the sample S (N+1)/2 is doubled—this middle sample is weighted with a filter coefficient a (N+1)/2 which is divided by 2. All weighted samples of the combined output signal which correspond the actual FIR filter supplied input sample are integrated by the integrator 5 . The integrator 5 comprises a second adder A 1 which receives the output signal from the multiplier 4 as a first summand and supplies the actual output sample of the FIR filter at the end of its integrating period at its output. The output of the second adder A 1 is supplied to a fourth delay element D 4 with a delay of one clock cycle which supplies its output signal to the second fixed terminal of a switch S 3 . The variable terminal of the switch S 3 supplies the second summand to the second adder A 1 . The first fixed terminal of the third switch S 3 is connected to a zero signal 6 .

All three switches S 1 , S 2 , S 3 are switched to their first fixed terminal S 10 , S 20 , S 30 in the first clock cycle. Here, the first switch S 1 loads the new input sample, the second switch S 2 takes over one input sample from the first ring buffer 1 to the second ring buffer 2 , and the third switch S 3 initializes the integrator 5 . From the second cycle they are switched to their respective second fixed terminal S 11 , S 21 , S 31 until one output sample of the FIR filter is determined and the next input sample is needed.

FIG. 2 shows the block diagram of the FIR filter structure according to the present invention for a filter of even filter order N for an input signal which is not multiplexed, i. e. comprises only one multiplex. Basically, the filter structure is equal to that of the FIR filter shown in FIG. 1 . Only the delays of the first, second and third delay elements D 1 , D 2 . D 3 are different. For an even filter order N the first delay element D 1 only provides a delay of one clock cycle, the second delay element D 2 provides a delay of N/2 clock cycles, and the third delay element D 3 provides a delay of N/2−1 clock cycles. Therefore, the first ring buffer outputs the samples S 1 , S 2 , . . . , S N/2 , and the second ring buffer 2 outputs the samples S N , S N−1 , . . . , S N/2+1 .

Further, since no middle sample exists as in the case for an odd filter order N, the multiplier 4 switches through the filter coefficients a 1 , a 2 , . . . , a N/2 without having to divide one of the filter coefficients.

FIG. 3 shows the basically similar filter structure for a FIR filter for odd filter order N with an M-times multiplexed input signal in only the second and third delay elements have to be changed in comparison to the filter shown in FIG. 1 in that the second delay element of the first ring buffer 1 and the third delay element of the second ring buffer 2 both have a delay of ((N−1)+(N+1)(M−1))/2 clock cycles.

Therefore, the first ring buffer 1 and the second ring buffer 2 respectively output half of the last N samples of the multiplex of the input sample currently supplied to the FIR filter.

The FIR filter according to the present invention is reduced in size, e. g. a realization with as few elements as possible, since only one multiplier is necessary because of running the filter at a higher clock rate. Further, the higher clock rate is reduced in comparison to prior art filters which are reduced in size. Therefore, the realization on an ASIC is cheaper, since only a reduced calculation power is needed for a small size filter unit.