Method and circuit for minimizing glitches in phase-locked loops

This application is a continuation of U.S. patent application Ser. No. 09/553,612 filed Apr. 20, 2000, now U.S. Pat. No. 6,593,817.

This invention relates to a method and a circuit for minimizing glitches in phase-locked loops.

A PLL (Phase Lock Loop) as generally shown at 1 in FIG. 1 comprises essentially a phase comparator 2 , a filter 3 , a frequency divider 4 , and a voltage controlled oscillator VCO 5 . With the phase lock loop PLL 1 locked to a periodic input signal at a frequency Fref, a frequency Fvco of the voltage controlled oscillator VCO 5 is equal to that of the input signal multiplied by a division ratio N of the frequency divider 4 .

The phase comparator 2 then generates a signal which is proportional to the phase difference between the input signal and the output signal of the frequency divider 4 . This signal modifies, through the filter 3 , the control voltage of the voltage controlled oscillator VCO 5 , and consequently its frequency Fvco as well, thereby bringing the output frequency Fdiv of the frequency divider 4 to the same value as the input frequency Fref.

The characteristic parameters according to which a phase lock loop PLL 1 is evaluated are:

accuracy of the generated frequency;

phase noise;

glitch rejection;

locking time; and

loop phase margin.

The frequency accuracy of the voltage controlled oscillator VCO 5 is dependent on the frequency accuracy of the input signal and the accuracy of the phase comparator 2 .

Specifically, it is:

Δ Fvco=N*ΔFref +ΔΦ/2 *π*Fvco   (1)

where,

ΔFvco is the frequency error of the voltage controlled oscillator VCO 5 ;

N is the division ratio of the frequency divider 4 ;

ΔFref is the frequency error of the input signal;

ΔΦ is the phase error of the phase comparator 2 ; and

Fvco is the output frequency of the voltage controlled oscillator VCO 5 .

System specifications covering certain communication standards provide for the largest frequency error of the voltage controlled oscillator VCO 5 to be in the 10 −8 *Fvco range. For example, the GSM Standard sets the maximum error to 2*10 −8 *Fvco.

In this case, assuming one half of that frequency error to be due to inaccuracy of the input frequency (usually obtained from a crystal oscillator), the maximum acceptable phase error would be 6*10 −8 radians.

Such a restricted value for the phase error rules out the use a Gilbert cell for a phase comparator, since this cell exhibits a minimum phase error which lies well above said limit. Furthermore, a Gilbert cell type of phase comparator would exhibit a non-constant system loop gain in the phase locked range of operation.

Thus, for standard practical applications, the phase comparator is provided in a charge pump form, using first Icharge and second Idischarge current generators, having the same Icp value and opposite signs, which generators will vary the output control voltage in opposite directions according to whether the output signal of the frequency divider 4 is leading or lagging behind the input signal. A block diagram for a phase lock loop PLL 1 ′ including a charge pump 6 , according to the prior art, is shown in FIG. 2 .

To avoid phase errors and variations in the loop gain of the phase lock loop PLL 1 ′ near the locking range, a time interval Tmin is usually provided when both current generators, Icharge and Idischarge, deliver equal and opposite currents, such that the input voltage to the filter 3 will remain unchanged, as shown in FIG. 3 . Thus, the current generators Icharge, Idischarge are turned on at each cycle to ensure that the frequency of the voltage controlled oscillator VCO 5 remains locked to the value N*Fref.

The use of a filter 3 ′ with two-poles and a zero, as schematically illustrated in FIG. 4, is conceivable. This filter 3 ′ comprises a resistive element R 1 connected in series to a first capacitive element C 1 , between a terminal T 1 and a voltage reference such as a ground GND. The filter 3 ′ also comprises a second capacitive element C 2 , connected between said terminal T 1 and ground, in parallel with said resistive element R 1 and said first capacitive element C 1 .

The settling time is dependent on the overall loop gain, its phase margin, the filter size, and the maximum admissible frequency error.

Using the filter 3 ′, it is readily seen that the proportionality of the settling time Ts is: T     s ∝ N * R1 * C1 I     cp * K     o * ln  ( B Δ     F     max ) ( 2 )

where,

N is the division ratio;

R 1 , C 1 are elements of the filter 3 ′;

Icp is the charge pump 6 current;

Ko is the oscillator VCO 5 gain;

B is the channel jump of the oscillator VCO 5 ;

ΔFmax is the maximum frequency error of the oscillator VCO 5 .

Formula (2) shows that to obtain short settling times, as is normally required, in wide band, small frequency error systems, it is necessary to use very high values for the charge pump 6 current and filters having decidedly small time constants.

Reasonable values for conventional systems of the GSM and DCS types are:

Icp=4 mA, and

t=25 μs.

Thus, by suitable dimensioning of the filter and the charge pump, a phase lock loop PLL could be provided with a settling time value according to specification. However, such dimensioning would be at variance with the specified rejection of glitches at frequencies that are multiples of the reference frequency Fref of the phase lock loop PLL 1 .

In fact, a real phase look loop PLL 1 would exhibit, as a result of process tolerances, a non-pure frequency spectrum, like that shown in FIG. 5 .

In particular, the two most evident glitches locate a distance equal to the reference frequency Fref away from the lock frequency Fvco of the voltage controlled oscillator VCO 5 . Other glitches, located farther from the oscillation frequency Fvco, are filtered and reduced to a large extent.

It should be noted that glitches are mainly due to two different phenomena, namely the leakage current of the VCO control terminal and a dissymmetry between the two generators of the charge pump.

In particular, the leakage current of the VCO control node is the sum of the leakage currents of the charge pump and the VCO. The contribution from the latter is generally dominant because, at the frequencies of interest, the VCO would essentially consist of an LC resonator, wherein the frequency variation is obtained by varying the voltage across a junction capacitance which has a fairly large leakage current.

The overall leakage current causes the control voltage of the VCO to change proportionally to that current, even with the VCO in the locked state, during the “off” period of the current generators of the charge pump. Consequently, at each cycle, the charge pump is to balance the amount of charge lost during the “off” period.

Thus, the control voltage waveform shows a periodic trend with a period 1/Fref, and this periodic signal generates glitches at frequencies that are multiples of the reference frequency Fref. It can be seen, therefore, that the amplitude of such glitches is directly proportional to the leakage current and inversely proportional to the value of the second capacitive element C 2 of the filter 3 ′.

As a result, in transmission systems designed to strict specifications as to settling time and glitches, this contribution to the overall glitch requires that VCOs with very low associated leakage values be used. There are VCOs commercially available which meet both specifications for conventional transmission systems.

The generation of glitches is also due to asymmetry of the two generators of the charge pump. Particularly in the locked condition, in order to prevent the frequency of the VCO from varying, the average voltage value at the control node must be kept constant. The amounts of charge supplied by the two current generators must, therefore, be equal and opposite.

Assuming that in the locked condition one of the generators is delivering a current Icp for a time interval Tmin, and that the current error is ΔIcp between the two generators, advantageously, the second generator would deliver a current Icp+ΔIcp for a time interval equal to Tmin−ΔTmin, to satisfy the following relation:

Icp*T min=( Icp+ΔIcp )*( T min−Δ T min)  (3)

Illustrated by way of example in FIG. 6 are waveforms representing the currents generated by the two current generators of the charge pump, as well as the difference between the two currents, equal to the current Ifiltro at the filter 3 in the locked condition.

In particular, it should be noted that the total amount of charge supplied to the filter 3 is zero, it being given as the difference of two identical values.

This current Ifiltro generates a periodic variation in the filter voltage, in turn generating glitches at frequencies that are multiples of the reference frequency Fref. These glitches are directly proportional to the asymmetry of the current generators, ΔIcp, and the value of the “on” period Tmin of the generators, and are inversely proportional to the filter capacitance C 2 .

The contribution to the generation of glitches from the asymmetry of the current generators in applications for which strict settling time specifications are provided, is an order of magnitude larger than the contribution from leakage.

Therefore, the requirements for settling time values and glitch generation are difficult to meet simultaneously, especially in transmission systems designed to strict specifications. In fact, whereas to obtain limited durations of the settling time a large charge current Icp must be used for the charge pump along with a very small filter capacitance C 2 , the error percent between the current generators, and the respective turn-on times, should be quite small.

Conventional circuit designs, and technological limitations setting a minimum turn-on time for a current generator, make meeting the specifications very difficult.

Embodiments of this invention provide a phase lock loop which can minimize the generation of glitches and overcome the limitations of prior art circuits so as to meet, for example, the specifications established for transmission systems.

These embodiments avoid direct connection of the charge pump to the filter, thereby suppressing the glitch due to asymmetry between the current generators of the phase comparator.

Specifically, the invention relates to a circuit for minimizing glitches in phase-locked loops, of the type having an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. In one embodiment, a compensation circuit is placed between the charge pump generator and the filter.

The features and advantages of the device and the method according to the invention will become apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing a phase lock loop according to the prior art.

FIG. 2 is a schematic diagram showing a phase lock loop with a charge pump, according to the prior art.

FIG. 3 is a graph showing qualitative patterns of internal signals of the phase lock loop of FIG. 2 .

FIG. 4 is a schematic diagram showing a detail of the phase lock loop of FIG. 2 .

FIG. 5 is a graph showing the frequency spectrum of a VCO incorporated to the phase lock loop of FIG. 2 .

FIG. 6 is a graph showing qualitative patterns of further internal signals of the phase lock loop of FIG. 2 .

FIG. 7 is a schematic diagram showing a phase lock loop with a charge pump, according to an embodiment of the invention.

FIG. 8 is a schematic diagram showing a first embodiment of the phase lock loop of FIG. 7 .

FIG. 9 is a schematic diagram showing a detail of the phase lock loop of FIG. 7 .

FIGS. 10 a , 10 b and 10 c are graphs showing qualitative patterns of internal signals of the phase lock loops of FIG. 2 and FIG. 7 .

FIG. 11 is a schematic diagram showing a second embodiment of the phase lock loop of FIG. 7 .

Referring to the drawing views, the numeral 7 generally denotes a phase lock loop with a charge pump according to embodiments of this invention, shown in schematic form.

Similar to the loop 1 described above in connection with the prior art, the loop 7 has a terminal EXT that receives an external reference signal Sref and is connected to the input of a phase detector 8 . The phase detector 8 is further connected to a series of a charge pump generator 9 , a filter 10 , and a voltage controlled oscillator VCO 11 .

The oscillator VCO 11 is also fed back to the input of the phase detector 8 through a frequency divider 12 .

Advantageously in this embodiment, the loop 7 further includes a compensation circuit 13 connected between the charge pump generator 9 and the filter 10 . In particular, the compensation circuit 13 includes a storage element 14 connected in series with a controlled switch 15 . The switch 15 is controlled by a control signal Cpoff coming from the charge pump generator 9 .

The operation of the loop 7 according to this embodiment will now be described.

The switch 15 is controlled to open during the power-on of the current generators incorporated in the charge pump generator 9 . Thus, in the locked condition and in the presence of dissymmetry between said current generators, a filter current If will be flowing through the storage element 14 , allowing an amount of charge to build up in this element.

Actually, at the end of the conduction period of the generators inside the charge pump generator 9 , the charge built-up in the storage element 14 will be nil, as shown in FIG. 6 already discussed in connection with the prior art.

Thus, the provision of a compensation circuit 13 is effective to suppress the contribution from glitches appearing in the loop 7 .

Advantageously in this embodiment, the compensation circuit 13 , with its mechanism of charge build-up in the storage element 14 , will absorb the amount of charge passed through the charge pump generator 9 . In this way, any leakages from the generator or charge build-ups due to dissymetries on its inside are accommodated.

Shown in FIG. 8 is a first embodiment of the loop 7 of FIG. 7 . In particular, the storage element 14 comprises essentially a capacitor Cstorage connected between the output of the charge pump generator 9 and a voltage reference, such as a ground GND.

The capacitor Cstorage should be of limited capacitance not to affect the transfer function of the loop 7 as a whole. This implies a limited capability of the capacitor Cstorage of storing charge.

In particular, outside the locked condition of the loop 7 , the turning on of one of the two current generators in the charge pump generator 9 , being proportional to the difference between the reference signal Sref and a feedback signal Sdiv supplied to the input of the phase detector 8 from the frequency divider 12 , will generate too large an amount of charge for storing in the capacitor Cstorage.

To obviate this potential drawback, a second circuit portion can be added to the capacitor Cstorage as shown in FIG. 8 . Advantageously in this modification, the switch 15 comprises first SW 1 and second SW 2 elementary switches, connected in parallel with each other between the charge pump generator 9 and the filter 10 and respectively controlled by a signal LOCK from the phase detector 8 and a signal Cpoff from the charge pump generator 9 .

In particular, the first elementary switch SW 1 , controlled by the signal LOCK, closes when the loop 7 is not in a locked condition and opens when the phase difference between the signals Sref and Sdiv is smaller than a predetermined threshold value. The second elementary switch SW 2 , controlled by the signal Cpoff, opens before the turning on of the charge pump generator 9 and closes after this is turned off.

The switches and capacitors can be integrated simultaneously by present manufacturing techniques. There remains to be integrated the filter 10 .

The phase lock loop 7 of this embodiment will, when produced in an integrated circuit therefore, have the same number of pins and non-integratable components as a conventional loop.

In addition, the pair of elementary switches, SW 1 and SW 2 , are effective to retain the low resistance specifications outside the locked condition, by the switch SW 1 having a small equivalent resistance and reduced capacitance in the other conditions, and the switch SW 2 comprising small-size transistors, in particular smaller than those used in switch SW 1 .

It should be noted that the parasitic capacitances associated with the elementary switches SW 1 and SW 2 will cause charge to pass between the capacitor Cstorage and the filter even in the locked condition and absence of a leakage current, specifically upon the elementary switches changing of state.

This passage of charge through the second elementary switch SW 2 generates glitches, because of its disturbing effect on the state of the control node of the oscillator VCO 11 .

The passage of charge through the first elementary switch SW 1 produces a variation in the control voltage of the oscillator VCO 11 , which may result in a shift of the locked condition.

Accordingly, it will be expedient to minimize this charge passage inside the elementary switches SW 1 and SW 2 by designing them for compensation of charge upon changeover.

A possible circuit embodiment of a compensated elementary switch 16 is shown in FIG. 9 .

The switch 16 has an input terminal IN, an output terminal OUT, and a control terminal CONTROL. In particular, the control terminal of the first elementary switch SW 1 receives the signal LOCK (FIG. 8 ), and the control terminal of the second elementary switch SW 2 receives the signal Cpoff (FIG. 8 ), their respective input terminals being connected to the charge pump generator 9 and their respective output terminals being connected to the filter 10 .

The switch 16 of FIG. 9 includes a pass-gate PG 1 which is connected between the input terminal IN and the output terminal OUT and consists of a first NMOS transistor M 1 and a second PMOS transistor M 3 whose control terminals are coupled to the control terminal CONTROL.

In particular, the control terminal of the first transistor M 1 is connected to the control terminal CONTROL through a first inverter INV 1 , and the control terminal of the second transistor M 3 is connected to the control terminal CONTROL through a series of second INV 2 and third INV 3 inverters. Thus, the transistors M 1 and M 3 of the pass-gate PG 1 are driven in phase opposition, thereby ensuring compatibility of the switch 16 input with connection to both a ground reference and a supply terminal.

The switch 16 further comprises first M 2 a and second M 2 b NMOS compensation transistors having their source and drain terminals shorted together and connected to the input IN and output OUT terminals of the switch 16 . The compensation transistors M 2 a and M 2 b also have their control terminals connected together and to the control terminal CONTROL of the switch 16 through the series of the inverters INV 2 and INV 3 .

The transistors M 2 a and M 2 b are thus driven in phase opposition to the transistor M 1 .

Finally, the switch 16 comprises third M 4 a and fourth M 4 b PMOS compensation transistors which have their source and drain terminals shorted together and connected to the common source and drain terminals of the transistors M 2 a and M 2 b and to the input IN and output OUT terminals of the switch 16 , respectively. Furthermore, the compensation transistors M 4 a and M 4 b have their control terminals connected together and to the input terminal IN of the switch 16 through the inverter INV 1 .

Similar as the transistors M 2 a and M 2 b , the transistors M 4 a and M 4 b are driven in phase opposition to the transistor M 3 .

Advantageously in this embodiment, the size of the compensation transistors (M 2 a , M 2 b , M 4 a , M 4 b ) is chosen equal to one half the size of the transistors of the pass-gate PG 1 .

How this choice reflects in advantageous features of the inventive device will now be explained.

In the locked condition, the voltage at the input terminal IN is approximately equal to the voltage at the output terminal OUT. The gate-drain and gate-source capacitances of the first transistor M 1 are, therefore, identical.

With the transistor arrangement of this embodiment, the compensation transistors M 2 a and M 2 b have the same gate-source and gate-drain voltages as the first transistor M 1 of the pass-gate PG 1 . The paralleled gate-source and gate-drain capacitances of these compensation transistors with halved dimensions are equal to the corresponding capacitances of transistor M 1 .

In this condition, as the control terminal CONTROL changes its state, the gate nodes of the transistors M 2 a and M 2 b move in opposite directions to the gate node of the transistor M 1 , and the amount of charge injected thereby into the terminals IN and OUT is equal and opposite to the amount of charge injected by the gate-source and gate-drain capacitances of transistor M 1 . The compensation of transistor M 3 by transistors M 4 a and M 4 b is effected in a like manner.

By using a filter as described in relation to FIG. 9, a disturbance can be obtained which is by a few orders of magnitude less than the disturbance produced by the generator dissymmetry within the charge pump generator.

FIG. 10 shows comparative graphs illustrating the improved performance brought about by the phase lock loop of an embodiment of this invention compared with a prior art loop.

In particular, FIG. 10 ( a ) shows the evolution of current in a prior art loop; FIGS. 10 ( b ) and 10 ( c ) show the evolution of the current through the switch during the on and off transitions respectively according to a tested embodiment of the invention.

It can be seen that the amount of charge injected into the filter upon the switch in the loop of this embodiment opening and closing is 100 times less than in prior solutions.

An additional advantage of the phase compensation loop according to this embodiment is that the glitches originated by the leakage current of the charge pump generator 9 are halved.

In applications where glitches are to be specially small, prior art arrangements were obliged to use VCOs with minimal leakage currents, as previously pointed out. In this condition, the leakage current of the VCO takes the same order of magnitude as the leakage current of the charge pump generator, thereby playing an important role as regards compliance with design specifications.

The phase compensation loop of this embodiments of the invention allows the contribution from the leakage current of the charge pump generator to be cut down by one half through a modification of its operating principle. Particularly in the loop, the second elementary switch SW 2 is controlled to open with a half-period delay from its close, thereby halving the filter voltage discharge due to the leakage current of the charge pump generator.

This modification can be acquired to the operating principle of the charge pump generator by using a flip-flop 17 of the set/reset type connected to a control terminal of said generator, as shown schematically in FIG. 11 .

In particular, the flip-flop 17 would be set by the turn-off signal of both internal generators of the charge pump generator 9 , and reset by the trailing edge of the reference signal Sref.

It should be considered that, to arrive at the embodiment shown in FIG. 11, the phase detector 8 has been assumed to compare the signals at the raising edges, and the duty cycle of the reference signal Sref assumed to be 50%.

Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.