Dynamic control of phase-locked loop

This application claims priority from co-pending U.S. Provisional Patent Application No. 60/318,814 filed Sep. 13, 2001 for Dynamic Control of a Phase-Locked Loop.

This invention relates to communications systems and methods, in particular, to Phase-Locked Loops.

Phase-Locked Loops (PLLs) are commonly used for synthesis of a smoothed clock from an irregular or jittered input clock. The smoothed clock runs at the frequency of the input clock but does not contain the some or all of the jitter present in the input clock signal. FIG. 1 shows a block diagram for a basic PLL.

A PLL like that shown in FIG. 1 is a linear system. The Phase Detector 108 measures the difference between the phase of the Input Clock 104 and the phase of the Output Clock 128 . This difference, known as Phase Error 112 , is then passed through a Low Pass Filter (LPF) 116 that attenuates the high-frequency components to produce a Filtered Phase Error 120 . (One type of low pass filter is sometimes called an “integrator”.) The Filtered Phase Error 120 is then fed into a Voltage-Controlled Oscillator (VCO) 124 . The Output 132 of the VCO 124 is fed back to the Phase Detector 108 as the Reference Clock Value 140 , after passing through a Divider 136 . The Divider adjusts the frequency of the Reference Clock Value 140 to match the frequency of the Input Clock 104 as is necessary when the frequency of the Output 132 of the VCO 124 is set to be an integer multiple of the Input Clock frequency.

This type of system is a feedback system, and when operating properly it tends to drive the Phase Error 112 to zero (or some small value) and the Output Clock 128 will track the Input Clock 104 , or at least the desired frequency components thereof.

FIG. 2 shows a typical PLL application. The jittered Input Clock 104 is used to clock Input Data 206 into the FIFO Buffer 208 . It is also used as an input to the PLL 204 , which provides a smoothed clock as an output 128 . The smoothed Output Clock 128 is also used to clock “smooth” Output Data 210 out of the FIFO Buffer 208 that is being used as a buffer to absorb jitter from jittered Input Data 206 .

A PLL has a number of parameters that are selected at design time:

Gain of the phase detector−K P

Gain low pass filter (LPF)−K F

Gain of the Voltage Controlled Oscillator (VCO)−K V

Natural frequency of the low pass filter−ω N

The divide by value used in the divider−N

The parameters control the PLL's operational characteristics as follows:

Frequency response and cutoff frequency: F C =ω N /2π

Transient response and settling time: Ts≈1/(2*F C )

Steady-state phase error: E=F in /[F center (1+K)] where F center is the nominal frequency of the VCO.

Tracking range: R=R 0 /(1+K) where R 0 is the nominal range of the VCO.

These operational characteristics are all inter-related. Thus, changing one parameter tends to change more than one of the operational characteristics. The design and operation of Phase-Locked Loops is within the skill of one of ordinary skill in the art. General information on this topic is readily available and thus will not be described here in any detail. Textbooks describing the design of Phase-Locked Loops include 1) Floyd Martin Gardner, “Phaselock Techniques”, John Wiley & Sons, ISBN: 0471042943; 2) Roland E. Best, “Phase-Locked Loops: Design, Simulation, and Applications”, McGraw-Hill Professional Publishing, ISBN: 0071349030; and 3) John J. D'Azzo, “Linear Control System Analysis and Design”, McGraw-Hill, ISBN 0070161836.

The values are chosen based on knowledge of the input signal as well as the system requirements. The choice of the design parameters affects the performance of the PLL in such areas as stability, acquisition and tracking bandwidth and noise rejection. Fixed (“static”) parameters mean that the PLL may not be operating in the optimal fashion as the characteristics change for the input signal.

A linear control system like a PLL can be highly optimized when the characteristics of the input signal vary only slightly. A system that worked fine for one type of input signal may not work well as the input changes. A dynamic system allows the PLL to treat the varying input in a piecewise linear fashion, giving optimum performance in each set of input conditions.

The range of values on the input signal may exceed the dynamic range of some of the PLL components. In this case, a system with fixed parameters might not work at all in some situations. A dynamic system can overcome this limitation.

Some of the PLL parameters affect multiple performance metrics such that improving one metric has a deleterious affect on another metric. For example, acquisition range and noise rejection are usually inversely proportional. A dynamic system can increase the noise rejection in the domains where the input is well behaved, and a wide acquisition range is therefore not needed.

Prior art designs fixed the values of the PLL parameters so the PLL was optimized for one set of input conditions. In some cases specialized PLLs had more than one set of fixed PLL parameters for the PLL to operate in two different modes. For example, the prior art includes the concept of a PLL that uses a more stringent set of parameters for clock signal tracking after the PLL locks onto a clock signal. This is switching the mode of operation of the PLL to perform a different function (signal tracking versus signal acquisition).

Likewise some PLLs are adapted to work with two or more different frequencies of different values. Again, the PLL can be set to one mode or another based on the frequency that is expected, but the PLL does not have dynamically adjusted parameters to react to changes in the behavior of the expected input. More specifically, if the jitter associated with an input signal changes over time, the PLL does not react by changing PLL characteristics to adjust for the increased jitter.

In February of 2002, Altera Corporation announced a new programmable logic device, the Stratix™. This device has extended support for phase-locked loops. The features include PLL reconfiguration that gives designers flexibility in multiplying or dividing input clock frequencies to achieve higher or lower output clock frequencies and allows real-time variations of the PLL frequency and output clock skew. StratixTM frequency synthesis and programmable delay features can be changed by users on-the-fly; for example, designers can modify the PLL output frequencies and clock delays in prototype environments. This feature allows for PLL reconfiguration without reprogramming the rest of the chip. Furthermore, during system debugging, users can change the certain PLL parameters to optimize the system timing.

However, while a designer has additional control over frequency and clock skew, Altera documentation specifically excludes dynamic adjustment of the PLL loop filter components. Thus, although the Altera device facilitates development of PLL functions on a programmable logic device, it does not support or suggest the use of dynamic control of PLL parameters to adapt to changes in the characteristics of a received clock signal.

It is therefore an object of the invention to provide dynamic control of a PLL based on the real time characteristics of the input signal.

Several versions are disclosed of a Phase-Locked Loop with a control system to provide dynamic automatic adjustment to changes in one or more characteristics of the Phase-Locked Loop in response to changes in the jitter level of the input. These Phase-Locked Loops are responsive to changes in the input to the Phase-Locked Loops so that the operation of the Phase-Locked Loops can more closely approximate optimal settings for various levels of input jitter. One version of the invention compares a monitored jitter value against control state set points and upon detection of movement across a set point, changes one or more operating parameters of the Phase-Locked Loop. Various versions of the invention use different inputs and modify different operating parameters in order to achieve the objective of an automatic dynamic alteration of a Phase-Locked Loop in response to a change in jitter level of the input.

A version of the disclosed invention can be used as part of a circuit emulation system to receive circuit emulation payloads. In this version of the invention, the phase detector portion of the PLL is the jitter absorption buffer and the PLL uses a filtered jitter absorption buffer depth to vary the clock speed. This version of the invention uses a periodic sample of the difference between the highest and lowest levels of the jitter absorption buffer as a metric for network conditions. This metric is used by the control system to select the appropriate set of parameters for use by the PLL.

FIG. 1 shows a block diagram for a basic PLL as known in the prior art.

FIG. 2 shows a typical PLL application. The PLL is taking a jittered clock as an input, and providing a smoothed clock as an output, thus smoothing the clocking function for FIFO Buffer 208 .

FIG. 3 shows a system to provide dynamic control of a PLL based on the real time characteristics of the input signal.

FIG. 4 is a state machine representing one preferred embodiment of the present invention.

FIG. 5 is one implementation of the present invention using a Jitter Absorption Buffer as the phase detector.

In a preferred embodiment of the present invention, there are three control states, each with its own values of the PLL parameters. This invention can be extended to any system that dynamically changes from one set of coefficients to another based on current conditions. Thus, the number of states can be any number two or larger. Two states would probably be too coarse. It is currently felt that the optimal number of states would be from three to five states to avoid having an unduly complex system. This disclosure will explain the concept through the use of a three state example.

Likewise, the preferred embodiment of the present invention measures the current estimate of variation or jitter of the input signal, denoted J. One preferred method for estimating jitter is set forth in co-pending patent application Ser. No. 10/200,418 by Pate et al. with title Measurement of Packet Delay Variation based on earlier filed provisional patent application No. 60/307,747. The 418 application is incorporated by reference.

In a preferred embodiment, the current estimate of variation or jitter of the Input Signal 110 is used to trigger the state transitions as shown in FIG. 4 . As shown in FIG. 3, alternative embodiments could use the jitter of the Input Clock 104 , Reference Clock Value 140 , or the jitter of the Filtered Phase Error 120 for triggering state transitions. The unfiltered Phase Error 112 could also be used for triggering state transitions. However, when using the unfiltered Phase Error 112 , it is likely that the Analysis Block 304 (discussed below) would need its own low pass filter so that control state decisions were not unduly influenced by high frequency components of the unfiltered Phase Error 112 .

Finally, the preferred embodiment of the present invention only manipulates a single value for K. Since the PLL characteristics are controlled by the product K P K F K V (i.e. the individual values are not distinct with respect to operation of the PLL), the gains K P , K F and K V may be consolidated into a single effective gain denoted K. The constants K P , K F and K V could be manipulated separately if needed, as in an implementation where truncation errors in calculations are significant. For example, if increasing K P to a certain value in the Phase Detector 108 caused a fixed point calculation to overflow, the same effect could be accomplished by increasing K P to a lesser amount and instead increasing K F at the Low Pass Filter 116 and/or K V at the VCO 124 a corresponding amount.

These concepts are illustrated in FIG. 3, which is a modification of FIG. 2 . The modification adds an Analysis Block 304 and a Parametric Control Block 308 . As shown in FIG. 3, the Analysis Block 304 receives one or more inputs from the PLL operation as mentioned above. In the preferred embodiment the Analysis Block 304 performs a comparison between the input variable and constants that mark the transition points between one state and another, such as the transition from low to medium. As described below, this simple comparison can be modified to have a dead band to prevent chatter. Those of skill in the art realize that the Analysis step could include filtering or be based on a function of two or more inputs, though simplicity favors a simple comparison based on a single input. (Note while it may seem redundant to have a filter in the Analysis Block 304 , having a filter in Analysis Block 304 could be useful when the designer opts for a responsiveness in the Analysis Block 304 that is different from the desired responsiveness of the VCO 124 .)

The output of the Analysis Block 304 triggers the change in the Parametric Control Block 308 . As shown in FIG. 3, the parametric control block can impart changes on the gains of one or more of the various components or the value of ω N . A preferred embodiment set forth in the state machine of FIG. 4, manipulates both gain and ω N , thus illustrating that more than one parameter can be varied within the scope of the present invention.

FIG. 4 in combination with Tables 1 and 2 illustrates one preferred embodiment of the present invention. In this preferred embodiment the three states are:

Low—This is the steady state when the current value of J is low as defined by the threshold L.

Medium—This is the steady state when the current value of J is medium as defined by the thresholds L and M.

High—This is the steady state when the current value of J is high as defined by the threshold M.

Note that there are no timers in this state machine. Hysteresis could be introduced to prevent minor changes in J from triggering changes in the coefficients when J is approximately equal to L or to M. For example, the state changes would occur at L plus a first delta and L minus a second delta rather than at L. The preferred embodiment would have first delta equal to second delta so there is a dead band of width two times delta, centered on L. Table 1 shows the state transitions for each range of J.

Table 2 shows the values of K and ω N for each state.

Note that the values of ω N and K vary with the measured jitter such that the responsiveness of the PLL increases with increasing jitter.

The cutoff frequency increases with jitter

The settling time is shorter as jitter increases

The tracking range is greater

The net effect of increased responsiveness is that the PLL tracks (instead of removes) more of the jitter, reducing the likelihood of overrunning any jitter buffers that may be in the system. For example, consider the system shown in FIG. 2 . The FIFO might overrun or underrun if the cutoff frequency of the PLL is set too low. Thus, there is a tradeoff between removing as much of the high frequency jitter as possible and having the output clock respond to low frequency jitter in order to reduce the risk of buffer underflow or overflow. The present invention adjusts the operating parameters to optimize performance of the PLL based on the current operating conditions.

In some applications, the change of parameters may cause the designer to take special steps to assure smooth operation of the Phase-Locked Loop. A change in natural frequency of an exponentially smoothed filter will not normally cause a disruption due to the memory factor of the filter i.e. the change is inherently smoothed over time. However, a change to the gain or divider may cause a step change in frequency that is undesirable. Depending upon the application, the designer may need to limit the size of the change. One way to do this is to limit the slew rate of the VCO, such that it cannot make large step changes in frequency.

One of skill in the art could implement the teachings of the present invention with a linear equation to adjust one or more controlled parameters of the PLL based on one or more monitored inputs. However, as described above, the preferred embodiment uses two or more states with fixed values for the controlled parameters.

In order to provide additional information to help illustrate the many ways that this present invention can be implemented, applicants provide the following details on an unusual implementation of the present invention.

FIG. 5 illustrates the general progression from Transmit Bits 10 from a first circuit through Encapsulating Device 14 to Transmit Packets 20 through the Packet Network 24 to Arriving Packets 30 through de-encapsulation and a Jitter Absorption Buffer (JAB) 34 to become a stream of Receive Bits 40 . Consider a CBR (constant bit rate) application where the bits are created at constant rate R. The rate R remains constant because there are no pauses in the data stream. The application at the receiving end is typically set to receive and process bits at a clock speed proportional to the same rate R. On the path from creation to processing at the receive end the Transmit Bits 10 first arrive at a device that encapsulates them into packets and injects the Transmit Packets 20 into a Packet Network 24 at rate P. Just as the bits arrive from the application at regular intervals, the Encapsulating Device 14 sends out Transmit Packets 20 at regular intervals. However, the intervening packet network is not perfect, so it introduces packet delay variation (PDV) due to congestion.

A system that is receiving packets from a network that introduces PDV will see the incoming packets arrive at a rate that over a large period of time averages out to be the creation rate P (assuming packets are not lost entirely and the packet size is fixed). But from moment to moment, the receive rate varies as congestion in the network causes variation in the amount of time for a packet to traverse the network. The Arriving Packets 30 are processed at the receive end and the various headers and overhead are removed before the remaining payload data is placed into the JAB 34 . The data stream of bits leaving the JAB 34 are clocked by Reference Clock Value 140 . The JAB 34 buffers the system by having a queue of received payload data so that a steady stream of receive bits 40 can be released.

One of skill in the art should appreciate that the transmission of bits at a constant bit rate serves as a clock signal and the irregularities associated with the receipt of bits at the JAB reflects jitter in the received clock signal. As the JAB receives this jittered clock signal and the Reference Clock Value 140 , the JAB 34 can serve as the Phase Detector 108 . (Actually, it is more robust than classic phase detectors as a classic phase detector has the capacity to measure phase errors up to ±179.9 degrees and the JAB is not limited in this way).

The JAB depth/Phase Error 112 is periodically passed to the Low Pass Filter 116 . In one preferred embodiment, the JAB depth is measured in bytes of payload data. In a preferred embodiment, the Low Pass Filter 116 implements a smoothing function on the values passed from the JAB and thus implements an exponential filter to provide the functionality of a low pass filter. The Filtered Phase Error 120 is then fed into a Voltage-Controlled Oscillator (VCO) 124 . The Output 132 of the VCO 124 is fed back to the Phase Detector 108 as the Reference Clock Value 140 , after passing through a Divider 136 .

Variations of the JAB depth over time are used to create a metric that represents certain components of packet delay variation (jitter). A preferred metric is the periodic subtraction of the lowest JAB depth for a period of time (LWM) from the highest JAB depth for a period of time (HWM). This Metric 110 is provided to the Analysis Block 304 which drives the Parametric Control Block 308 . The Parametric Control Block 308 impacts changes to the smoothing function in the Low Pass Filter 116 which impacts the gain for the low pass filter (K F ) and the natural frequency of the low pass filter (ω N ).

The system as shown in FIG. 5 is useful for implementing adaptive timing for the drain rate of the JAB 34 . For example, an application using a T 1 line uses a rate centered on 1.544 Mbps but this rate can be adjusted up or down by up to 50 ppm. This tends to center the depth of the JAB as some prescribed center value. As shown in FIG. 5, the output 40 of the JAB 34 can be clocked by the Reference Clock Value 140 and provided to a T 1 Transceiver 44 which further processes the data to provide a T 1 Output Stream 48 . This example is to further illustrate industrial applicability, however, and feeding a T 1 Transceiver or another constant bit rate transceiver is certainly not a requirement of the present invention.

In a co-pending application Ser. No. 10/190,416 for Use of a Circular Buffer to Assure In-Order Delivery of Packets teaches methods that avoid a rapid change in the adaptive timing resulting from the transmission loss of a packet. The '416 application claims priority from U.S. Provisional Patent Application No. 60/304,062 for Use of A Circular Buffer to Assure In-Order Delivery of Packets. Note that the teachings of the present application can be implemented without the implementation of the teachings of the '416 application.

In order to promote clarity in the description, common terminology for components is used. The use of a specific term for a component suitable for carrying out some purpose within the disclosed invention should be construed as including all technical equivalents which operate to achieve the same purpose, whether or not the internal operation of the named component and the alternative component use the same principles. The use of such specificity to provide clarity should not be misconstrued as limiting the scope of the disclosure to the named component unless the limitation is made explicit in the description or the claims that follow.

Those skilled in the art will recognize that the methods and apparatus of the present invention have many applications and that the present invention is not limited to the specific examples given to promote understanding of the present invention. Moreover, the scope of the present invention covers the range of variations, modifications, and substitutes for the system components described herein, as would be known to those of skill in the art.

The legal limitations of the scope of the claimed invention are set forth in the claims that follow and extend to cover their legal equivalents. Those unfamiliar with the legal tests for equivalency should consult a person registered to practice before the patent authority which granted this patent such as the United States Patent and Trademark Office or its counterpart.