Semiconductor memory device

This application relies for priority upon Korean Patent Application No. 2001-55949, filed on Sep. 11, 2001, the contents of which are herein incorporated by reference in their entirety.

The present invention relates to a semiconductor memory device having a redundancy function. Also the invention relates to a semiconductor memory device to enhance a data access speed.

As a memory unit, a memory cell must stably store data that is processed in a system. Accordingly, there is a requirement for a procedure to test respective memory cells.

A redundancy circuit is a spare circuit, built into a memory device, for replacing defective cells with redundant memory cells. When an external address addressing a defective cell is input, the redundancy circuit disables a wordline organically connected to the defective cell and accesses a redundancy memory cell corresponding to the defective cell.

A semiconductor memory device must have a function to be instantly responsive to a central processing unit (CPU) speed, which is the most ideal requirement of system users. What is needed for having that function is to reduce the load of respective signal lines for transmitting a data access signal. Japan Laid-Open Application No. 7-182892 (filed on Dec. 22, 1993) discloses a semiconductor memory device having a hierarchical row decoder coupled to a main wordline, which can repair a defect without an increase in the number of redundancy main wordlines and occupy a minimal circuit area. Japan Laid-Open Application No. 8-340089 (filed on Mar. 2, 1995) discloses a DRAM device which can achieve a high speed by lowering the resistance of metal interconnections. Japan Laid-Open Application No. 10-308091 (filed on Mar. 2, 1997) discloses a semiconductor memory device which can suppress increase in the power consumption and achieve a high speed and a smaller occupied area while keeping the advantages of a hierarchical wordline. Japan Laid-Open Application No. 10-320979 (filed on Apr. 14, 1998) discloses a semiconductor memory device which can enhance a transmission speed and improve an integration level by shortening interconnections. U.S. Pat. No. 5,764,585 (filed on Jun. 7, 1996) discloses a DRAM device having a plurality of main row decoders each being coupled to one main wordline, and a plurality of sub-row decoders each being coupled to the one main wordline and a plurality of sub-wordlines, which can enhance an access speed of the device by reducing the load of the main row decoders. These above prior art devices are oriented toward a high speed by improving a chip layout,

Referring now to FIG. 1, a conventional DRAM device includes a plurality of memory cell arrays 10 , 12 , and 14 having a plurality of memory cells, a main row decoder 16 , a plurality of main wordlines MWL 0 -MWL 63 , a predecoder 30 , an address program circuit 32 , a redundancy main wordline RMWL, sub-row decoders ah, and redundancy sub-row decoders i-p. Now, wordlines crossing over a plurality of memory cell arrays and their drivers are described in detail below. For reference, an external address used in the following discussion is XA 0 -XA 8 .

The main row decoder 16 activates one of 64 main wordlines MWL 0 -MWL 63 according to an external row address XA 3 -XA 8 . Each of the main wordlines MWL 0 -MWL 63 is connected to one side of the main row decoder 16 and is horizontally arranged over the memory cell arrays 10 , 12 , and 14 . Each of sub-row decoders a, c, e, and g is disposed between the memory cell arrays 12 and 14 , and is connected to a main wordline through a corresponding one of sub-wordlines SW 0 , SW 2 , SW 4 , and SW 6 crossing over the memory cell array 12 and 14 . Each of sub-row decoders b, d, f, and h is disposed between the memory cell arrays 10 and 12 , and is connected to a main wordline through a corresponding one of sub-wordlines SW 1 , SW 3 , SW 5 , and SW 7 crossing over the cell arrays 10 and 12 .

The predecoder 30 activates one of eight predecoding lines SWPD 0 -SWPD 7 according to an external row address XA 0 -XA 2 . Each of the predecoding lines SWPD 0 -SWPD 7 is horizontally arranged over the memory cell arrays 10 , 12 , and 14 and is vertically arranged therebetween, coupling each of corresponding sub-row decoders a-h to one side of the predecoder 30 . In other words, each of the predecoding lines SWPD 0 -SWPD 7 is coupled to 64 sub-row decoders.

The address program circuit 32 receives the same address XA 3 -XA 8 as an external address inputted to the main row decoder 16 during a repair operation, activating a redundancy main wordline RMWL. The redundancy main wordline RMWL is coupled to one side of the address program circuit 32 and is horizontally arranged over the memory cell arrays 12 - 14 . Each of redundancy sub-row decoders i, k, m, and l is disposed between the memory cell arrays 12 and 14 , and couples a corresponding one of redundancy sub-wordlines RSWL 0 , RSWL 2 , RSWL 4 , and RSWL 6 to the redundancy main wordline RMWL. Each of redundancy row decoders j, l, n, and p is disposed between the memory cell arrays 10 and 11 , and couples a corresponding one of redundancy sub-wordlines RSWL 1 , RSWL 3 , RSWL 5 , and RSWL 7 to the redundancy main wordline RMWL.

The operations of the above semiconductor memory device are now described in detail. Each of the main wordlines MWL 0 -MWL 63 is activated according to the combination of external row addresses XA 3 -XA 8 . For example, when all external row addresses XA 3 -XA 8 inputted to the main row decoder 16 are ‘0’ (i.e., ‘000000’), only the main wordline MWL 0 is activated and the others, MWL 1 -MWL 63 , are inactive.

The predecoder 30 activates one of eight predecoding lines SWPD 0 -SWPD 7 according to an external row address XA 0 -XA 2 . For example, when all row addresses XA 0 -XA 2 are ‘0’ (i.e., ‘000’), the predecoding line SWPD 0 is activated and the other predecoding lines SWPD 1 -SWPD 7 are inactive.

As previously described, each of the sub-row decoders a-h is coupled to one of the main wordlines MWL 0 -MWL 63 through a corresponding sub-wordline. Therefore, each of the sub-row decoders a-h is activated when both a main wordline and a predecoding line, which are organically coupled to each other, are activated. As described in the example above, when the 0th main wordline MWL 0 and the 0th predecoding line are activated, only the sub-row decoder “a” is activated. Therefore, the sub-row decoder “a” activates memory cells coupled to the sub-wordline SW 0 .

The most ideal case is that a predecoding signal on the predecoding line SWPD 0 is supplied to only the sub-row decoder “a” coupled to the activated 0th main wordline MWL 0 . As shown in FIG. 1, however, the predecoding signal is supplied to all the sub-row decoders “a” coupled to the 63 main wordlines MWL 1 -MWL 63 as well as the activated main wordline MWL 0 (i.e., the predecoding signal is supplied to all the 64 sub-row decoders “a”), which becomes a load of the predecoding line SWPD 0 . From the standpoint of a signal, the data access signal on the predecoding line is subjected to a considerable physical resistance when it is supplied to the final cell. Therefore, the data access speed of the conventional memory device is reduced.

A repair is needed when a defective cell is created by various causes during a wafer fabricating process. When an external address for accessing a defective cell is inputted, a redundancy circuit disables a wordline coupled to a defective cell and enables a redundancy wordline. The conventional memory device of FIG. 1 carries out the repair with a main wordline unit. For example, when there are defective cells coupled to the sub-wordline SWL 1 among cells in the memory cell array 12 , operations of the memory device are described below.

As mentioned above, the sub-wordline SWL 1 is activated when the main wordline MWL 0 and the predecoding line SWPD 1 are activated, i.e., an external address is ‘001000000’. Therefore, when an address XA 0 -XA 8 (i.e., ‘001000000’) for selecting a sub-wordline SWL 1 coupled to a defective cell is inputted, an address program circuit 32 disables the main row decoder 16 and activates a corresponding redundancy main wordline RMWL and a predecoding line SWPD 1 . As a result, all memory cells coupled to the 0th main wordline MWL 0 are replaced by a redundancy main wordline RWML.

FIG. 2 illustrates a partial circuit construction of a main row decoder 16 associated with a 0th main wordline MWL 0 and a partial circuit construction of a predecoder 30 associated with a 0th predecoding line SWPD 0 .

Referring now to FIG. 2, an address program circuit 32 compares an externally inputted row address XA 3 -XA 8 with an address stored therein. According to the comparing result, the address program circuit 32 generates a redundancy enable signal RED_E indicating a normal mode or a repair mode. That is, if the externally inputted row address XA 3 -XA 8 match up to the address stored in the address program circuit 32 , the control signal becomes high (i.e., logic ‘1’) to enter a repair mode. Otherwise, the control signal becomes low (i.e., logic ‘0’) to exhibit a normal mode.

Components for activating a 0th main wordline MWL 0 in a main row decoder 16 are a decoder 40 , an inverter 44 , and a buffer 45 . Since components for activating the other wordlines MWL 1 -MWL 63 are identical to the components for activating the 0th main wordline MWL 0 , only a circuit construction associated with the 0th main wordline MWL 0 is illustrated and described at this time. The decoder 40 has NAND gates 41 - 43 and outputs a signal for activating the 0th main wordline MWL 0 when all the external row addresses XA 3 -XA 8 are low (i.e., ‘000000’) while a redundancy enable signal RED_E outputted from an address program circuit 32 is high. The buffer 45 converts the level of a signal outputted from the decoder 40 into the level suitable for driving the main wordline MWL 0 , and outputs the signal having the converted level.

Components for activating a 0th predecoding line SWPD 0 in the predecoder 30 are an AND gate 51 and a buffer 52 . Since components for activating the others SWPD 0 -SWPD 7 are identical to the components for activating the 0th predecoding line SWPD 0 , only a circuit construction associated with the 0th predecoding line SWPD 0 is illustrated and described at this time. The AND gate 51 outputs a signal for driving the predecoding line SWPD 0 when the address XA 0 -XA 2 is ‘000’. The buffer 52 converts the level of a signal outputted from the decoder 51 into the level suitable for driving the predecoding line SWPD 0 , and outputs the signal having the suitable level.

A buffer 60 converts the level of a redundancy enable signal RED_E outputted from the address program circuit 32 into the level suitable for driving the redundancy main wordline RMWL, and outputs the signal having the suitable level. Also the buffer 60 may be built in the address program circuit 32 .

The conventional memory device having the foregoing structure carries out a normal mode when the control signal RED_E outputted from the address program circuit 32 is low. When the control signal RED_E is high, the conventional memory device carries out a repair mode where the redundancy main wordline RMWL is activated.

Unfortunately, even when only one of sub-wordlines coupled to one main wordline fails, all the sub-wordlines must be replaced by redundancy sub-wordlines in the repair mode. That is, a repair is performed with a wordline unit. Accordingly, a redundancy flexibility is reduced and a circuit area is increased.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for a semiconductor memory device which realizes a high-speed operation by alleviating the load of a predecoding line. There is also a need for a semiconductor memory device to enhance a redundancy flexibility. What is also needed is a semiconductor memory device where circuit areas are reduced.

Accordingly, a semiconductor memory device is provided that includes at least one main wordline, a plurality of sub-wordlines corresponding to the main wordline, a plurality of main memory cells each being coupled to the sub-wordlines, a main wordline selector for activating the main wordline according to an external address, at least one redundancy sub-wordline, a plurality of redundancy sub-wordlines corresponding to the redundancy main wordline, a plurality of redundancy memory cells each being coupled to the redundancy sub-wordlines, a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline.

Beneficially, the number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline. The redundancy control circuit enables the main wordline selector when among the sub-wordlines, a sub-wordline to which a normal main memory cell is coupled is addressed.

In one embodiment the redundancy control circuit has at least fuse circuit that stores a row address of the defective main memory cell and compares the stored address with an externally inputted address. If the addresses match up to each other, the fuse circuit generates a redundancy enable signal. The main wordline selector is enabled/disabled according to the redundancy enable signal.

FIG. 1 illustrates a conventional memory device.

FIG. 2 illustrates circuit constructions associated with a redundancy operation of the memory device shown in FIG. 1 .

FIG. 3 A and FIG. 3B illustrate a memory device according to one of more aspects the present invention.

FIG. 4 illustrates circuit constructions associated with a redundancy operation of the memory device shown in FIG. 3 A and FIG. 3 B.

FIG. 5 illustrates a detailed circuit construction of a fuse circuit of FIG. 4 .

A semiconductor memory device (DRAM) disclosed herein includes a plurality of sub-wordlines corresponding to a main wordline, a plurality of sub-wordlines corresponding to a redundancy main wordline, a plurality of redundancy memory cells each being coupled to the redundancy sub-wordlines, and a redundancy control circuit. In addressing a sub-wordline to which a defective memory cell is coupled, the redundancy control circuit disables a sub-wordline selector and controls the sub-wordline to be replaced by the redundancy main wordline. Particularly, because the number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than that of the sub-wordlines coupled to the main wordline, redundancy flexibility can be improved and the circuit area can be reduced.

The present invention will now be described more fully hereinafter with reference to accompanying drawings.

Referring to FIGS. 3A-B, there is illustrated a block diagram of a memory device. The memory device includes memory cell arrays 101 , 102 , and 103 having a plurality of memory cells, a first predecoder 110 , a first main row decoder 120 , first main wordlines MWL 0 -MWL 31 , second main wordlines MWL 32 -MWL 63 , a second predecoder 140 , an address program circuit 150 , redundancy main wordlines RMWL 0 -RMWL 3 , and a redundancy predecoder 160 . The first main wordlines MWL 0 -MWL 31 are coupled to the first main row decoder 120 and are horizontally arranged over the memory cell arrays 101 , 102 , and 103 . The second main wordlines MWL 32 -MWL 63 are coupled to the second main row decoder 130 and are horizontally arranged over the memory cell arrays 101 , 102 , and 103 . The redundancy main wordlines RMWL 0 -RWML 3 are coupled to the address program circuit 150 and are horizontally arranged over the memory cell arrays 101 , 102 , and 103 .

The first predecoder 110 activates one of eight predecoding lines SWPD 0 -SWPD 7 according to an external address /XA 8 . Each of the predecoding lines SWPD 0 -SWPD 7 is horizontally arranged over the memory cell arrays 101 , 102 , and 103 , and is vertically arranged therebetween, connecting each of the corresponding sub-row decoders a-h to one side of the predecoder 110 .

The second predecoder 140 activates one of eight predecoding lines SWPD 8 -SWPD 15 according to an external address XA 8 . Each of the predecoding lines SWPD 8 -SWPD 15 is horizontally arranged over the memory cell arrays 101 , 102 , and 103 , and is vertically arranged therebetween, connecting each of the corresponding sub-row decoders p-w to one side of the predecoder 140 . The predecoding lines SWPD 0 -SWPD 7 and SWPD 8 -SWPD 15 are connected to 32 sub-row decoders, respectively. Accordingly, as compared to the prior art where 64 sub-row decoders are connected to one predecoding line, a load of the predecoding line is reduced to enhance a data access speed by a factor of two times or more.

The first main row decoder 120 activates one of the first main wordlines MWL 0 -MWL 31 according to an external row address XA 3 -XA 7 . Each of the first main wordlines MWL 0 -MWL 31 is coupled to one side of the first main row decoder 120 and is horizontally arranged over the memory cell arrays 101 , 102 , and 103 . Each of the sub-row decoders a, c, C, and g is disposed between the memory cell arrays 102 and 103 , and is coupled to a main wordline through corresponding one of sub-wordlines SW 0 , SW 2 , SW 4 , and SW 6 crossing over the memory cell arrays 102 and 103 . Each of the sub-row decoders b, d, f, and h is disposed between the memory cell arrays 101 and 102 , and is coupled to a main wordline through corresponding one of sub-wordlines SW 1 , SW 3 , SW 4 , and SW 7 crossing over the cell arrays 101 and 102 .

The second main row decoder 130 activates one of the second main wordlines MWL 32 -MWL 63 according to the external row address XA 3 -XA 7 . Each of the second main wordlines MWL 32 -MWL 63 is coupled to one side of the second main row decoder 130 , and is horizontally arranged over the memory cell arrays 101 , 102 , and 103 . Each of the sub-row decoders p, r, t, and v is disposed between the memory cell arrays 102 and 103 and is coupled to a main wordline through corresponding one of sub-wordlines SW 8 , SW 10 , SW 12 , and SW 14 crossing over the cell arrays 102 and 103 . Each of the sub-row decoders q, s, u, and w is disposed between the memory cell arrays 101 and 102 , and is coupled to a main wordline through corresponding one of sub-wordlines SW 9 , SW 11 , SW 13 , and SW 15 .

The address program circuit 150 activates redundancy main wordlines RMWL 0 -RMWL 3 by receiving an external address XA 1 -XA 8 except an external address XA 0 . The redundancy main wordlines RMWN 0 -RMWL 3 are coupled to one side of the address program circuit 150 , and are horizontally arranged over the memory cell arrays, 101 , 102 and 103 .

The redundancy predecoder 160 activates one of two predecoding lines according to the external row address XA 0 . Each of predecoding lines RSWPD 0 -RSWPD 1 is horizontally arranged over the cell arrays 101 , 102 , and 103 and is vertically arranged therebetween, coupling each of corresponding sub-row decoders i-p to one side of the redundancy predecoder 160 .

Each of the redundancy sub-row decoders i, k, m, and o is disposed between the memory cell arrays 102 and 103 , and couples the redundancy sub-wordlines RSWL 0 , RSWL 2 , RSWL 4 , and RSWL 6 to the redundancy main wordlines RMWL 0 -RMWL 3 , respectively. Each of the redundancy sub-row decoders j, 1 , n, and p is disposed between the memory cell arrays 101 and 102 , and couples redundancy sub-wordlines RSWL 1 , RSWL 3 , RSWL 5 , and RSWL 7 to the redundancy main wordlines RMWL 0 -RMWL 3 , respectively.

According to this embodiment, in controlling the redundancy row decoders i-o, two redundancy sub-wordlines are coupled to each of the redundancy main wordlines and the redundancy predecoder 160 is constructed to be separate from the main predecoders 110 and 140 . As a result, redundancy flexibility can be improved.

FIG. 4 illustrates a partial circuit construction of an address program circuit 150 and a redundancy predecoder 160 . The first main wordline decoder 120 and the first predecoder 110 are the same as shown in FIG. 2 and will not be explained in further detail.

Referring to FIG. 4, an address program circuit 150 includes four fuse circuits 310 - 313 for storing an address of a defective cell in memory cell arrays 101 , 102 , and 103 . Different defective addresses may be stored in the fuse circuits 310 - 313 , respectively.

FIG. 5 illustrates a detailed circuit construction of the fuse circuit 310 shown in FIG. 4 . Since the other fuse circuits 311 - 313 shown in FIG. 4 have the same operation and construction as the fuse circuit 310 , only the fuse circuit 310 is illustrated. Unlike a conventional fuse circuit which includes 12 fuses so as to store only 6 bit address XA 3 -XA 8 , the fuse circuit 310 of FIG. 5 includes 16 fuses F 11 -F 81 and F 12 -F 82 , NMOS transistors MN 11 -MN 81 , MN 12 -MN 82 , and MN 13 -MN 83 each corresponding to each of the fuses F 11 -F 81 and F 12 -F 82 , a master fuse circuit 420 , an inverter 430 , and a NAND gate 440 , so as to store an 8 bit address XA 1 -XA 8 . The detailed operations of the fuse circuit 310 are well known to a person skilled in the art, and will not be explained in further detail.

Returning to FIG. 4, the fuse circuits 310 - 313 each compare an external row address XA 1 -XA 8 with a defective address stored therein. If they match up to each other, then a corresponding one of the fuse circuits 310 - 313 outputs a signal RED 0 _E . . . RED 3 _E having a high level (i.e., logic ‘1’), respectively.

A signal output from a NOR gate 321 becomes high when at least one of the signals RED 0 _E-RED 3 _E is high. Therefore, a redundancy enable signal RED_E output from an inverter 322 becomes low. As a result, first and second main row decoders 120 and 130 , as well as first and second predecoders 110 and 140 are disabled, and the redundancy predecoder 160 is enabled.

Buffers 340 - 343 in address program circuit 150 convert levels of the signals RED 0 _E-RED 3 _E into levels suitable for driving redundancy wordlines RMWL 0 -RMWL 3 and output the signals RED 0 _E-RED 3 _E having the suitable levels, respectively. According to this construction, a redundancy main wordline corresponding to a fuse storing an address matching up to external row address XA 1 -XA 8 is activated.

Redundancy predecoder 160 includes inverters 323 , 324 , and 327 , AND gates 325 and 328 , and buffers 326 and 329 . The inverters 323 and 324 receive and invert a redundancy enable signal RED_E and an external address X 0 . The AND gate 325 receives output signals of the inverters 323 and 324 to perform an AND operation. The inverter 327 receives and inverts the redundancy enable signal RED_E, and the AND gate 328 receives an output signal of the inverter 327 and the external address X 0 to perform an AND operation. The buffers 326 and 329 convert levels of signals output from corresponding AND gates 325 and 328 into levels suitable for driving redundancy predecoding lines RSWPD 0 -RSWPD 1 , and output the signals having the suitable level, respectively. Thus, when the external address X 0 is ‘0’, the redundancy predecoding line RSWPD 0 is activated. When the external address X 0 is ‘1’, the redundancy predecoding line RSWPD 1 is activated.

For example, assume that a defect exists in a memory cell coupled to a sub-wordline SWL 0 whose row address is ‘000000000’ and an address of the defective cell is stored in a second fuse circuit 311 . When an externally supplied row address XA 1 -XA 8 is ‘00000000’, a signal RED 1 _E output from the second fuse circuit 311 becomes high, and signals RED 0 _E, RED 2 _E, and RED 3 _E output from the other fuse circuits 310 , 312 , and 313 become low. Therefore, the redundancy enable signal RED_E becomes low. As a result, the first and second main row decoders 120 and 130 , as well as the first and second predecoders 110 and 140 , are disabled. On the other hand, a first redundancy main wordline RMWL 1 is activated by the signal RED 1 _E output from the second fuse circuit 311 . Since the external row address X 0 is ‘0’, the redundancy predecoding line RSWPD 0 is activated. Thus, a redundancy sub-row decoder k is activated to replace the sub-wordline SWL 0 by a redundancy sub-wordline RSWL 2 .

In the exemplary case of the defective cell coupled to the sub-wordline SWL 0 whose row address is ‘000000000’, when a row address ‘000000001’ is externally supplied (i.e., the sub-wordline SWL 1 is addressed), operations of the memory device are described below. Since the upper 8 bits ‘00000000’ of an external input address matches up to the 8 bit address ‘00000000’ stored in the second fuse circuit 311 , the signal RED I_E becomes high, and signals RED 0 _E, RED 2 _E, and RED 3 _E output from the other fuse circuits 310 , 312 , and 313 become low. As a result, a first redundancy main wordline RMWL 1 is activated. Since the lowest bit X 0 of the external row address is ‘1’, the predecoding line RSWPD 1 is activated. Thus, the redundancy sub-row decoder “1” is activated to replace the sub-wordline SWL 1 by a redundancy sub-wordline RSWL 3 .

In conclusion, when the upper 8 bits of an externally supplied address match up to an address of a defective cell stored in fuse circuits 310 - 313 , a sub-wordline corresponding to the row address is replaced by a redundancy sub-wordline. That is, when there is a sub-wordline to which a defective cell is coupled among 8 sub-wordlines corresponding to one main wordline, 8 sub-wordlines are all replaced by sub redundancy wordlines in the prior art. In contrast, a first sub-wordline to which a defective cell is coupled, and another sub-wordline whose lowest bit is different from that of the first sub-wordline, are replaced by two redundancy sub-wordlines in the embodiment disclosed above. Particularly, when among sub-wordlines coupled to a main wordline, a sub-wordline to which a normal main memory cell is addressed, a main wordline selector is enabled to improve a redundancy flexibility and to reduce a circuit area.

While the invention has been described with respect to certain preferred embodiments and examples, it is not intended to limit the scope of the claims thereby, but solely by the claims appended hereto.