Standby current erasion circuit of DRAM

1. Field of the Invention

The present invention relates to a circuit for erasing the leakage current of DRAM, more particularly to a circuit for erasing the short DC standby current between the bit lines and the word lines of DRAM.

2. Background of the Invention

In the manufacturing process of DRAM, a short circuit between the bit line and the word line sometimes occurs and causes a leakage current and affect the product yield.

One of the solutions for the above-mentioned problem is disclosed in U.S. Pat. No. 5,499,211, entitled “BIT-LINE PRE-CHARGE CURRENT LIMITER FOR CMOS DYNAMIC MEMORIES.” As shown in FIG. 1 , a conventional circuit 10 comprises a word line 12 , a pair of complementary bit lines 13 , a pre-charge equalization circuit 14 and a current-limiting means 11 . In prior art, in order to prevent an excess leakage current caused by the short circuit between the bit line (BL) and the word line (WL), a current-limiting means 11 , such as a depletion NMOS, is added between a source of pre-charge voltage (VBLEQ) 15 and the pair of complementary bit lines 13 so as to limit the maximum leakage current when the short circuit between the bit line and the word line occurs.

Generally, the word line voltage (V WL ) is 0 volt in the standby mode, such as the word line driving circuit 20 shown in FIG. 2( a ). However, the bit line voltage is larger than 0 volt, so a leakage current path will be formed in the standby mode. The leakage current will flow from BLEQ, BL, and WL to the ground. FIG. 2( b ) shows a timing diagram of FIG. 1 and FIG. 2( a ). In other words, the conventional method cannot effectively erase the leakage current when the short circuit occurs between the bit lines and the word lines. For the current application in the product for low power DRAM, the leakage current is still too large to satisfy the market requirement.

Regarding the problems in the prior art, the present invention provides an innovative standby current erasion circuit for the DRAM to overcome the above-mentioned disadvantages.

The object of the present invention is to provide a standby current erasion circuit for DRAM, which is suitable for the application requirement in a low power DRAM.

To this end, the present invention discloses a standby current erasion circuit for DRAM, which improves prior art word line driving circuit to have the word line voltage output in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

The standby current erasion circuit for DRAM according to the present invention comprises a block detection circuit and a word line driving circuit. The block detection circuit is used to enable a short circuit control signal when a short circuit between the bit lines and word lines of the DRAM is detected. The word line driving circuit is connected to the block detection circuit, and sets a voltage level of the bit line occurring a short circuit as a voltage level of the corresponding word line occurring a short circuit in a standby mode if the short circuit control signal is enabled.

The present invention will be described according to the appended drawings in which:

FIG. 1 shows a prior art standby current erasion circuit for DRAM;

FIG. 2( a ) shows a prior art word line driving circuit;

FIG. 2( b ) shows a timing diagram of FIG. 1 and FIG. 2( a );

FIG. 3( a ) shows an embodiment of the word line driving circuit according to the present invention;

FIG. 3( b ) shows a timing diagram of the invention if there is no short circuit between the word lines and the bit lines;

FIG. 3( c ) shows a timing diagram of the invention if a short circuit occurs between the word lines and the bit lines;

FIG. 4( a ) shows an embodiment of the word line driving circuit of FIG. 3( a ) according to the present invention;

FIG. 4( b ) shows a timing diagram of the word line driving circuit of FIG. 4( a );

FIG. 5( a ) shows an embodiment of the inverters of FIG. 4( a );

FIG. 5( b ) shows a timing diagram of the structure in FIG. 5( a );

FIG. 6( a ) shows an embodiment of the first logic circuit of FIG. 4( a );

FIG. 6( b ) shows a timing diagram of the structure in FIG. 6( a ); and

FIG. 7 shows an embodiment of the second logic circuit of FIG. 4( a ).

The standby current erasion circuit for DRAM according to the present invention can adopt a structure similar to FIG. 1 . The detailed description is illustrated as follows.

FIG. 3( a ) shows an embodiment of the word line driving circuit according to the present invention. This embodiment inserts a block detection circuit 31 in a front stage of prior art word line driving circuit (e.g., an inverter), and pulls up the word line driving voltage V WL from 0 V to the bit line voltage V BL . FIG. 3( b ) shows a timing diagram of the invention if there is no short circuit between the word lines and the bit lines, and FIG. 3( c ) shows a timing diagram of the invention if a short circuit occurs between the word lines and the bit lines. When there is no short circuit between the bit lines and word lines, a selection line S is set to zero; or one, otherwise. The block detection circuit 31 functions like a decoder, and when the selection line S is zero, the output signal A is equal to the input signal IN. In other words, in this situation, the signal feeds through the block detection circuit 31 . However, when the selection line S is one, the block detection circuit 31 inverts the input signal IN to obtain the output signal A. In other words, the output signal A functions as a short circuit control signal. By the circuit of the invention, a short DC standby current due to manufacturing flaws will be erased, and the requirements of low power DRAM products will be satisfied.

In addition, since the output voltage of the word line driving circuit occurring a short circuit in a standby mode is equal to the word line voltage, the leakage current due to a short circuit between the word lines and bit lines can be erased. In other words, the present invention can omit the current-limiting means 11 used in prior art and get a better performance.

FIG. 4( a ) shows an embodiment of the word line driving circuit of FIG. 3( a ) according to the present invention. By a first logic circuit 41 , a second logic circuit 42 , an inverter 43 and a fuse 44 , the selection line S and the input signal IN can generate output signals A and WL, and the signal EQ serves as a control signal for shifting voltage level. FIG. 4( b ) shows a timing diagram of the word line driving circuit of FIG. 4( a ).

FIG. 5( a ) shows an embodiment of the inverters 43 of FIG. 4( a ). By the fuse 44 and spare circuits on columns and rows of the DRAM, the problem of short circuits between word lines and bit lines can be solved. FIG. 5( b ) shows a timing diagram of the structure in FIG. 5( a ).

FIG. 6( a ) shows an embodiment of the first logic circuit 41 of FIG. 4( a ), and FIG. 6( b ) shows a timing diagram of the structure in FIG. 6( a ).

FIG. 7 shows an embodiment of the second logic circuit 42 of FIG. 4( a ).

The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.