Method and circuit for determining frequency and time variations between electronic signals

This invention relates generally to signal processing, and more particularly to a method and system for determining frequency and time variations between electronic signals.

In signal processing applications, it is often necessary to determine certain parameters of a signal in order to accurately track the signal. These applications can include, but are not limited to, frequency control, symbol synchronization, bit synchronization and coherent carrier tracking. Phase-locked loops (PLLs) are well known in the art and they can function as a signal tracking tool. A PLL is an electronic circuit that can be configured to control an oscillator so that the oscillator produces a signal having a constant phase angle relative to a reference signal. A PLL can be configured to control a voltage controlled oscillator (VCO). In this regard, a variable tuning voltage can be applied to an input of the VCO to produce an output that varies over a wide frequency range. Notably, by applying a specified tuning voltage, the VCO can produce one or more signals having a particular frequency.

The resolution of a circuit can be used to define the variation between an input signal and a reference signal. In general, the smaller the variation between the input signal and the reference signal, the greater the accuracy or resolution. In contrast, the greater the variation between the input signal and a reference, the lesser the accuracy or resolution. Notably, less resolution will require less timing samples or counts to achieve synchronization. For example, a system that requires a 5% resolution or accuracy may require 128 counts to achieve such precision. However, a system that requires 0.03% accuracy may require 16,384 counts. In this context, a 5% accuracy provides less precision than a 0.03% accuracy or resolution. Importantly, the greater the required resolution, the greater the number of required counts and the greater the processing time. This greater processing time can adversely affect system speed and performance.

In certain applications, it can be critical to maintain a minimal resolution in order to maintain functionality of a circuit or particular integrated circuit (IC). For example, it can be necessary to switch a PLL from a first reference clock signal to a second reference clock signal. Under normal operation, the PLL will attempt to converge to the frequency of the first reference signal and once the desired accuracy is met, switching to the second reference signal can occur. However, if the frequency of the PLL and the second reference clock signal are not within a certain minimal resolution at the switchover point, signal divergence can result in a loss of synchronization, which can ultimately cause a loss of system functionality. To prevent divergence, greater resolution can be required.

Given these inflexibilities and other inherent drawbacks, there is a need for providing a method and circuit for determining variations between electronic signals in order to overcome the limitations described.

The invention provides a method for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The method can include the step of generating a plurality of time shifted input clock signals that are time shifted relative to the input clock signal. The plurality of time shifted signals can be sampled at periodic intervals relative to the reference clock signal. Sampled values for the time shifted signals can be compared with values for the reference clock to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition wherein the frequency of the input clock signal can be less than the frequency of the reference clock signal, or the frequency of the input clock signal can be greater than the frequency of the reference clock signal, and the frequency of the input clock signal can be equal to the frequency of the reference clock signal.

The generating step can further include the step of shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals includes the input clock signal and the time shifted versions of the input clock signal. The time shifted versions of the input clock signal can all have the same frequency.

The sampling step can further include the step of sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for at least one of the plurality of time shifted signals. A value for one or more of the time shifted signals can subsequently be stored in a flip-flop or register. The value for the one or more of the plurality of time shifted signals can be stored on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. Furthermore, one or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal to yield a second sampled value for one or more of the plurality of time shifted signals. Finally, the first and second sampled value for one or more of the plurality of time shifted signals can be compared to determine how the frequency of the input clock signal is varied from the frequency of the reference clock signal.

In another aspect of the invention, an electronic circuit can be provided for determining variation between a frequency of an input clock signal and a frequency of a reference clock signal. The electronic circuit can include means for generating a plurality of time shifted input clock signals. The time shifted signals can be configured so that they can be shifted relative to the input clock signal. Means can be provided for sampling the plurality of time shifted signals at periodic intervals relative to the reference clock signal. Comparing means can be configured for comparing values for the sampled time shifted signals with values for the reference clock signal to determine the variation between the frequency of the input clock signal and a frequency of the reference clock signal. The variation can include a condition where the frequency of the input clock signal can be less than the frequency of the reference clock signal, the frequency of the input clock signal can be greater than the frequency of the reference clock signal, or the frequency of the input clock signal can be equal to the frequency of the reference clock signal.

The generating means of the electronic circuit can further include means for shifting each of the plurality of time shifted signals by an amount equivalent to the period of the input clock signal divided by the number of input clock signals. The number of input clock signals can include the input clock signal and the shifted versions of the input clock signals. The time shifted signals can be configured so that they can all have the same frequency.

The sampling means can further include means for sampling at least one of the plurality of time shifted signals on a first rising edge of the reference clock signal to yield a first sampled value for one or more of the plurality of time shifted signals. A flip-flop or register can be configured to store a value for one or more of the plurality of time shifted signals. The storing means can store the first sampled value of one or more of the plurality of time shifted signals on a first falling edge of the reference clock signal, which occurs subsequent to the first rising edge of the reference clock signal. One or more of the plurality of time shifted signals can be sampled on a second rising edge of the reference clock signal occurring subsequent to the first rising edge of the reference clock signal, to yield a second sampled value for one or more of the plurality of time shifted signals. The comparing means can be configured to compare the first and the second sampled values for one or more of the plurality of time shifted signals, in order to determine the variation in frequency between the input clock signal and the reference clock signal.

In another aspect of the invention, a high resolution frequency detection circuit can be provided for determining variance between an input clock signal and a reference signal. The high resolution frequency detection circuit can include a first bank of flip-flops, a second bank of flip-flops, a third bank of flip-flops, and a fourth bank of flip-flops. Clock inputs of flip-flops in the first bank of flip-flops can be coupled to the reference clock signal and each data input of the flip-flops in the first bank of flip-flops can be singularly coupled to one of a plurality of time shifted input clock signals. Each data input of the flip-flops in the second bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the first bank of flip-flops. Clock inputs of the flip-flops in the second bank of flip-flops can be coupled to a complement of the reference clock signal.

A first input of each XOR gate in a first bank of XOR gates can be singularly coupled to an output of one of the flip-flops in the first bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops in the second bank of flip-flops. The XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal. A clock input of each of the flip-flops in the second bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. The high resolution frequency detection circuit can further include a log 2 (n) bit adder wherein each input of the log 2 M(n+1) bit adder can be singularly coupled to an output of one of the XOR gates in the first bank of XOR gates.

Another aspect of the invention can include a high resolution frequency detection circuit for determining variance between an input clock signal and a reference signal. In this regard, a clock input of each flip-flop in a first bank of flip-flops can be coupled to the reference clock signal and each flip-flop input can be singularly coupled to one of a plurality of time shifted input clock signals. Each input of flip-flops in a second bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the first bank of flip-flops. A clock input of each flip-flop in the second bank of flip-flops can be coupled to a complement of the reference clock signal. Clock inputs of each of flip-flops in a third bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. Each input of the flip-flops in the third bank of flip-flops can be singularly coupled to one of a plurality of time shifted input clock signals. Each input for flip-flops in fourth bank of flip-flops can be singularly coupled to an output of each of the flip-flops in the third bank of flip-flops. Clock inputs of each of the flip-flops in the fourth bank of flip-flops can be coupled to the reference clock signal

A first input of each of XOR gate in a first bank of XOR gates can be singularly coupled to an output of one of the flip-flops of the first bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops in the fourth bank of flip-flops. The XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal. A first input of each of the XOR gate in a second bank of XOR gates can be singularly coupled to an output of one of the flip-flops of the second bank of flip-flops, while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops of the third bank of flip-flops. Each of the XOR gates can be configured to compare a previously sampled value for an input clock signal with a successively sampled value for the input clock signal.

The high resolution frequency detection circuit can be configured so that a clock input of each of the flip-flops in the second bank of flip-flops can be coupled to a signal that is the complement of the reference clock signal. A clock input of each of the flip-flops in the fourth bank of flip-flops can be coupled to the reference clock signal. A first log 2 (n+1) bit adder can be configured so that each input of the first n-bit adder can be singularly coupled to an output of one of the XOR gates of The first bank of XOR gates. The high resolution frequency detection circuit can further include a second log 2 (n+1) bit adder configured so that each input of the first n-bit adder can be singularly coupled to an output of one of the XOR gates of the second bank of XOR gates.

In yet a further aspect of the invention, an enhanced resolution frequency detection circuit can be provided for determining the variance between an input clock signal and a reference signal. In this regard, the enhanced resolution frequency detection circuit can include a delay-locked loop having an input reference clock signal coupled thereto. A plurality of frequency detection circuits can be configured so that each clock input of the frequency detection circuits can be coupled to a separate output of the delay-locked loop. Each input of the frequency detection circuit can be coupled to a set of time shifted input clock signal. A plurality of XOR gates can be configured so that each of the plurality of XOR gates can be coupled to an output of each of the plurality of frequency detection circuits so as to provide an XOR operation of all bits in a same bit position at the output of each of the frequency detection circuit.

The invention also provides a time detection circuit for determining the variation between an input clock signal and a reference signal. The time detection circuit can include a first bank of n+1 flip-flops and a plurality of time shifted input clocksignals. Each of the time shifted input clock signals can be singularly coupled to a clock input of a flip-flop in the first bank of n+1 flip-flops. The reference clock signal can be coupled to an input of each of the n flip-flops in the first bank of flip-flops.

FIG. 1 is an exemplary frequency detection circuit in accordance with the invention.

FIG. 2 is an exemplary timing diagram of a reference clock signal and an input clock signal in accordance with the inventive arrangements of FIG. 1 .

FIG. 3 depicts an exemplary timing diagram of a reference clock signal and a plurality of time shifted input clock signals in accordance with the inventive arrangements.

FIG. 4 depicts an exemplary timing diagram of a reference clock signal and a plurality of time shifted input clock signals in accordance with the inventive arrangements.

FIG. 5 illustrates an exemplary circuit for determining a change in an input clock signal in accordance with the inventive arrangements.

FIGS. 6 a and 6 b illustrates an enhanced circuit for overcoming range limitations of circuits in accordance with the inventive arrangements.

FIGS. 7 a and 7 b illustrate various aspects of an exemplary circuit for enhancing the resolution of a frequency detection circuit in accordance with the inventive arrangements.

FIG. 8 depicts an exemplary time detector circuit in accordance with the inventive arrangements.

Referring to FIG. 1, there is shown an exemplary circuit frequency detection circuit 100 in accordance with the invention. Regarding circuit 100 , there is shown a first bank of a flip-flops (FFs) 110 and a second bank of flip-flops 120 . Each bank of FFs 110 and 120 can contain “n+1” FFs. A reference clock signal (REFCLK) 105 can be coupled to a clock input of each of the “n+1” flip-flops located in the first bank of flip-flops 110 . Notably, REFCLK signal 105 can be coupled to flip-flops 1 - 0 , 1 - 1 , 1 - 2 , 1 - 3 . . . 1 -n. The complement or inverse of REFCLK signal 105 , namely input signal 115 , can be coupled to a clock input of each of the “n+1” flip-flops located in the second bank of flip-flops 120 . Notably, input signal 115 can be coupled to flip-flops 2 - 0 , 2 - 1 , 2 - 2 , 2 - 3 , . . . , 2 -n. The flip-flops can preferably be D-type flip-flops although the invention is not limited in this regard.

Advantageously, a plurality of input clock signals can be used to achieve greater accuracy in determining the variation between an input clock signal and a reference clock signal. Each of the plurality of the input clock signals can have the same frequency and can be a time shifted version of the input clock signal. Each input clock signal that is to be compared with the reference clock signal 105 can be singularly coupled to a flip-flop as shown. For example, input or VCO clock signal CLK 0 can be coupled to the data input of the first flip-flop in the first bank of flip-flops 110 , namely flip-flop 1 - 0 . Similarly, clock signal CLK 1 can be coupled to the data input of the second flip-flop in the first bank of flip-flops 110 , namely flip-flop 1 - 1 . Finally, clock signal CLKn can be coupled to the data input of the last flip-flop in the first bank of flip-flops 110 , namely FF 1 -n. It should readily be understood that “n” is a placeholder which can represent a positive whole number.

The output of each flip-flop in the first bank of flip-flops 110 can be coupled to the data input of a corresponding flip-flop in the second bank of flip-flops 120 as shown. For example, the output of flip-flop 1 - 0 can be coupled to the data input of flip-flop 2 - 0 and the output of flip-flop 1 - 1 can be coupled to an input of flip-flop 2 - 1 .

A plurality of input clock signals can be used to determine the variation between the frequency of the input clock signal and the reference clock signal. These input clock signals can be VCO clock signals. For illustrative purposes a set of 20 clock signals can be used to determine the variation in frequency between an input clock signal and a reference clock signal. Notably, the invention is not limited in this regard and the set of clock signals can include other quantities of clock signals without departing from the spirit and scope of the invention. Each of the clock signals in the set of 20 clock signals can have the same frequency but is a shifted version of the input clock signal. In this regard, each successive signal in the set of 20 clock signals can be shifted by T ( 20 ) ,

where T is the period of the input clock signal, and T = 1 f ,

where f is the frequency of input clock signal CLK 0 can be configured as the input clock signal and each successive clock signal CLK 1 , CLK 2 , CLK 3 , . . . , CLK 19 can successively vary by T 20 .

In operation, on the rising edge of REFCLK, the first bank of flip-flops 110 of the circuit 100 can be used to sample the value of each of the clock signals comprising the set of 20 clock signals, namely CLK 0 , CLK 1 , CLK 2 , CLK 3 , . . . , CLK 19 . In this regard, n=19 in FIG. 1 . The sampled values can be stored in the flip-flops 1 - 0 , 1 - 1 , 1 - 2 , 1 - 3 , . . . , 1 - 19 , respectively. On the falling edge of the REFCLK signal 105 , the stored values can be shifted into the corresponding flip-flops in the second bank of flip-flops 120 . On the next rising edge of REFCLK signal 105 , a new value can be sampled for the set of 20 clock signals CLK 0 , CLK 1 , CLK 2 , CLK 3 , . . . , CLK 19 and the sampled values accordingly stored in the flip-flops 1 - 0 , 1 - 1 , 1 - 2 , 1 - 3 , . . . , 1 - 19 , respectively. At this instant, a currently sampled value stored in each of the flip-flops of the first bank of flip-flops 110 can be compared with a previously sampled value stored in corresponding ones of each of the flip-flops comprising the second bank of flip-flops 120 .

If the frequency of the CLK 0 signal is the same as the frequency of the REFCLK signal 105 , then the output from the first bank of flip-flops 110 can be the same as the output from the second bank of flip-flop 120 . Notably, D 0 L=D 0 E, D 1 L=D 1 E, D 2 L=D 2 E, D 3 L=D 4 E, . . . , D 19 L=D 19 E. Importantly, if there is a difference or variation in the frequency between the input clock signal and the reference clock signal, then there will be a variation between at least some of the values stored in each of the flip-flops in the first bank of flip-flops 110 and corresponding flip-flops in the second bank of flip-flops 120 . In that case, the DxL value can differ from the DxE value, where x is the bit number or the clock signal, and x= 0 , 1 , 2 , 3 , . . . , 19 .

The variation in the frequency can be expressed as follows. For exemplary purposes, the clock signal CLK 0 can have a frequency denoted by f 0 and REFCLK can have a frequency denoted by f ref . Consequently, the clock signal CLK 0 can have a period denoted by T 0 and REFCLK can have a period denoted by T R . FIG. 2 depicts an exemplary timing diagram of REFCLK and CLK 0 signals. Although FIG. 2 depicts the REFCLK and CLK 0 signals starting at the same instant in time, the invention is not limited in this regard. At the rising edge of REFCLK signal 205 which occurs at time t 0 , the CLK 0 signal 207 can be sampled. A second sample of the CLK 0 207 can occur at a time t 1 . However, t 1 =t 0 +T R . A third sample of the CLK 0 signal 207 can be taken on rising edge of REFCLK signal 205 occurring at a time t 2 . However, t 2 =t 0 +2T R =(t 0 +T R )+T R and (t 0 +T R )=t 1 . Therefore, t 2 =t 1 +T R . If T<T R , then at t 1 , CLK 0 leads REFCLK by (T R T−). Similarly, if T 0 >T R , then at t 1 , CLK 0 lags REFCLK by (T−T R ). The REFCLK signal can be represented mathematically by: REFCLK = F ref  ( t ) = ∑ m = - ∞ m = + ∞  [ u  ( t - mT R ) - u  ( t - ( m + 1 )  T R ) ] ,

where u(t) is the unit step function. The unit step function is well known in the art. The CLK 0 signal can be represented mathematically by: CLK0 = F 0  ( t ) = ∑ n = - ∞ n = + ∞  [ u  ( t - nT ) - u  ( t - ( n + 1 )  T ) ] .

The CLK 1 signal can be shifted by T s = T 20

from CLK 0 and can therefore be represented mathematically by: CLK1 = F 1  ( t ) = F 0  ( t - T s ) ⇒ CLK1 = ∑ n = - ∞ n = + ∞  [ u  ( t - T s - nT ) - u  ( t - T s - ( n + 1 )  T ) ]

FIG. 3 depicts an exemplary timing diagram in accordance with the inventive arrangements. Referring to FIG. 3, there is shown a REFCLK signal 305 , an input clock CLK 0 signal 307 and nine clock signals CLK 1 , CLK 2 , CLK 3 , . . . , CLK 9 . The clock signals CLK 1 , CLK 2 , CLK 3 , . . . , CLK 9 are shifted versions of the input clock CLK 0 signal 307 . It should be recognized that the remaining signals, namely CLK 10 through CLK 19 , do not need to be used since the information contained therein are redundant when compared to CLK 0 through CLK 9 respectively. However, the invention is not limited in this regard. Notably, the complete set of input clock signals CLK 0 through CLK 19 are shifted such that the total shift is equal to one period of CLK 0 . Consequently, the partial set of clock signals CLK 0 through CLK 9 have a total shift of one-half of the period of CLK 0 . For     CLK0 , at     time     instant     t A , CLK0 = F 0  ( t A ) = 0 ⇒ F 0  ( t A ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t A - nT ) - u  ( t A - ( n + 1 )  T ) ] . For     CLK1 , at     time     t A , CLK1 = F 1  ( t A ) = 0 = F 0  ( t A - T s ) ⇒ F 1  ( t A ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t A - T s - nT ) - u  ( t A - T s - ( n + 1 )  T ) ] . For     CLK2 , at     time     t A , CLK2 = F 2  ( t A ) = 0 = F 0  ( t A - 2  T s ) ⇒ F 2  ( t A ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 2  T s - nT ) - u  ( t A - 2  T s - ( n + 1 )  T ) ] . For     CLK3 , at     time     time     t A , CLK3 = F 3  ( t A ) = 0 = F 0  ( t A - 3  T s ) ⇒ F 3  ( t A ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 3  T s - nT ) - u  ( t A - 3  T s - ( n + 1 )  T ) ] . For     CLK4 , at     time     time     t A , CLK4 = F 4  ( t A ) = 1 = F 0  ( t A - 4  T s ) ⇒ F 4  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 4  T s - nT ) - u  ( t A - 4  T s - ( n + 1 )  T ) ] . For     CLK5 , at     time     time     t A , CLK5 = F 5  ( t A ) = 1 = F 0  ( t A - 5  T s ) ⇒ F 5  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 5  T s - nT ) - u  ( t A - 5  T s - ( n + 1 )  T ) ] . For     CLK6 , at     time     time     t A , CLK6 = F 6  ( t A ) = 1 = F 0  ( t A - 6  T s ) ⇒ F 6  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 6  T s - nT ) - u  ( t A - 6  T s - ( n + 1 )  T ) ] . For     CLK7 , at     time     t A , CLK7 = F 7  ( t A ) = 1 = F 0  ( t A - 7  T s ) ⇒ F 7  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 7  T s - nT ) - u  ( t A - 7  T s - ( n + 1 )  T ) ] . For     C1K8 , at     time     t A , CLK8 = F 8  ( t A ) = 1 = F 0  ( t A - 8  T s ) ⇒ F 8  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 8  T s - nT ) - u  ( t A - 8  T s - ( n + 1 )  T ) ] . For     C1K9 , at     time     t A , CLK9 = F 9  ( t A ) = 1 = F 0  ( t A - 9  T s ) ⇒ F 9  ( t A ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t A - 9  T s - nT ) - u  ( t A - 9  T s - ( n + 1 )  T ) ] .

At a later time t B , wherein t B >t A , the CLK 0 through CLK 9 can be sampled. The resulting sampled information can be represented as follows. For     CLK0 , at     time     instant     t B , CLK0 = F 0  ( t B ) = 0 ⇒ F 0  ( t B ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t B - nT ) - u  ( t B - ( n + 1 )  T ) ] . For     CLK1 , at     time     instant     t B , CLK1 = F 1  ( t B ) = 0 = F 0  ( t B - T s ) ⇒ F 1  ( t B ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t B - T s - nT ) - u  ( t B - T s - ( n + 1 )  T ) ] . For     CLK2 , at     time     instant     t B , CLK2 = F 2  ( t B ) = 0 = F 0  ( t B - 2  T s ) ⇒ F 2  ( t B ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 2  T s - nT ) - u  ( t B - 2  T s - ( n + 1 )  T ) ] . For     CLK3 , at     time     instant     t B , CLK3 = F 3  ( t B ) = 0 = F 0  ( t B - 3  T s ) ⇒ F 3  ( t B ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 3  T s - nT ) - u  ( t B - 3  T s - ( n + 1 )  T ) ] . For     CLK4 , at     time     instant     t B , CLK4 = F 4  ( t B ) = 0 = F 0  ( t B - 4  T s ) ⇒ F 4  ( t B ) = 0 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 4  T s - nT ) - u  ( t B - 4  T s - ( n + 1 )  T ) ] . For     CLK5 , at     time     instant     t B , CLK5 = F 5  ( t B ) = 1 = F 0  ( t B - 5  T s ) ⇒ F 5  ( t B ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 5  T s - nT ) - u  ( t B - 5  T s - ( n + 1 )  T ) ] . For     CLK6 , at     time     instant     t B , CLK6 = F 6  ( t B ) = 1 = F 0  ( t B - 6  T s ) ⇒ F 6  ( t B ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 6  T s - nT ) - u  ( t B - 6  T s - ( n + 1 )  T ) ] . For     CLK7 , at     time     instant     t B , CLK7 = F 7  ( t B ) = 1 = F 0  ( t B - 7  T s ) ⇒ F 7  ( t B ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 7  T s - nT ) - u  ( t B - 7  T s - ( n + 1 )  T ) ] . For     C1K8 , at     time     instant     t B , CLK8 = F 8  ( t B ) = 1 = F 0  ( t B - 8  T s ) ⇒ F 8  ( t B ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 8  T s - nT ) - u  ( t B - 8  T s - ( n + 1 )  T ) ] . For     C1K9 , at     time     instant     t B , CLK9 = F 9  ( t B ) = 1 = F 0  ( t B - 9  T s ) ⇒ F 9  ( t B ) = 1 = ∑ n = - ∞ n = + ∞  [ u  ( t B - 9  T s - nT ) - u  ( t B - 9  T s - ( n + 1 )  T ) ] .

Notably, in comparing the sampled values for time instants t A and t B , at t A , CLK 4 =F 4 (t A )= 1 , while at t B , CLK 4 =F 4 (t B )= 0 . However, since t B =t A +T R , then F 0 (t B )=F 0 (t A +T R ). ⇒ F 0  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + T R - nT ) - u  ( t A + T R - ( n + 1 )  T ) ] . Similarly , F 1  ( t B ) = F 0  ( t A + T R - T s ) , ⇒ F 1  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + T R - T s - nT ) - u  ( t A + T R - T s - ( n + 1 )  T ) ] .

Similar expressions can be generated for F 2 (t B ), F 3 (t B ), F 4 (t B ), F 5 (t B ), F 6 (t B ), F 7 (t B ), F 8 (t B ), and F 9 (t B ).

If the difference between T R and T is Δt, then T R =T+Δt. Hence, F 0  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + T + Δ     t - nT ) - u  ( t A + T + Δ     t - ( n + 1 )  T ) ] ⇒ F 0  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + Δ     t - ( n - 1 )  T ) - u  ( t A + Δ     t - nT ) ] .

Similarly, F 1  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + Δ     t - T s - ( n - 1 )  T ) - u  ( t A + Δ     t - T s - nT ) ] .

Similar expressions can be generated for F 2 (t B ), F 3 (t B ), F 4 (t B ), F 5 (t B ), F 6 (t B ), F 7 (t B ), F 8 (t B ), and F 9 (t B ).

Notwithstanding, F 0 (t), F 1 (t), F 2 (t), F 3 (t), F 4 (t), F 5 (t), F 6 (t), F 7 (t), F 8 (t), and F 9 (t) are all periodic. Consequently, F 0 (t)=F 0 (t+T)=F 0 (t−T) can generally represent the shifted versions of F 0 (t). Accordingly, since, F 0  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + Δ     t - ( n - 1 )  T ) - u  ( t A + Δ     t - nT ) ] ⇒ F 0  ( t B ) = ∑ n = - ∞ n = + ∞  [ u  ( t A + Δ     t - nT ) - u  ( t A + Δ     t - ( n + 1 )  T ) ] ⇒ F 0  ( t B ) = F 0  ( t A + Δ     t )

Similarly, F 1 (t B )=F 1 (t A +Δt), F 2 (t B )=F 2 (t A +Δt) F 3 (t B )=F 3 (t A +Δt), F 4 (t B )=F 4 (t A +Δt), F 5 (t B )=F 5 (t A +Δt), F 6 (t B )=F 6 (t A +Δt), F 7 (t B )=F 7 (t A +Δt), F 8 (t B )=F 8 (t A +Δt), and F 9 (t B )=F 9 (t A +Δt). If Δt=0, then at every sampling time t A , t B , t C , t D , and t E , the logical values of the clocks will be the same. The logical value can be represented by logic “0” or logic “1”.

FIG. 4 depicts a timing diagram in accordance with the inventive arrangements. Referring to FIG. 4, sampling instants A, B and C are shown. Importantly, the values of the respective input clock signals at sampling instant B are the same as the respective input clock signals at sampling instant B′. For example, CLK 1 =0 at sampling instants B and B′ and CLK 8 =1 at sampling instants B and B′. Moreover, the values of the respective input clock signals at sampling instant C are the same as the respective input clock signals at sampling instant C′. For example, CLK 2 =0 at sampling instants C and C′ and CLK 7 =1 at sampling instants C and C′. Importantly, when Δt=0, T=T R and the input clock signals will have the same values. Whenever |Δt|=T S , then in any consecutive two sampling time instants A followed by B or B followed by C, only one of the clocks will change its values. Such a change can include a transition from a logic “0” to a logic “1” or from a logic “1” to a logic “0.” Whenever |Δt|=2T S , then in any consecutive two sampling time instants A followed by B or B followed by C, two (2) of the clocks will change their values. Similarly, whenever |Δt|=3T S , then in any consecutive two sampling time instants A followed by B or B followed by C, three (3) of the clocks will change their values.

In general, if |Δt|=aT S , where “a” is a constant, then in any consecutive two sampling time instants, “a” clocks will change their values. However, in a case where “a” is fractional, for example, a=0.8, then 0.8 clocks will change their values. In such a case, in order to provide information pertaining to the number of changes in the input clock signals that will occur over a specified time interval, it can be advantageous to convert “a” to an integer value by using a multiplication factor. For example, in the case where “a” is 0.8, a multiplication factor of 10 converts “a” to 8. Hence, 8 clock signals will change their values over 10 consecutive sampling time instants.

When Δt is a fraction of T S , “a” will generally be less than 1 and it can be preferable to consider a plurality of consecutive sampling time instants. Hence, if 10 clocks change over 10 consecutive sampling instants and each clock change occur at a different sampling instant, then |Δt|=T S . Similarly, for five changes occurring in 10 consecutive sampling instants, |Δt|=0.5T S , and for 15 changes occurring in 10 consecutive sampling instants, |Δt|=1.5T S .

FIG. 5 illustrates an exemplary circuit 500 in accordance with the inventive arrangements for determining a change in an input clock signal between two consecutive sampling times. Referring now to FIG. 5, a change in the value of an input clock signal from one sampling time instant to the adjacent sampling time can be achieved by executing an exclusive OR (XOR) operation on the output of the flip-flop from the first bank of flip-flops 510 , with the output of the flip-flops from the second bank of flip-flops 520 for each input clock signal. In operation, the XOR gate can generate a logic “1” whenever there is a change in the value of an input clock signal from one sampling time instant to an adjacent sampling time. For example, for input clock signal CLK 1 , the output of flip-flop 1 - 1 (D 1 E) and output of flip-flop 2 - 1 (D 1 L) can be coupled to an XOR gate XOR 1 in the bank of XOR gates 515 . Consequently, in a case where 10 consecutive sampling intervals are utilized, the value of |Δt| can be determined by counting the number of logic “1's” appearing at the outputs of the XOR gates, namely XOR 0 , XOR 1 , XOR 2 , XOR 3 , XOR 4 , XOR 5 , XOR 6 , XOR 7 , XOR 8 , and XOR 9 , for ten (10) consecutive sampling intervals.

In this regard |Δt| can be determined in terms of T S . Hence, in a case where 10 consecutive sampling intervals are being used, “a” can be determined by dividing the total number of logic “1's” in 10 consecutive sample time instant by 10. The total number of logic “1's” can be determined by using an adder 540 , coupled to the outputs of the XOR gates. Adder can be a seven bit (7-bit) parallel adder although the invention is not limited in this regard. Adder 540 can be used to determine both the number of 1's at each sampling time instant and the number of ones occurring over a specified number of consecutive sampling time instants. Notably, it should be recognized that the use of 10 consecutive sampling time instants is for illustrative purposes and the invention is not limited in this regard.

Importantly, it can be necessary to determine T S since T S is required to determine Δt. However, T R =T+Δt=T+aT S . Since there are 20 periodic shifts within one period of the CLK 0 , then T s = T 20 .

T R can be expressed as, T R = T + a     T 20 . 

⇒ T = T R  ( 20 20 + a ) .

In this regard, if 8 logic “1's” are found over a 10 consecutive sampling time instants, then a=±0.8, and T can be subsequently determined.

Referring again to FIG. 5, in operation, on the rising edge of REFCLK 305 , for example 309 (FIG. 3 ), the input clocks CLK 0 through CLK 9 can be sampled and their sampled value can be stored in respective flip-flops FF 1 - 0 through FF 1 - 9 in the first bank of flip-flops 310 . On the next falling edge of REFCLK 305 , namely 311 , the information sampled and stored in the first bank of flip-flops 310 can be shifted into the corresponding flip-flops in the second bank of flip-flops 320 . At the next rising edge of REFCLK 305 , namely 311 , the input clocks can be sampled and the sampled values stored in the first bank of flip-flops 310 . The contents of the corresponding flip-flops in the banks of flip-flops 310 and 320 can be coupled to the XOR gate inputs XOR 0 , . . . , XORn. Importantly, the XOR gate can compare the contents of the flip-flop in the first bank with the contents of the flip-flop in the second bank of flip-flops. The XOR gate can generate a logic “1” whenever the contents stored in the flip-flops differ.

Whenever the difference between the frequency of REFCLK 305 and the frequency of the input clock is significant, a portion of the XOR gates can generate a logic “1” at the rising edge of REFCLK 305 , for example 309 (FIG. 3 ). Notably, the occurrences of logic “1” will be consecutive. If 3T S >(T R −T)>3T S , then 3 consecutive XORs will generate a logic “1.” Particularly, the logic “1's” which are generated can be expressed as (i modulo 10 ), ((i+1) modulo 10 ) and ((i+2) modulo 10 ), where 0≦i≧9.

For illustrative purposes, the total number of logic “1's” at the rising edge of REFCLK 305 , for example 309 , (FIG. 3) can be denoted as “b.” Therefore, “a” is the average of “b” over 10 clock cycles of REFCLK 305 . In order to ensure proper operation of the circuit 500 , the values of both “a” and “b” can be limited to 10. In this regard, if |T R −T|>10T S the range of frequency for proper operation of circuit 500 can be denoted by, T = T R  ( 20 20 ± 10 ) .

Hence, ⅔T R ≦T≦2T R , and 0.5f REFCLK ≦f VCO ≦1.5f REFCLK where f VCO represents the frequency of the variable frequency oscillator (VCO) or other frequency source creating the input clock signals.

In accordance with the inventive arrangements, the circuit 500 can be enhanced in order to extend its resolution or range of accuracy. FIGS. 6 a and 6 b illustrates an enhanced circuit 600 that can overcome range limitations of circuit 500 . FIG. 6 b is a continuation of FIG. 6 a . Referring to FIGS. 6 a and 6 b , circuit 600 comprises a first bank of flip-flops 610 , a second bank of flip-flops 620 , a third bank of flip-flops 630 , a fourth bank of flip-flops 640 , a first bank of XOR gates 615 and a second bank of XOR gates 625 . Flip-flop banks 610 and 620 and the first bank of XOR gates 615 can be coupled similar to circuit 500 of FIG. 5 . Similarly, flip-flop banks 630 and 640 and the second bank of XOR gates 625 can be coupled similar to circuit 500 of FIG. 5 .

For illustrative purposes, the operation of circuit 600 can be described with reference to the timing diagram of FIG. 3 . Referring to FIG. 3, time instant t A can be denoted by 309 , time instant t B can be denoted as 311 , time instant t C can be denoted as 313 and time instant t D can be denoted as 315 . In operation, the first bank of flip-flops 610 can sample the input clocks or VCO on the rising edge of REFCLK signal 305 , for example 309 , while the third bank of the flip-flops 630 can sample the input clocks on the falling edge of the REFCLK signal 305 , for example 310 . On the falling edge of REFCLK signal 305 , for example 310 , the second bank of flip-flops 620 can store the value sampled by the first bank of flip-flops 610 . On the next rising edge of REFCLK signal 305 , for example 311 , the fourth bank of flip-flops 640 can store the value previously sampled by the third bank of flip-flops 630 on the previous falling edge of REFCLK signal 305 , namely 310 . The arrangement of FIG. 6 a and 6 b can provide a resolution that is twice that provided by circuit 500 . Notably, circuit 600 permits every one-half cycle of the REFCLK signal 305 to be measured as opposed to every one cycle of REFCLK signal 305 by circuit 500 . Note that a first input of each of XOR gates in the first bank of XOR gates 615 can be singularly coupled to an output of one of the flip-flops of the first bank of flip-flops 610 , while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops in the fourth bank of flip-flops 640 . Similarly note that a first input of each of the XOR gates in a second bank of XOR gates 625 can be singularly coupled to an output of one of the flip-flops of the second bank of flip-flops 620 , while a second input of each of the XOR gates can be singularly coupled to an output of one of the flip-flops of the third bank of flip-flops 630 .

Referring once again to FIGS. 6 a and 6 b , the first bank of XOR gates 615 can be configured to compare sampled values stored in corresponding flips-flops of the first bank of flip-flops 610 and the fourth bank of flip-flops 640 . The second bank of XOR gates 625 can be configured to compare sampled values stored in corresponding flips-flops of the second bank of flip-flop 620 and the third bank of flip-flops 630 . In this arrangement, the second bank of XOR gates 625 can compare values sampled by the third bank of flip-flops 630 at t 1 with values that have been stored by the second bank of flip-flops 620 at t 1 . Similarly, the first bank of XOR gates 615 can compare values sampled by the first bank of flip-flops 610 at t 2 with values that have been stored by the fourth bank of flip-flops 640 at t 2 . Notably, the value compared by the first bank of XOR gates at t 2 is the value sampled by the first bank of flip-flops 610 at t 2 and the values sampled by the third bank of flip-flops at time instant t 1 . Accordingly, the second bank of XOR gates 625 effectively compares values that have been sampled by the third bank of flip-flops 630 at time instant t 1 with values that have been sampled by the first bank of flip-flops 610 at time instant t 0 . The arrangement of circuit 600 can permit up to 20 consecutive logic “1” to be generated at the outputs of the first bank of XOR gates 615 and the second bank of the XOR gates 625 .

In a case where T 0 =T R , it should be expected that the value resulting from the comparison at time instant t 0 would be the inverse polarity of what has been sampled by the third bank of flip-flops 630 at time instant t 1 . Notably, it can be preferable to use an XNOR or negative XOR gate to generate a logic “1” whenever the values generated by the third bank of flip-flops 630 and the second bank of flip-flops 620 are the same. Similarly, it can also be preferable to use an XNOR or negative XOR gate to generate a logic “1” whenever the values generated by the fourth bank of flip-flops 640 and the first bank of flip-flops 610 are the same.

In accordance with the inventive arrangements, a delay locked loop (DLL) can be used to further enhance the resolution of the frequency detection circuits 500 and 600 . Referring to FIG. 7 a , there is shown a single frequency detector 720 and a DLL 707 . The frequency detector 720 can include a bank of flip-flops 710 configured in a manner similar to the first bank of flip-flop 110 of FIG. 1 . Notably, instead of the REFCLK signal 105 being coupled directly to the clock input of each flip-flop in the first bank of flip-flops 110 as shown in FIG. 1, a REFCLK signal 705 can be coupled to an input of DLL 707 . Each of the different phased outputs of the DLL 707 have the same frequency as REFCLK 705 and can be respectively coupled to a clock input of a flip-flop in the bank of flip-flops 710 . For example, output Φ 1 of DLL 707 can be coupled to a clock input of FF 1 - 1 in the bank of flip-flops 710 . The flip-flops can be D-type flip-flops although the invention is not limited in this regard.

Referring to FIG. 7 b , there is shown a plurality of frequency detectors 720 a , 720 b , 720 c , . . . , 720 t . These frequency detectors can be the same as those shown in FIG. 1 . Each of the clock inputs of the frequency detectors 720 a , . . . , 720 t can be coupled to an output of DLL 707 . For example, output Φ 1 of DLL 707 can be coupled to a clock input of frequency detector 720 a . Similarly, output Φ 20 of DLL 707 can be coupled to a clock input of frequency detector 720 t . The input or VCO clock signals can each be coupled to the input of each of the frequency detectors 720 a , . . . , 720 t . Each frequency detector FD 1 , FD 2 , . . . , FD 20 contains 20 outputs, namely 1 - 1 , 1 - 2 , . . . , 1 - 10 , 2 - 1 , 2 - 2 , . . . , 2 - 10 . In this regard, the outputs 2 - 1 , 2 - 2 , . . . , 2 - 10 are the complement of outputs 1 - 1 , 1 - 2 , . . . , 1 - 10 respectively. Respective outputs of each of the frequency detectors can be coupled to the inputs of XOR gates as shown. For example, the first (1st) output 1 - 1 of frequency detector 720 a and the eleventh (11th) output of frequency detector 720 t , namely 2 - 1 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 722 . The second (2nd) output 1 - 2 of frequency detector 720 a and the twelfth (12th) output of frequency detector 720 t , namely 2 - 2 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 724 . The tenth (10th) output 1 - 10 of frequency detector 720 a and the twentieth (20th) output of frequency detector 720 t , namely 2 - 10 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 726 . The eleventh (1th) output 2 - 1 of frequency detector 720 a and the first (1st) output of frequency detector 720 b , namely 1 - 1 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 728 . The twelfth (12th) output 2 - 2 of frequency detector 720 a and the second (2nd) output of frequency detector 720 b , namely 1 - 2 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 73 . The twentieth (20th) output 2 - 10 of frequency detector 720 a and the tenth (10th) output of frequency detector 720 b , namely 1 - 10 , can be respectively coupled to a second (2nd) and a first (1st) input of XOR gate 732 .

The second (2nd) output of frequency detector 720 a and the second (2nd) output of frequency detector 720 b can be coupled to the inputs of XOR gate 724 . An input of XOR gate 724 can be coupled to an input of XOR gate 730 . XOR gate 730 can further couple a second (2nd) output of the frequency detector 720 c . In this arrangement, all the second (2nd) outputs of frequency detectors 720 a , 720 b , 720 c , . . . , 720 t can be tied through XOR gates. Similar connections are made in order to couple all the respective outputs of the frequency detectors using XOR gates.

The inventive arrangement of FIGS. 7 a and 7 b can be configured to utilize two sets of clocks. There can be a set of 10 VCO/input clock signals and a set of 20 REFCLK 705 signals generated by the DLL 705 . The VCO signals can be time-shifted signals having the same frequency. The frequency of the VCO signals can be dependent on the voltage of the oscillator. The signals from the output of the DLL can differ in phases but their frequency can be the same as the REFCLK 705 frequency.

In operation, on the rising edge of every REFCLK 705 , the input clocks can be sampled. The REFCLK 705 signals can be represented as Φ 1 , Φ 2 , Φ 3 , . . . ,Φ 20 . The rising edge of REFCLK 705 can be represented by Φ 1 . At Φ 1 , the frequency detector 720 a can sample the input clocks. Similarly, at Φ 2 , Φ 3 , . . . , Φ 20 , the VCO clock is sampled. The XOR gates coupled to the outputs of the frequency detectors can be configured to detect changes or transitions in the state of any of the VCO clocks occurring between two consecutive REFCLK signals. This change can be represented as:

Φ (imod 20) ,Φ ((i+1)mod 20) where 0 ≦i ≦10.

The outputs of the frequency detectors can be labeled D i . So, D i1 and D (i+1)1 can be coupled to an XOR gate to determine when a transition occurs. Similarly, D i2 and D (i+1)2 can be couples to an XOR gate to determine when a transition occurs. The remaining signals can be coupled to XOR gates in a similar manner. Notably, within an interval (Φ (i+1) −Φ i ), the number of transitions can be measured by the outputs of the XOR gates.

If the period of REFCLK is represented by T R , and (Φ (i+1) −Φ i )=T r , then, T r = ( T R 20 )

since there were 20 REFCLK signals. In a case where there were “x” REFCLK signals, then T r = ( T R x ) .

If the period of the VCO signal is T v , and the difference between any two consecutive VCO signals is T v , then, T v = ( T V 20 ) .

During a time period T r , the number of T v 's that have occurred can be measured. The number of T v 's that have occurred during time period T r can be denoted by “a.” Preferably, this measurement can be done over all T r 's in T R . This can provide an average of “a” over the total number of T r 's in T R , which in this case is twenty (20) times. Hence, T r = ( a 1 + a 2 + a 3 + … + a 20 20 ) · T v ,

where a 1 +a 2 +a 3 +. . . +a 20 represents the number of transitions in the input or VCO clocks that occur in T r1 , T r2 , T r3 , . . . , T r20 consecutively. However, a 1 +a 2 +a 3 +. . . +a 20 can be denoted as “A.” ⇒ T r = ( A 20 ) · T v = ( A 20 ) · ( T V 20 ) ,    and 

⇒ T V = ( 400 A ) · T r = ( 400 A ) · ( T R 20 ) = ( 20 A ) · T R .

In another embodiment of the invention, a time detector (TD) circuit is provided for measuring the frequency of the input or VCO clocks. The frequency of the input or VCO clocks can be determined by measuring the number of logic “1” that occur over a specified interval. FIG. 8 depicts an exemplary time detector circuit 800 in accordance with the inventive arrangements. Referring to FIG. 8, there is shown a bank of flip-flops 810 . The bank of flip-flops 810 can include ten (10) flip-flops, namely FF 0 , FF 1 , FF 2 , FF 3 , . . . , FF 9 . A REFCLK signal 805 can be connected to an input of the each of the flip-flops in the bank of flip-flops 810 . Input or VCO clock signals CLK 0 , CLK 1 , CLK 2 , CLK 3 , . . . , CLK 9 can be connected to the clock input of flip-flops, namely FF 0 , FF 1 , FF 2 , FF 3 , . . . , FF 9 , respectively. The output of the flip-flops FF 0 , FF 1 , FF 2 , FF 3 , . . . , FF 9 are 01 , 02 , 03 , . . . , 09 , respectively. It should readily be recognized that although ten (10) flip-flops are utilized, the invention is not limited in this regard.

In operation, the time detector 800 can be configured to utilize the input or VCO clocks to sample the REFCLK signal 805 . For illustrative purposes, CLK 0 can be the reference clock signal for all the VCO clocks. At an initial time t 0 , on the rising edge of CLK 0 , all the clocks CLK 0 through CLK 9 can sample REFCLK at different times. The outputs of the flip-flops FF 0 , FF 1 , . . . , FF 9 can represent the sampled values of REFCLK. For example, at a time t 1 , where t 1 >t 0 , the outputs of O 0 through 09 of FF 0 through FF 9 can be represented as an output code of 0000111111, respectively. A transition from a logic “0” to a logic “1” can indicate that the rising edge of REFCLK 805 occurs between the VCO clocks that indicate the change. If the VCO clocks have the same frequency as REFCLK 805 , then sampling the REFCLK signal at the next clock signal of the VCO clocks will generate the same output at O 0 - 09 as the previous sample. In that case, if the sample occurred at a time t 2 , where t 2 >t 1 , then O 0 -O 9 can also have the same output code of 0000111111.

In a case where the frequency of REFCLK 805 is less than the point where a transition in outputs O 0 -O 9 would occur, the transition point would be shifted towards the left in a direction towards O 0 . For example, at a time t 2 , where t 2 >t 1 , then O 0 -O 9 can have an output code of 0011111000. The difference in time between the clock periods can be determined by comparing the output code at time t 2 with output code at time t 1 . This can be achieved by XOR'ing each bit of the second code with its corresponding bit from the first code. Notably, the XOR operation using XOR gates can determine how many bits have changed states between the two periods. Accordingly, since the period of the VCO signal changes while the period of the REFCLK signal remains fixed, the number of logic “1” (ones) at the output of the XOR gates can signify the number of T S 'S. For example, T s = T 20

and represent the shift between clocks comprising a clock set over one period of CLK 0 . In this regard, the clock set contains 20 clock signals although the invention is not limited in this regard.

Since the difference between the period, T R , of REFCLK and the VCO period, T, is equivalent to aT S , the prior equations utilized for determining the frequency range and error for the frequency detector 600 can be appropriately applied to the time detector 800 . However, an important difference can include the measurement of the frequency in the VCO. In the case of the frequency detector 600 , the error, T s T R = T VCO 20 × T R .

Since the period of the REFCLK signal is fixed, whenever the VCO period decreases, the error decreases. Consequently, the error with respect to REFCLK is variable. With regards to the time detector 800 , since a VCO clock signal is utilized as a reference clock, the error can be considered fixed. In this case, T s T VCO = T VCO 20 × T VCO = 1 20 .

A second difference pertains to the relationship between the number of logic “1's” and the VCO frequency or VCO period. In the case of the frequency detector, there is a linear relationship between the number of logic “1's” and the VCO frequency. However, there is a non-linear relationship between the number of logic “1's” and the VCO period. In the case of the time detector, there is a linear relationship between the number of logic “1's” and the VCO period. However, there is a non-linear relationship between the number of logic “1's” and the VCO frequency. Importantly, depending on the application and appropriate considerations regarding the relationship between time/frequency and the number of logic “1's,” either the time detector or the frequency detector can be utilized.

In light of the foregoing description of the invention, it should be recognized that the present invention can be realized in hardware, software, or a combination of hardware and software. A method and system for determining frequency and time variations between electronic signals according to the present invention can be realized in a centralized fashion in one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system, or other apparatus adapted for carrying out the methods described herein, is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which, when loaded in a computer system, is able to carry out these methods. Computer program or application in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduction in a different material form.

The embodiments and architecture described above should give a circuit designer greater flexibility in designing high-speed electronic circuits that require a high resolution to ensure proper synchronization during switching. Notably, the increased resolution can ensure that component and system functionality can be maintained during switching. Advantageously, the frequency and time detection method and circuit described herein can also provide a less costly design and development path than with current systems.

Additionally, the description above is intended by way of example only and is not intended to limit the present invention in any way, except as set forth in the following claims.