Phase inversion prevention circuit for an operational amplifier input stage

This application claims the benefit of provisional patent application No. 60/392,524 to Carter, filed Jun. 28, 2002.

1. Field of the Invention

This invention relates to the field of operational amplifier input stages, and particularly to methods of preventing phase inversion for a cascoded transistor op amp input stage.

2. Description of the Related Art

A basic op amp input stage is shown in FIG. 1. A differential pair MN 1 and MN 2 have their sources connected to a common mode node 10 , their gates connected to receive a differential input signal (V− and V+), and their drains connected to a load 12 (here, a pair of resistors). A tail current I tail is connected at common mode node 10 . MN 1 and MN 2 conduct respective currents through load 12 in response to the input signal, which creates an output voltage V out .

An op amp input stage has an associated common mode input range. For example, for FET and MOSFET input transistors, the common mode input range is defined as the voltage range over which the input devices are in the pinch-off region. For an N-channel FET, this condition is met when the FET's drain-source voltage V ds is greater than V gs −V p , where Vgs is the FET's gate-source voltage and V p is its pinch-off voltage.

There is an intrinsic diode (D 1 , D 2 ) present between the gate and drain of each input FET (or, for a bipolar input stage, between the base and collector of each input transistor). Normally, the drain voltage of an input FET decreases with a rising input. However, if the gate voltage V g of an input FET exceeds its drain voltage V d , the input stage is no longer within its common mode input range. If V g becomes sufficiently greater than V d , the intrinsic diode becomes forward-biased, such that a condition known as “phase inversion” occurs. When in this condition, a rising input at the gate of an input FET causes the voltage at its drain to increase, rather than decrease as it would normally. Phase inversion also causes the entire tail current I tail to be drawn through the input terminals.

Phase inversion can easily occur in a folded cascode input stage, in which cascode transistors are inserted in series with the drains of respective input transistors (assuming a FET input stage). The cascode transistors are driven with a cascode voltage, which is typically arranged to float with the common mode input voltage V cm [=(V++V−)/2]. If V cm gets too high, the transistor which creates the cascode voltage saturates, fixing the cascode voltage and thereby pinning the input FETs' drain voltages. When so pinned, the intrinsic diode of one of the input FETs can eventually become forward-biased, and phase inversion occurs.

A phase inversion prevention circuit for an operational amplifier input stage is presented, which overcomes the problems noted above.

The present phase inversion prevention circuit includes primary and secondary input pairs, and a detection circuit which detects when either of the primary input pairs' intrinsic diodes is near a forward-biased condition. When such a condition is detected, a switching network switches tail current from the primary input pair to the secondary input pair, which takes over the input stage's amplifying duties.

The invention is particularly suitable to use with folded cascode input stages, which are especially susceptible to phase inversion. In such applications, the detection circuit detects the onset of phase inversion by monitoring the which drives the cascode transistors. The outputs of the secondary input pair are connected to bypass the cascode transistors. Thus, when the onset of phase inversion is detected, the switching network operates to disable the primary input pair and enable the secondary input pair; with the cascode transistors bypassed, the secondary input pair avoids phase inversion.

Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

FIG. 1 is a schematic diagram of a known op amp input stage.

FIG. 2 is a schematic/block diagram which illustrates the basic principles of a phase inversion prevention circuit for an operational amplifier input stage per the present invention.

FIG. 3 is a schematic diagram of one possible embodiment of a phase inversion prevention circuit for an operational amplifier input stage per the present invention.

FIG. 4 a schematic diagram of another possible embodiment of a phase inversion prevention circuit for an operational amplifier input stage per the present invention.

A diagram which illustrates the basic principles of the present invention is shown in FIG. 2 . An operational amplifier's input stage includes a “primary” differential input pair MN 1 and MN 2 . The current circuits of MN 1 and MN 2 —the sources of FETs MN 1 and MN 2 in the exemplary embodiment shown—are connected together at a first common mode node 20 . When a tail current is provided at common mode node 20 , MN 1 and MN 2 conduct respective currents in response to a differential input signal applied to inputs V+ and V−. The respective currents are conducted through a load 22 to provide an output V out .

As noted above, input transistors MN 1 and MN 2 have intrinsic diodes D 1 and D 2 between their respective gates and drains. Phase inversion occurs when the gate voltage of one of the input transistors becomes greater than its drain voltage such that the transistor's intrinsic diode becomes forward-biased.

The invention overcomes this problem with a phase inversion prevention circuit 24 , which includes a phase inversion detection circuit 26 , a switching network 28 , and a “secondary” input pair Q 1 and Q 2 , which are preferably bipolar transistors. Q 1 and Q 2 have their emitters connected together at a common mode node 30 , their collectors connected to the drains of MN 1 and MN 2 , respectively, and their bases connected to V− and V+, respectively.

Phase inversion detection circuit 26 is arranged to detect when either of intrinsic diodes D 1 and D 2 is near a forward-biased condition. Switching network 28 is arranged to connect a tail current I tail to either common mode node 20 (thereby enabling MN 1 and MN 2 ) or to common mode node 30 (thereby enabling Q 1 and Q 2 ) in response to a control signal produced by detection circuit 26 . In operation, when detection circuit 26 is not detecting the onset of a forward-biased condition, switching network 28 connects tail current I tail to common mode node 20 , such that primary input pair MN 1 and MN 2 are enabled and produce V out . However, when detection circuit 26 detects that D 1 and/or D 2 is near a forward-biased condition, tail current I tail is switched from common mode node 20 to common mode node 30 . This disables the primary input pair and enables secondary input pair Q 1 and Q 2 , which now function to provide V out . In this way, phase inversion for the primary input stage is avoided.

Note that though the primary input stage in FIG. 2 is made with FETs, the invention is equally applicable to a bipolar primary input stage. Bipolar transistors also have intrinsic diodes which can become forward-biased such that a phase inversion condition results. As with a FET input stage, this condition can be detected and prevented with the present invention.

The diagram of FIG. 2 merely illustrates the basic principles of the invention. For the circuit shown in FIG. 2, if the conditions are such that the primary input pair is near a phase inversion condition, the secondary input pair is likely to also be so threatened—since the two input pairs are essentially connected in parallel. One way to reduce this possibility is with the use of a pair of level shifting diodes D 3 and D 4 , connected between V− and V+ and the inputs of Q 1 and Q 2 , respectively. The diodes serve to shift the common mode input voltage range of the secondary input pair up by a diode drop, such that—over at least a limited common mode input voltage range—the secondary input stage will not phase invert even if the primary stage does.

A more practical application of the invention is shown in FIG. 3 . Here, the op amp's input stage is in a “folded cascode” configuration. This design is popular, as it results in a common mode input range which is greater than would be possible using a conventional pair of current mirrors to output the differential output current.

The folded cascode input stage includes primary input pair MN 1 and MN 2 , having their sources connected to common mode node 20 as before. Here, however, the drain of MN 1 is connected to an output terminal 40 (and to a supply voltage VCC through a load resistor R 1 ) via a cascode transistor Q 3 , and the drain of MN 2 is connected to an output terminal 42 (and to VCC through a load resistor R 2 ) via a cascode transistor Q 4 . Differential output terminals 40 and 42 are connected to an output stage which includes transistors Q 5 -Q 8 , and which produces the stage's output voltage V out .

In practice, cascode transistors Q 3 and Q 4 limit the drain-source voltages of the input FETs to a value set by a “cascode voltage” V cascode connected to drive Q 3 and Q 4 . One mechanism for generating such a cascode voltage is shown in FIG. 3 : a current source transistor Q 9 , connected to supply voltage VCC, conducts a current I cascode in response to a fixed bias voltage V 2 . The output of Q 9 is connected to a resistor R 4 at a node 44 , and the other end of R 4 is connected to a transistor Q 10 , the base of which is connected to common mode node 20 . As long as Q 9 is not in saturation, the current I cascode through Q 10 and R 4 , and thus the voltage at node 44 , is essentially constant with respect to node 20 . The voltage at node 44 is the “cascode voltage” V cascode .

V cascode is an essentially constant voltage which floats with V cm . At some V cm value, current source transistor Q 9 saturates. With Q 9 saturated, I cascode starts to decrease with an increasing V cm , which in turn reduces V cascode . This reduces the voltages at the bases of Q 3 and Q 4 , which in turn reduces the voltages at their emitters and at the drains of MN 1 and MN 2 . With the MN 1 /MN 2 drain voltages falling, an increase in V cm can forward bias one of intrinsic diodes D 1 and D 2 and thereby cause a phase inversion condition.

As noted above, the invention prevents a phase inversion condition by switching tail current from primary input pair MN 1 /MN 2 to a secondary input pair when it is detected that a phase inversion condition is near. As shown in FIG. 3, the secondary input pair comprises bipolar transistors Q 1 and Q 2 . The emitters of Q 1 and Q 2 are connected together at common mode node 30 , their bases are connected to V− and V+, respectively, (preferably via respective diodes D 3 and D 4 , discussed below), and their collectors are connected to output terminals 40 and 42 , respectively. When so connected, the collectors of secondary input pair Q 1 /Q 2 bypass cascode transistors Q 3 and Q 4 , which substantially reduces the possibility of having their intrinsic diodes forward-biased by a high V cm .

One way in which the onset of a phase inversion condition can be detected is by monitoring current I cascode . As noted above, when current source transistor Q 9 saturates, I cascode starts to decrease as V cm continues to increase. This decrease in I cascode can be used to indicate the onset of a phase inversion condition. One implementation of this approach is shown in FIG. 3. A current source transistor Q 11 produces a bias current I bias in response to a fixed biased voltage V 3 , which is mirrored by a first current mirror 46 to produce a tail current I tail1 . This current is provided to common mode node 20 of primary input pair MN 1 /MN 2 . A second current mirror 48 mirrors I cascode to a “comparison node” 50 . Another current source transistor Q 12 produces a reference current I ref in response to a bias voltage V 4 ; I ref is also provided to comparison node 50 . Node 50 is connected to drive a diversion transistor Q 13 which is connected to divert I bias from current mirror 46 when on. Node 50 is also connected to drive a transistor Q 14 , which produces a tail current I tail2 . I tail2 is provided to common mode node 30 of secondary input pair Q 1 /Q 2 .

Currents I cascode and I ref are arranged such that, when Q 9 is not in saturation, the cascode current I cascode mirrored to comparison node 50 is greater than I ref . This keeps diversion transistor Q 13 turned off, such that I tail1 is generated and the primary input pair is enabled. However, when Q 9 saturates, I cascode decreases; when I cascode decreases to I ref , the voltage at the comparison node 50 (and the base of diversion transistor Q 13 ) increases. This causes Q 13 to turn on and divert I bias from current mirror 46 . When Q 13 is appropriately sized, all of I bias is diverted from current mirror 46 , I tail1 is reduced to zero, and primary input pair MN 1 /MN 2 is disabled. At the same time, a rising voltage at comparison node 50 causes Q 14 to begin providing I tail2 to common mode node 30 , thereby enabling secondary input pair Q 1 /Q 2 . The total current through the emitter of Q 13 —given by I ref +I bias (when Q 13 is sized to divert all of I bias )—determines the tail current I tail2 , which can be scaled up or down by establishing an appropriate emitter area ratio between Q 13 and Q 14 .

Once I tail2 is on, it pulls approximately the same amount of current out of the folding nodes as does the primary input pair—thereby maintaining the dynamics of the system. The secondary pair takes over the function of the op amp, maintaining op amp gain and output voltage when the common mode input voltage range is exceeded. Note that when the differential input is within the common mode input voltage range, the secondary bipolar input pair is reverse-biased, thereby limiting the op amp's input current to that of a conventional FET amplifier.

When implemented as shown in FIG. 3, the exact input FET drain-source voltage when the tail currents are switched from the primary stage to the secondary stage can be set by the appropriate sizing of I ref , I cascode , and the transistors making up current mirror 48 . The approximate common mode input voltage V cm(off) which corresponds to this drain-source voltage (for MN 1 in this example) is given by:

V

cm(off)

sat,Q9

−V

be,Q3

−V

ds

+V

gs

where V sat,Q9 is Q 9 's saturation voltage, V be,Q3 is Q 3 's base-emitter voltage, and V ds and V gs are MN 1 's drain-source and gate-source voltages, respectively.

As noted above, the bases of secondary input stage transistors Q 1 /Q 2 are preferably connected to V− and V+ via diodes D 3 and D 4 , respectively. The diodes serve to shift the common mode input range for the secondary input stage up by a diode drop. D 3 and D 4 also serve to limit the input bias current when the secondary input stage is disabled.

A resistor R 5 is preferably connected between common mode nodes 20 and 30 , to guarantee that the primary input stage turns back on when V cm returns to within the common mode input range. This resistor provides two functions: it maintains a small amount of current through the input FETs while the secondary input stage is enabled, and it provides a base current to Q 10 so that Q 9 can come out of saturation. The small amount of current maintained through the input FETs via R 5 defines an operating point, just as the tail current defined the operating point for the primary stage's turn-off mechanism. The “turn-on” common mode voltage V cm(on) is defined by the same equation given above for V cm(off) , except that V gs is defined by the size of R 5 and not the tail current. For an optimally-sized R 5 , V gs will be close to a pinch-off voltage. R 5 also forces the secondary bipolar input pair to be reverse-biased during normal operation, thereby reducing the input bias current.

When V cm returns to within the common mode input range, Q 9 comes out of saturation, I cascode and V cascode return to their constant values, I tail2 is turned off and I tail1 is turned back on, and the primary input stage resumes operation.

The secondary input stage preferably comprises bipolar transistors. FET devices could theoretically be used, but would require that several diodes be stacked in series with each input to get the inputs at or above the supply voltage (required to prevent phase inversion), and to keep the gate voltages low enough to allow the FETs to function properly.

An alternative mechanism for detecting the onset of phase inversion is shown in FIG. 4 . Instead of comparing the current I cascode which generates cascode voltage V cascode to a reference current I ref , the circuit in FIG. 4 senses the status of current source transistor Q 9 using collector feedback. A PNP transistor Q 15 has its base and collector connected in parallel with those of Q 9 , and its emitter is connected to a node 60 at the base of diversion transistor Q 13 . In operation, when Q 9 saturates, current is transferred through Q 15 to node 60 . This causes diversion transistor Q 13 to turn on and divert I bias from current mirror 46 as before.

Note that the specific circuit implementations shown in FIGS. 3 and 4 are merely exemplary. A number of other mechanisms could be employed to detect the onset of phase inversion, and to switch tail current from the primary input stage to the secondary input stage in response.

While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.