Disk drive writer with active reflection cancellation

The present invention relates to a driving circuit for the write head of a magnetic disk drive, and more particularly to a write driver utilizing active reflection cancellation to allow the circuit to provide an undistorted write signal with increased peak voltage delivered by the preamplifier compared to resistive impedance matched write circuits.

Rigid magnetic disk drives employ E-block assemblies supporting a plurality of actuator arms each having read and write heads at the distal end thereof and arranged to move with the E-block across the radius of the magnetic recording disk. The writer circuit, or write driver, is included in an integrated circuit chip mounted on the E-block at the proximal end of the actuator arms and is connected to the write heads at the distal end through interconnect cable.

A typical write circuit preamplifier generates a roughly square wave voltage pattern across a write head that results in a roughly square wave write current pattern through the write head. Each pulse is composed of a rise-time portion, an overshoot portion, and a steady-state portion. The overshoot portion is the portion of the pulse where the absolute value of the write current exceeds the absolute value of the steady-state current; for example, where the steady-state current is 40 mA, the overshoot current may reach a peak of about 70 mA. The rise-time is defined as the time that it takes the current to change from 10% to 90% of its steady-state value, as it swings from one direction to the other. Thus, for a writer programmed for 40 mA steady-state write current, the rise-time is defined as the time required for the current in the write head to change from −32 mA to +32 mA, and vice versa.

Historically, there have been many improvements to conventional write circuits to enhance their performance, primarily in the areas of enhancing the switching speed of the circuit to reduce the rise-time portion of the write current waveform, as well as working with the overshoot portion of the waveform to give a fast rise-time while minimizing undershoot and ringing. However, these improved write circuits have been unable to achieve impedance matching to the interconnect. Such impedance matching would require a small resistor in parallel with the write head which would shunt some of the write current away from the write head during operation of the circuit and thereby compromise the performance of the circuit. The lack of impedance matching results in pattern dependent distortion which limits the performance of the write circuit.

U.S. application Ser. No. 09/475,909 filed Dec. 30, 1999 for “Impedance-Matched Write Circuit” by J. Leighton, R. Barnett and T. Ngo, discloses an impedance-matched write circuit that operates on a principle that is somewhat different than that of conventional write circuits, thereby reducing or eliminating pattern dependent distortion. The impedance matching of this circuit improves the write driver's performance, but also results in a decrease in the voltage delivered by the write driver preamplifier caused by the voltage drop across the series impedance matching resistor.

It would be beneficial to provide a write driver that achieves the reduction and/or elimination of pattern dependent distortion that is provided by impedance matching while delivering the full voltage of the preamplifier to the write circuit. Such a write driver configuration is the subject of the present invention.

The present invention is a write driver circuit and method for selectively providing a write current through a write head in first and second opposite directions. The write driver circuit is connected to the write head through an interconnect. The write driver circuit provides an incident write current signal through the interconnect to the write head, and also provides a reflection cancellation signal through the interconnect to the write head. In an exemplary embodiment, the incident write current signal is provided by providing an incident voltage signal across the write head, and the reflection cancellation signal is provided by providing a reflection cancellation voltage signal across the write head. In an exemplary embodiment, the reflection cancellation signal is a delayed and filtered version of the incident write current signal that cancels a reflected signal that is reflected at the interface between the interconnect and the write head due to impedance mismatching.

FIG. 1 is a diagram illustrating a write circuit connected to a write head via an interconnect in a manner common to storage devices such as disk drives.

FIG. 2 is a diagram showing an exemplary write head voltage waveform provided by a write circuit across a write head.

FIG. 3 is a diagram showing an exemplary reflected write head voltage waveform which is also present across a write head in a system that is not impedance matched.

FIG. 4 is a diagram of an impedance matched write circuit.

FIG. 5 is a diagram of a reflection cancellation circuit according to the present invention.

FIG. 6 is a diagram modeling the impedance characteristics of a write head.

FIG. 7 is a diagram of an exemplary filter for emulating the reflection properties of the interface between an impedance mismatched interconnect and write head according to the present invention.

FIG. 8 is a diagram illustrating the signal generated by the preamplifier of a write circuit according to the present invention.

FIG. 9 is a diagram of a write circuit employing active reflection cancellation according to an exemplary embodiment of the present invention.

FIG. 10 is a diagram of an exemplary full circuit implementation of a write circuit employing active reflection cancellation in accordance with the present invention.

FIG. 1 is a diagram illustrating write circuit 10 connected to write head 12 via interconnect 14 , in a manner common to storage devices such as disk drives. While write head 12 is located to interact with the storage medium (such as a disk) directly, write circuit 10 is typically located remotely from write head 12 , which is why interconnect 14 is required to connect write circuit 10 to write head 12 .

Interconnect 14 has a characteristic impedance which is mismatched with the impedances of write circuit 10 and write head 12 . In an exemplary configuration, interconnect 14 has 100 Ohms differential impedance (Zdiff) and 30 Ohms common-mode impedance (Zcm), and write head 12 has 7 nano-Henries of inductance (L) in parallel with 200 Ohms parallel resistance (Rp) with a series resistance of 10 Ohms (Rs) in series with the parallel L-Rp circuit. The impedance mismatch causes pattern dependent distortion resulting from reflection of signals at the write circuit-interconnect interface and at the interconnect-write head interface.

FIG. 2 is a diagram showing an exemplary write head voltage waveform 20 provided by the write circuit across the write head. Write head voltage waveform 20 switches from an initial steady-state value (−Vss) to an opposite steady-state value (+Vss) in order to switch the direction of write current flowing through the write head. The waveform has a rise-time portion 22 when switching occurs, followed by an overshoot portion 24 and finally settling to the steady-state value.

FIG. 3 is a diagram showing an exemplary reflected write head voltage waveform 30 which is also present across the write head in a system that is not impedance matched. Referring briefly to FIG. 1 , write circuit 10 generates a signal at time that travels along interconnect 14 to write head 12 , arriving at time t 1 . The signal is reflected at the interface between interconnect 14 and write head 12 due to the impedance mismatch at that interface. The reflected signal is an attenuated and distorted version of the original signal, and it travels along interconnect 14 back to write circuit 10 , where it is reflected again due to the impedance mismatch at the interface between interconnect 14 and write circuit 10 . The reflected signal is further attenuated and distorted, and travels along interconnect 14 to write head 12 , arriving at time (t 1 +2τ), where τ is the propagation time of interconnect 14 . The “twice reflected” signal across the write head is shown as delayed, distorted signal 32 in FIG. 3 . Thus, the total signal present across the write head is the sum of the generated write head voltage waveform 20 shown in FIG. 2 and the reflected write head voltage waveform 30 shown in FIG. 3 .

The pattern dependent distortion of the reflected signal effectively limits the performance of the write driver circuit. One possibility for reducing reflections at the interconnect-write head interface is to move write circuit 10 onto the disk drive suspension so that write circuit 10 is located immediately adjacent to write head 12 , eliminating the need for interconnect 14 . There are many problems with this approach, including numerous mechanical issues and added cost, that make locating write circuit 10 on the disk drive suspension impractical.

As discussed previously, the reflections at the interfaces of interconnect 14 can be reduced or eliminated by implementing the impedance matched write circuit disclosed U.S. application Ser. No. 09/475,909. The concept of this circuit is shown in greatly simplified form in FIG. 4 . While this circuit improves the write driver's performance, it also results in a decrease in the voltage (V TL ) delivered by the write driver preamplifier to the interconnect and on to the write head, caused by the voltage drop across the series impedance matching resistor (R PA ). As write current overshoot requirements continue to increase, there will be a continuing need for the write circuit to provide as much voltage as possible. The present invention is an alternative write circuit design for reducing or eliminating pattern dependent distortion while providing a high level of voltage to the interconnect and the write head.

FIG. 5 is a diagram illustrating the concept of the present invention. A write circuit preamplifier generates a signal (V PA ) to drive the write head. This is the conventional write driver voltage signal, as shown in FIG. 2 . The write circuit also generates a signal (−V REF ) to cancel the reflected signal (V REF , shown in FIG. 3 ) caused by impedance mismatch that would otherwise result in pattern dependent distortion. The net signal delivered to the interconnect and on to the write head is therefore the same as the undistorted V PA signal shown in FIG. 2 , since the actual reflected signal is canceled by the reflection cancellation signal. This configuration does not have a voltage drop across an impedance matching resistor, and thus can deliver the entire V PA peak voltage to the write head to provide the required write current overshoot capability.

In order to achieve the desired performance, the −V REF cancellation signal must accurately match the timing and shape of the actual reflected signal due to the impedance mismatch between the interconnect and the write head. The delay time of the cancellation signal is twice the propagation time of the interconnect. The amplitude is based on the generated waveform and the reflection coefficient of the interface between the interconnect and the write head. This reflection coefficient is defined as:

Γ = Z H - R TL Z H + R TL ( Eq .   ⁢ 1 )

where Z H is the impedance of the write head and R TL is the characteristic impedance of the interconnect.

The impedance of the write head can be modeled relatively simply in the manner shown in FIG. 6 . The write head, defined between terminals 40 and 42 , has a series resistance R S , a parallel resistance R P and a parallel inductance L P . Thus, the impedance of the write head model is defined as:

Z H = R S + j ⁢   ⁢ ω ⁢   ⁢ R P ⁢ L P R P + j ⁢   ⁢ ω ⁢   ⁢ L P ( Eq .   ⁢ 2 )

Substituting Eq. 2 into Eq. 1 gives the reflection coefficient of the interface between the interconnect and the write head in terms of the write head and interconnect parameters:

Γ = R P ⁡ ( R S - R TL ) + j ⁢   ⁢ ω ⁢   ⁢ L P ⁡ ( R P + R S - R TL ) R P ⁡ ( R S + R TL ) + j ⁢   ⁢ ω ⁢   ⁢ L P ⁡ ( R P + R S + R TL ) ( Eq .   ⁢ 3 )

The reflection coefficient therefore consists of a pole and a zero:

2 ⁢   ⁢ π ⁢   ⁢ f POLE = R P ⁡ ( R S + R TL ) L P ⁡ ( R P + R S + R TL ) ( Eq .   ⁢ 4 ) 2 ⁢   ⁢ π ⁢   ⁢ f ZERO = R P ⁡ ( R S - R TL ) L P ⁡ ( R P + R S - R TL ) ( Eq .   ⁢ 5 )

The pole and zero frequencies are readily quantified by employing the following typical system parameters:

L P =7 nano-Henries (nH)

R S =10 Ohms (Ω)

R P =200 Ω

R TL =70 Ω

f POLE =−1.30 gigaHertz (GHz)

f ZERO =1.95 GHz

The frequencies of the poles and zero are convenient for realization by a relatively simple filter design known in the art. An example of a filter having these pole and zero frequencies is shown in FIG. 7 .

In order to effectively cancel a reflected signal, the cancellation signal must be both distorted properly (by the filter shown in FIG. 7 which emulates the reflection coefficient of the impedance mismatched interface between the interconnect and the write head) and delayed properly. Since analog delays are difficult to achieve in a silicon circuit context such as a disk drive circuit, it is preferable for the write voltage signal to be generated as a combination of square waves (digital signals), so that the delay function can be performed digitally, which is quite simple. The signal generated by the preamplifier (V PA , FIG. 5 ) is therefore a summation of square waves, as shown in FIG. 8 . The V PA waveform is constructed by summing two square waves, the second of which is delayed from the first by a programmed time constant. The −V REF signal (see FIG. 5 ) for canceling the reflected signal of the write circuit is constructed by delaying the V PA waveform by two interconnect time constants and by filtering it with a filter such as is shown in FIG. 7 to simulate the distortion caused by impedance mismatching.

FIG. 9 is a diagram of a write circuit employing active reflection cancellation according to an exemplary embodiment of the present invention. The write circuit basically includes two parts: an upper section including a pair of emitter follower transistors (Q 1 and Q 3 ) and resistors R 2 and R 3 , and a bottom section including a pair of current mirrors Q 0 -Q 2 and Q 5 -Q 4 ) and resistors R 0 , R 1 , R 4 , and R 5 . The circuit is configured as an H-bridge, as is generally well known in the art. In the embodiment shown, transistors Q 1 and Q 0 form one leg of the H, transistors Q 3 and Q 5 form the other leg of the H, and coil H W is connected across the center of the H between terminals H WP and H WN . The difference between the present invention and conventional H-bridge write circuits lies in the signals used to drive the circuitry. The driving signals are shown as ideal current sources I 0 , I 1 , I 2 and I 3 , representing the incident write current signal provided by the preamplifier (I 0 and I 3 ) and the reflection cancellation signal (I 1 and I 2 ), which is a delayed and filtered version of the incident write current signal as describe above.

In operation, the write circuit operates in an initial state when the incident write current signal is zero and the complement of the incident write current signal is a “high” value, meaning that no current flows through I 0 and that current flows “down” (toward ground) through I 3 . In this initial state, transistor Q 1 and the current mirror formed by transistors Q 5 and Q 4 are on, while transistor Q 3 and the current mirror formed by transistors Q 0 and Q 2 are off.

When a transition is to be recorded by the write head, the write current through the head switches directions. Thus, the incident write current signal switches from zero to a “high” value and the complement of the incident write current signal switches from a “high” value to zero, meaning that current flows “down” (toward ground) through I 0 and no current flows through I 3 . In this state, transistor Q 3 and the current mirror formed by transistors Q 0 and Q 2 are on, while transistor Q 1 and the current mirror formed by transistors Q 5 and Q 4 are off.

Following the switching of the write current by two interconnect time delays, the reflection cancellation signal cancels the actual reflected signal that is reflected back toward the write head. The reflection cancellation signal ( 12 ) is mirrored by the current mirror formed by transistors Q 0 and Q 2 , so that the 12 signal is subtracted from the incident write current signal I 0 . This effectively cancels the actual reflection of the write current signal that occurs due to the impedance mismatch at the interface between the interconnect and the write head.

When another transition is to be recorded by the write head, the write current through the head again switches directions. The incident write current signal switches from a “high” value to zero, meaning that no current flows through 10 and that current flows “down” (toward ground) through I 3 . In this state, transistor Q 1 and the current mirror formed by transistors Q 5 and Q 4 are on, while transistor Q 3 and the current mirror formed by transistors Q 0 and Q 2 are off.

Following the switching of the write current by two interconnect time delays, the complement of the reflection cancellation signal cancels the actual signal that is reflected back toward the write head. The complement of the reflection cancellation signal (I 1 ) is mirrored by the current mirror formed by transistors Q 5 and Q 4 , so that the I 1 signal is subtracted from the incident write current signal I 3 . This effectively cancels the actual reflection of the write current signal that occurs due to the impedance mismatch at the interface between the interconnect and the write head.

The circuit shown in FIG. 9 illustrates the present invention's ability to provide a signal that cancels a reflected signal occurring due to interconnect-write head impedance mismatching. This allows a clean, undistorted signal to be delivered to the write head while avoiding a drop in voltage available that occurs due to impedance matching with a series resistor.

FIG. 10 is a diagram of an exemplary full circuit implementation of a write circuit employing active reflection cancellation in accordance with the present invention. It should be understood that the circuit shown in FIG. 10 is shown to illustrate the best mode of practicing the invention, and should not be considered to limit the scope of the invention in any way. The portions of the circuit which functionally represent the components shown in FIG. 9 are shown in labeled blocks in order to simplify the understanding of the circuit. One skilled in the art will readily discern the operating characteristics of the overall circuit, in conjunction with the specification and drawings of the instant application and of U.S. application Ser. No. 10/219,948 filed on even date herewith for “Disk Drive Writer With Capacitive Boost” by J. Leighton, C. Elliott, M. O'Brien, C. Rabe, N. Krenz, R. Wimmer and S. O'Brien, which is hereby incorporated by reference.

Specifically, FIG. 10 shows a connection to a filter at terminals VFILTERP and VFILTERN in order to emulate the reflection coefficient of the head to interconnect interface to generate reflection cancellation currents I 1 and I 2 . The filter may be realized in an exemplary embodiment in the manner shown in FIG. 7 . Terminals VNONDELAYN, VNONDELAYP, VDELAYP and VDELAYN provide the summed square wave signals for forming the write currents I 0 and I 3 .

The present invention achieves the desirable effects of impedance matching (reduced or eliminated distortion of the write signal delivered to the write head) without the drop in signal level that occurs due to passive impedance matching, such as by a series impedance matching resistor. This is achieved by actively canceling the reflected signal that occurs to impedance mismatching between the interconnect and the write head. The reflection cancellation signal is generated by distorting the incident write signal with a filter that emulates the reflection coefficient of the interconnect-write head interface, and by delaying the signal by twice the interconnect propagation time. As a result, pattern dependent distortion in the write signal is reduced or eliminated, improving the performance of the write circuit.

Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. Particularly, while some forms of the invention are described in the form of discrete devices, it is recognized that the circuit is preferably reduced to practice in the form of an integrated circuit (IC). Therefore, terms such as “device” and the like should be construed in their broadest contexts to include portions of ICs that are conveniently described as functional components, as well as discrete devices. Likewise, some forms of the invention are described in terms of logical gates and chips that could also be implemented by discrete devices, all within the scope and spirit of the present invention.