Method and apparatus for automatic wiring design between block circuits of integrated circuit

1. Field of the Invention

The present invention relates to a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method.

2. Description of the Related Art

As the latest semiconductor integration circuit becomes to have higher integration density and larger scale, the number of wires increases and also a demand arises for much narrower wire region and much higher integration density thereof.

FIG. 12 is a view for illustrating a conventional method for automatic wiring design between block circuits of an integrated circuit.

As shown in this figure, inter-block wires 12 and 13 are disposed between circuit blocks 10 and 11 , terminals 101 and 102 are formed along a side 10 S of the circuit block 10 which faces the circuit block 11 , and terminals 111 and 112 are formed along a side 11 S of the circuit block 11 which faces the circuit block 10 . A contact hole 101 C is formed at a cross portion between the inter-block wire 12 and a wire 101 L extended from the terminal 101 , and is connected to the wire 101 L. Similarly, a contact hole 112 C is formed at a cross portion between the inter-block wire 12 and a wire 112 L extended from the terminal 112 , and is connected to the wire 112 L. Through these contact holes 101 C and 102 C, the block wire 12 is connected to the wires 101 L and 112 L belonging to upper or lower wire layers, respectively. The terminal 101 , the wire 101 L, the contact hole 101 C, the inter-block wire 12 , the contact hole 112 C, the wire 112 L and the terminal 112 belong to a same net.

In a case where the terminal 102 , the inter-block wire 13 and the terminal 111 belong to a same net, the terminal 111 and the inter-block wire 13 can be connected to each other as shown in this figure, but the terminal 102 and the inter-block wire 13 cannot be connected to each other. Wiring layout processes has already been performed for the inside of the circuit blocks 10 and 11 , and the block information in the inter-block wiring is given only about the frame and the terminal of the block, and therefore wire extension from the terminal to the internal of the block is forbidden in the inter-block wiring.

Thus, the prior art employs a method as shown in FIG. 13 where interval between the circuit blocks 10 and 11 is made widened; a wire 102 L is extended and bent from the terminal 102 ; a contact hole 102 C is formed at a cross portion between the wire 102 L and the inter-block wire 13 ; and the wire 102 L and the inter-block wire 13 are connected to each other through the contact hole 102 C. This falls into increasing the wiring area between the circuit blocks 10 and 11 and also changing the wiring area between the circuit block 10 or 11 and other circuit blocks not shown, causing the rewiring. In order to avoid this problem, a manual connection must be carried out between the blocks in the layout state shown in FIG. 12, but it requires much longer time in design.

In addition, in a case where the terminals 102 and 112 and the inter-block wire 12 belong to a same net as shown in FIG. 14, if the terminal 112 and the inter-block wire 12 are first connected to each other through the wire 112 L, a contact hole 112 C is formed in the same size as the width of the terminal 112 . Therefore, when the terminal 102 and the contact hole 112 C are connected to each other through the wire 102 L, the wire resistance is increased due to the insufficient area of the contact hole 112 C, which causes increase in the signal delay and timing error. In a case where the wire is used for supplying the power supply, the increased wire resistance lowers the supplied voltage and the electromigration tolerance, resulting in reducing the reliance of the integration circuit.

In order to avoid these problems, a method can be considered as shown in FIG. 15 where the area between the circuit blocks 10 and 11 is secured in advance two times as that in the case shown in FIG. 12; additional inter-block wires 12 A and 13 A are disposed parallel to the inter-block wires 12 and 13 ; the inter-block wires 12 A and 13 A are connected to the inter-block wires 12 and 13 , respectively; the inter-block wires 12 and 13 are used for connection with the terminals of the circuit block 10 ; and the inter-block wires 12 A and 13 A are used for connection with the terminals of the circuit block 11 . However, this method leads to increase in the inter-block area.

Accordingly, it is an object of the present invention to provide a method and an apparatus for automatic wiring design between block circuits of an integrated circuit and a program for performing the same method, which gives priority order to wring so as to reduce manual processes by decreasing the number of not-connected wires as a result of the automatic wiring process, and also reduce the wiring area required to form the inter-block wiring.

In one aspect of the present invention, there is provided a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other, the method comprising the steps of:

(a) sorting the terminals according to the width thereof; and

(b) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal.

According to this method, the connection is made for the block terminals in descending order of the width thereof, and therefore the length of extended wire from larger width terminals becomes shorter, which allows reducing the inter-block wiring area. In addition, because forming the contact hole is also performed in descending order of the width thereof, it can be avoided that a larger width wire is connected to a smaller width contact hole.

In another aspect of the present invention, the method for automatic wiring design between block circuits of an integrated circuit comprises the steps of:

(a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and

(b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.

According to this method, the connection is made for the terminal having larger current value, earlier than the terminal having smaller current value even though they have the same width. This allows the length of a wire, which connects between the terminal having larger current value and the inter-block wire, to be shorter than a wire which connects between the terminal having smaller current value and the inter-block wire. Therefore the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order. Further, this can prevent the voltage reduction due to the wire resistance.

FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic flow chart of part of the program stored in the storage shown in FIG. 1 .

FIG. 3 is a view showing a layout before performing the inter-block connection, which is used for illustrating the data stored in the storage 22 shown in FIG. 1 .

FIG. 4 is a view for illustrating step S 6 shown in FIG. 2 .

FIG. 5 is a view for illustrating step S 8 shown in FIG. 2 .

FIG. 6 is a view for illustrating step S 10 shown in FIG. 2 .

FIG. 7 is a view for illustrating step S 11 shown in FIG. 2 .

FIG. 8 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 2 .

FIG. 9 is a layout view showing another case where the automatic connection is made by the method shown in FIG. 2 .

FIG. 10 is a schematic flow chart for partly showing the method for automatic wiring design between the circuit blocks of an integrated circuit according to a second embodiment of the present invention.

FIG. 11 is a layout view showing a case where the automatic connection is made by the method shown in FIG. 10 .

FIG. 12 is a view for illustrating a problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.

FIG. 13 is a view for illustrating a problem in a conventional method where automatic connection and correction is made for the layout state shown in FIG. 12 .

FIG. 14 is a view for illustrating another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.

FIG. 15 is a view for illustrating still another problem in a conventional method for automatic wiring design between block circuits of an integrated circuit.

Hereinafter, the present invention will be described in more detail referring to the drawings.

First Embodiment

FIG. 1 is a schematic block diagram showing the hardware configuration of the apparatus for automatic wiring design between block circuits of an integrated circuit according to a first embodiment of the present invention.

The apparatus of this embodiment is a computer system which comprises, as shown in FIG. 1, a computer 20 , and storages 21 ˜ 23 , an input device 24 and a display device 25 , each coupled to the computer 20 . The computer 20 loads a program stored in the storage 21 into a main storage, in response to a starting command from the input device 24 . According to the program, the computer 20 reads wiring data from the storage 22 ; automatically performs inter-block connection; stores result of the automatic connection in the storage 23 ; and displays the contents of log file, including the achievement ratio of automatic wiring, not-connected information and the like, on the display device 25 .

FIG. 3 is a view for illustrating the data stored in the storage 22 shown in FIG. 1, where inter-block wires 12 and 13 are disposed between circuit blocks 10 and 11 , terminals 101 and 102 are formed along a side 10 S of the circuit block 10 which faces the circuit block 11 , and terminals 111 and 112 are formed along a side 11 S of the circuit block 11 which faces the circuit block 10 .

The storage 22 stores, as wiring data, frame data of the circuit blocks 10 and 11 , data of terminals 101 and 102 in the circuit block 10 and terminals 111 and 112 in the circuit block 11 , data of inter-block wires 12 and 13 , and net-list for inter-block connection. The data of the block frame and the block terminal is a cell data registered in a cell library, where the data of the block frame includes the identification code, the position, the size and the direction thereof, the data of the block terminal includes the identification code and the position and the size thereof. The direction of the block corresponds to an angle between the direction of its cell in the cell library and the altered direction after it is disposed in the design surface. The data of the inter-block wire includes the identification code, the end position, and the width thereof.

FIG. 2 is a schematic flow chart of part of the program stored in the storage 21 shown in FIG. 1 . The following parenthesized reference numerals refer to steps shown in FIG. 2 .

(S 1 ) The wiring data is read out of the storage 22 .

(S 2 ) Terminals formed along sides of blocks facing each other are sorted in descending order of the width (largest width first). For example, in a case of FIG. 3, terminals 101 , 112 , 102 and 111 are sorted in the mentioned order.

(S 3 ) A next larger width terminal is selected. In the beginning, a terminal having the largest width is selected.

(S 4 ) If there is no terminal to be selected in step S 3 , the procedure is finished, and if not, it moves to step S 5 .

(S 5 ) If there is no contact hole already formed on an inter-block wire belonging to the same net as the terminal selected in step S 3 , the procedure moves to step S 6 , and if not, it moves to step S 7 .

(S 6 ) A wire having the same width as the terminal selected in step S 3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net. For example, in a case shown in FIG. 4 where a terminal 101 and an inter-block wire 12 belong to the same net and there is no contact hole formed on the inter-block wire 12 , a wire 101 L is extended from the terminal 101 in the direction perpendicular to a side 10 S; a contact hole 101 C is formed at the cross portion between the wire 101 L and the inter-block wire 12 ; and the wire 101 L is connected to the contact hole 101 C. The inter-block wire 12 belongs to lower or upper wire layers with respect to the wire 101 L and is connected to the wire 101 L through the contact hole 101 C. Thereafter, the procedure returns to step S 3 .

(S 7 ) when it is assumed that a wire having the same width as the terminal selected in step S 3 is extended from the selected terminal, with the shortest extended route satisfying the design rule and is connected to the inter-block wire belonging to the same net, if the cross portion between the extended wire and the inter-block wire, that is, the contact hole to be formed is overlapped with the already-formed contact hole, the procedure moves to step S 8 , and if not, it moves to step S 9 . For instance, in a case shown in FIG. 5 where the terminal 101 has already been connected to the inter-block wire 12 , and a contact hole 101 C has been formed between the wire 101 L and the inter-block wire 12 , when a wire 111 A is virtually extended from the terminal 111 in the direction perpendicular to the side 11 S, the cross portion with the inter-block wire 12 is overlapped with an already-formed contact hole 101 C, and therefore the procedure moves to step S 8 .

(S 8 ) Without forming a contact hole, the terminal selected in step S 3 is connected to the contact hole overlapped therewith. For instance, in a case shown in FIG. 5, the terminal 111 is connected to the already-formed contact hole 101 C through a bent wire 111 L. Thereafter, the procedure returns to step S 3 .

(S 9 ) In a case where a space width between the wire extended in step S 7 and the wire which belongs to the same net as the extended wire and has been connected to the already-formed contact hole satisfies the design rule, the procedure moves to step S 10 , and if not, it moves to step S 11 . For instance, as shown in FIG. 6, the branch or cross of destination is determined based on whether the design rule is satisfied by the space width SL between the wire 111 L extended from the terminal 111 and the wire 101 L connected to the already-formed contact hole 101 C.

(S 10 ) In the case shown in FIG. 6, a contact hole 111 C is formed at the cross portion between the inter-block wire 12 and the wire 111 L extended in step S 7 , and the terminal 111 is connected to the contact hole 111 C through the wire 111 L. Thereafter, the procedure returns to step S 3 .

(S 11 ) In a case as shown in FIG. 7 where the space width SL between the wire 111 A extended in step S 7 and the already-formed wire 101 L does not satisfy the design rule, the terminal 111 is connected to the contact hole 101 C through a bent wire 111 L, without forming a new contact hole. Thereafter, the procedure returns to step S 3 .

FIGS. 8 and 9 show examples where the automatic connection is performed by the method shown in FIG. 2 .

FIG. 8 shows a case where terminals 102 and 111 and an inter-block wire 13 belong to one same net, and terminals 101 and 112 and an inter-block wire 12 belong to another same net. As shown in this figure, the terminals 101 and 102 have widths larger than the terminals 111 and 112 , and therefore after connection between the terminals 101 and 102 is performed in step S 6 shown in FIG. 2, connection between the terminals 111 and 112 is performed in step S 10 shown in FIG. 2 .

This method allows reducing the wiring region between the circuit blocks 10 and 11 , compared with the conventional case shown in FIG. 13 .

FIG. 9 shows a case where terminals 101 and 111 and an inter-block wire 13 belong to one same net, and terminals 102 and 112 and an inter-block wire 12 belong to another same net. As shown in this figure, the terminals 101 and 102 have width larger than the terminals 111 and 112 , and therefore after the connection processes for the terminals 101 and 102 are performed in step S 6 shown in FIG. 2, the connection processes for the terminals 111 and 112 are performed in step S 8 shown in FIG. 2 .

This method prevents forming of the contact hole 112 C having a narrow width as shown in FIG. 14 .

Second Embodiment

A method for automatic wiring design between block circuits of an integrated circuit according to the second embodiment of the present invention employs a procedure shown in FIG. 10 instead of step S 2 shown in FIG. 2 .

(S 20 ) When there is a block terminal connected to a power supply wire, the procedure moves to step S 21 , and if not, it moves to step S 23 .

(S 21 ) Calculation has been made in advance for obtaining the value (time average or maximum value) of electric current flowing through each block terminal connected to the power supply wire, and the storage 22 shown in FIG. 1 has stored the obtained current value. The terminals connected to the power supply wire are sorted in descending order of the current value.

(S 22 ) The same repeated procedure as the steps S 3 ˜S 11 shown in FIG. 2 is performed for the terminals connected to the power supply wire. However, differently from the first embodiment, a terminal having next larger current value is selected in step S 3 shown in FIG. 2 .

(S 23 ) If there is a block terminal connected to a signal wire, the procedure moves to step S 2 , which is the same as step S 2 shown in FIG. 2, and if not, the procedure is finished.

FIG. 11 shows an example where the automatic connection is performed by the method shown in FIG. 10 .

FIG. 11 shows a case where inter-block wires 12 and 13 are power supply wires; terminals 101 and 112 and an inter-block wire 12 belong to one same net, and terminals 102 and 111 and an inter-block wire 13 belong to another same net. The terminals 111 , 102 , 101 and 112 are in descending order of the current value, and their connection processes are performed in the order.

According to this method, the connection is made for the terminal 102 having larger current value I 2 , earlier than the terminal 112 having smaller current value I 1 even though they have the same width, which allows the power supply wire to be shortened in length, so that the whole electromigration tolerance of an integrated circuit is improved compared with a case where the connection is made in inverse order.

In addition, the number of inter-block wires is only required to be more than one, and also the number of terminals formed along the block sides facing each other is only required to be more than one. Further, the circuit block may be anyone of a cell, a macro cell, or a hard macro, or the like. Furthermore, a method may be employed where calculation is made for obtaining the current value (time average or maximum value) of the signal terminal, and the connection is made in descending order of the current value for the signal terminals having the same width. This method also improves the electromigration tolerance.

The forgoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of apparatuses or methods. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.