Full rate error detection circuit for use with external circuitry

1. Field of the Invention

This invention generally relates to digital communications and, more particularly, to a system and method for minimizing the effects of inter-symbol interference in a non-return to zero (NRZ) data channel.

2. Description of the Related Art

FIG. 1 is a diagram illustrating a signal recovered from a binary symmetric, non-dispersive channel in the presence of noise (prior art). Conventionally, the signal is filtered with a transfer function matched to the signaling waveform (in this case a one unit step) and thresholded at the voltage level most likely to yield the transmitted bit. To recover the transmitted information, a hard decision must be made on the value of the received bit.

As a function of the filtering process, and sometimes as a result of the transmission process, pulse spreading occurs. That is, the energy associated with a bit spreads to neighboring bits. For small degrees of spreading these effects of this can be limited to the nearest neighbors with modest degradation in performance.

Three basic types of pulse spreading exist. The first possibility is that both the neighboring bits are a zero (no neighboring bits are a one). The second possibility is that only one of the neighboring bits (either the preceding or subsequent bit) is a one. Alternately stated, only one of the neighboring bits is a zero. The third possibility is that both neighboring bits are one. The degree of dispersion exhibited by a channel, and hence the separation of the probability density functions, varies in response to a number of fixed and variable factors. Effective dispersion mitigation techniques must therefore be easily optimized to the channel and somewhat adaptive to changes in the channel due to aging, temperature changes, reconfiguration, and other possible influences.

It would be advantageous if multiple thresholds could be used to set and adjust an optimal threshold detection level.

The present invention provides a means of determining the optimal voltage level for a single serial data input threshold without the use of an external bit error rate calculator. The optimal threshold level can be determined and the threshold adjusted over the course of normal operation. The present invention is a relatively simple process that permits the bit error rate of a receiver system to be reduced. The error detection circuit allows the receiver chip to recover an input data signal with a poor “eye”. Therefore, system designers can run data signals over a longer distance of fiber optic cable before needing to receive and retransmit the signal. This leads to lower system costs.

Accordingly, a method is provided for selecting an optimal threshold detection level for a single serial data input receiver. The method comprises: receiving a serial data stream of pseudorandom binary information; using a plurality of threshold detection levels, estimating bit values; comparing the differences between estimated bit values; and, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values.

Estimating bit values using a plurality of threshold detection levels includes: establishing a first threshold (V 1 ) to distinguish a high probability one bit value estimate; establishing a second threshold (V 0 ) to distinguish a high probability zero bit value estimate; and, establishing a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds.

In some aspects, comparing the differences between estimated bit values includes: for each received bit, examining the results of the three thresholds; counting a first number of differences between the outputs of the first and third thresholds; counting a second number of differences between the outputs of the second and third thresholds. Then, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values includes adjusting the first and second thresholds until the first number equals the second number. Once the first and second thresholds are determined, the optimal (third) threshold can be determined approximately midway between the first and second thresholds.

Additional details of the above-described method and a system for selecting an optimal threshold detection level in a single serial data input receiver are provided below.

FIG. 1 is a diagram illustrating a signal recovered from a binary symmetric, non-dispersive channel in the presence of noise (prior art).

FIG. 2 is a schematic diagram of the present invention system for selecting an optimal threshold detection level in a single serial data input receiver.

FIG. 3 is a schematic diagram illustrating a threshold adjustment circuit.

FIGS. 4 a and 4 b are flowcharts illustrating the present invention method for selecting an optimal threshold detection level for a single serial data input receiver.

FIG. 2 is a schematic diagram of the present invention system for selecting an optimal threshold detection level in a single serial data input receiver. The system 300 comprises a first toggle flip-flop 302 having an input to accept differences between first and third threshold detector outputs on line 304 , and an output on line 306 to supply a first tally of the differences. A second toggle flip-flop 308 has an input on line 310 to accept differences between second and third threshold detector outputs, and an output on line 312 to supply a second tally of differences.

FIG. 3 is a schematic diagram illustrating a threshold adjustment circuit. Threshold adjustment circuit 400 has an input connected to the output of the first flip-flop on line 402 and an input connected to the output of the second flip-flop on line 404 . The threshold adjustment circuit 400 has an output on line 406 to supply first threshold value (V 1 ), an output on line 408 to supply second threshold value (V 0 ), and an output on line 410 to supply third threshold value (Vopt). The threshold adjustment circuit 400 creates a first count of the first tally and a second count of the second tally. The threshold adjustment circuit 400 adjusts the three thresholds in response to comparing the first and second counts.

Returning to FIG. 2 , the system 300 further comprises a first exclusive-OR 314 (XOR) having an input on line 316 to accept the first threshold detector output (onesdata), an input on line 318 to accept the third threshold detector output (hoggedata), and an output on line 304 connected to the first flip-flop input. A second XOR 320 has an input on line 322 to accept the second threshold detector output (zerosdata), an input on line 318 to accept the third threshold detector output, and an output on line 310 connected to the second flip-flop input. D flip-flops 324 , 326 , and 328 are used to retime the comparator outputs to a common data clock (hoggeclky) on line 329 .

Returning to FIG. 3 , a first comparator 412 has an input on line 414 to accept a pseudorandom serial data stream, an input connected to the threshold adjustment circuit output on line 406 to accept the first threshold, and an output on line 416 (onesdata) connected to the first XOR to supply the first threshold detector output. The first comparator 412 distinguishes when the data stream input on line 414 has a high probability of being a “1” bit value.

A second comparator 418 has an input on line 414 to accept the pseudorandom serial data stream, an input connected to the threshold adjustment circuit output on line 408 to accept the second threshold, and an output on line 420 connected to the second XOR to supply a second threshold detector output. The second comparator 418 distinguishes when the data stream input on line 414 has a high probability of being a “0” bit value. The first threshold is set to a relatively high voltage level so that only a high voltage signal triggers the first comparator. Likewise, the second threshold is set to a relatively low voltage level so that only a very low voltage fails to trigger the second comparator.

A third comparator 422 has an input on line 414 to accept the pseudorandom serial data stream, an input connected to the threshold adjustment circuit output on line 410 to accept the third threshold, and an output on line 424 connected to the first and second XORs to supply a third threshold detector output. The third comparator 422 distinguishes the data stream input on line 414 with the optimal threshold detection level. In some aspects, the first 412 , second 418 , and third 422 comparators receive non-return to zero (NRZ) serial input data on line 414 . Once the optimal threshold detection level has been set with certainty, the first and second comparators 412 / 418 are no longer needed. Likewise, once the optimal threshold detection level has been set on line 410 , the above-mentioned threshold adjustment circuit is no longer required.

Considering FIGS. 2 and 3 , the threshold adjustment circuit 400 adjusts the first threshold on line 406 and the second threshold on line 408 to make the first count equal the second count. The threshold adjustment circuit 400 adjusts the third threshold on line 410 approximately midway between the first and second thresholds. When a channel asymmetry is known, the third threshold can be offset to account for the asymmetry. In some aspects of the invention, the threshold adjustment circuit 400 has an input on line 414 to measure the serial data input voltage. The threshold adjustment circuit 400 averages the serial data input voltage and initially sets the third threshold on line 410 equal the average serial data input voltage.

Some aspects of the system 300 further comprise a first divider 330 (see FIG. 2 ) having an input connected to the output of the first flip-flop on line 306 and an output on line 402 connected to the threshold adjustment circuit input. Likewise, a second divider 332 has an input on line 312 connected to the output of the second flip-flop and an output on line 404 connected to the threshold adjustment circuit input. As shown, the first and second dividers 330 and 332 are divide-by-64 dividers. However, the invention is not limited to any particular division ratio.

Functional Description

The error detection circuit outputs the rate of differences between the outputs of three variable threshold comparators, as applied to the incoming data stream. To accomplish this, the incoming data stream is sent through three variable threshold comparators each with a discrete threshold. The error detection circuit clocks in the outputs of the three threshold comparators and increments a counter if the threshold operations result in different output states. Two separate comparisons are made, one between the middle threshold voltage data (Vopt) and a high threshold voltage data (V 1 ), the other between middle threshold voltage data and a low threshold voltage data (V 0 ). Each time a difference occurs, a counter is incremented. There are two counters, one for each of the comparisons.

In operation, the middle threshold voltage level is set to the serial data's average voltage using a sense line. Both the high voltage threshold level and the low threshold level are varied such that differences result from the comparisons. The rate of these differences is measured by an external circuit, such as the threshold adjust circuit. That circuit adjusts the high and the low voltage threshold levels until the rate of differences resulting from the two comparisons is equal. The optimal middle threshold voltage level is the average of the high threshold voltage and the low threshold voltage. This voltage is then applied to the middle threshold circuit and the bit error rate is reduced.

Three threshold comparators with discrete threshold voltages, high (V 1 ), mid (Vopt), and low (V 0 ), are applied to the incoming serial data stream. The outputs of these threshold detectors are sampled simultaneously at the serial data rate producing three serial data channels. The data compared using threshold voltages high, mid, and low produce respective data channels, high data, mid data, and low data. From this point on, the error detection circuit is symmetrical and the mid data channel passes into both sides of the circuit. The mid data channel and either the high or low data channel are inputs to an XOR logic gate. The result of this function is passed to a toggle flip-flop (T-FF). The output of this flip-flop is fed into a divide-by-64 circuit such that the maximum frequency on the output line is reduced. This is acceptable as only the rate of differences between thresholded bits is relevant.

FIGS. 4 a and 4 b are flowcharts illustrating the present invention method for selecting an optimal threshold detection level for a single serial data input receiver. Although the method is depicted as a sequence of numbered steps for clarity, no order should be inferred from the numbering unless explicitly stated. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. The method starts at Step 500 .

Step 502 receives a serial data stream of pseudorandom binary information. In some aspects, a non-return to zero (NRZ) data stream is received. Step 504 , using a plurality of threshold detection levels, estimates bit values. Step 506 compares the differences between estimated bit values. Step 508 adjusts the threshold levels to minimize the difference between comparisons of estimated bit values.

In some aspects of the method, estimating bit values using a plurality of threshold detection levels in Step 504 includes substeps. Step 504 a establishes a first threshold (V 1 ) to distinguish a high probability one bit value estimate. Step 504 b establishes a second threshold (V 0 ) to distinguish a high probability zero bit value estimate. Step 504 c establishes a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds. Although the invention is described as using a three level input differentiation scheme, it should be understood that the present invention concept has broader applications and is not limited to any particular number of thresholds.

In other aspects, comparing the differences between estimated bit values in Step 506 includes substeps. Step 506 a , for each received bit, examines the outputs of the three thresholds. Step 506 b counts a first number of differences between the outputs of the first and third thresholds. Step 506 c counts a second number of differences between the outputs of the second and third thresholds. Then, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values in Step 508 includes adjusting the first and second thresholds until the first number equals the second number.

In some aspects, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values in Step 508 further includes adjusting the third threshold approximately midway between the first and second thresholds. In some aspects the method includes a further step. Step 510 uses the third threshold as the optimal threshold detection level. The serial data can then be detected using the optimal (third) threshold detection level.

In other aspects, adjusting the threshold levels to minimize the difference between comparisons of estimated bit values in Step 508 includes other substeps. Step 508 a averages the voltage of the serial data stream. Step 508 b initially adjusts the third threshold to equal the serial data stream average voltage.

In some aspects, counting a first number of differences between the outputs of the first and third thresholds in Step 506 b includes substeps. Step 506 b 1 sums the differences between the outputs of the first and third thresholds. Step 506 b 2 divides the sum by a third number to generate the first number. Likewise, counting a second number of differences between the outputs of the second and third thresholds in Step 506 c includes substeps. Step 506 c 1 sums the differences between the outputs of the second and third thresholds. Step 506 c 2 divides the sum by the third number to generate the second number. In one aspect of the method, the third number is equal to 64.

In other aspects, summing the differences between the outputs of the first and third thresholds in Step 506 b 1 includes additional substeps. Step 506 b 1 a performs an exclusive-OR (XOR) operation comparing the first and third threshold outputs. Step 506 b 1 b toggles the first number when a “1” bit is generated. Likewise, summing the differences between the outputs of the second and third thresholds in Step 506 c 1 includes substeps. Step 506 c 1 a performs an exclusive-OR operation comparing the second and third threshold outputs. Step 506 c 1 b toggles the second number when a “1” bit is generated.

A system and method have been presented for selecting an optimal threshold detection level for a single serial data input receiver. Some specific circuit examples have given for implementation of the present invention concept. However, the invention is not necessarily limited to these examples. Further, the invention has been presented in the context of a three-threshold system. However, the invention would be applicable to systems with a different number of thresholds. Other variations and embodiments of the invention will occur to those skilled in the art.