Semiconductor device provided using wiring data of common design core

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-209682, filed Jul. 10, 2001, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a semiconductor device including a circuit having a multilayer wiring structure and, more specifically, to a system LSI to be designed using an IP (intellectual property) core.

2. Description of the Related Art

With development of a fine device structure and a high integration density of a semiconductor device according to progress of process technology,

a system LSI including a plurality of function blocks (circuits) in or on one chip has recently been achieved. In this system LSI, a general-purpose function block is efficiently designed reusing an IP core (design core) that is past design resources.

FIG. 7 shows a semiconductor memory chip using an SRAM (Static Random Access read write Memory) as an example of a system LSI.

In the case of the semiconductor chip 100 , when the device is designed, part of the device logic section 102 is designed using an SRAM design core 101 that is an IP core. Therefore, the development and design can be effectively carried out.

However, the system LSI includes various types of function blocks according to the specification of the device (product). For example, some function blocks have a four-level wiring structure and other function blocks have a five-level wiring structure. Further, some function blocks having the same number of wiring layers include a thick wiring layer like a function block whose uppermost wiring layer serves as a power line or a high-speed signal line.

For the reasons described above, conventionally, IP cores must be prepared for every each type of function blocks in order to improve efficiency of the design of the system LSI.

FIGS. 8A and 8B show an example of a system LSI in which two different function blocks IP 1 and IP 2 are provided on a single chip. FIG. 8A is a plan view of the chip and FIG. 8B is a cross-sectional view showing a main part (wiring layers) of the chip.

Referring to FIGS. 8A and 8B , the function block IP 1 corresponding to an IP core IP 1 a includes a four-level layer structure having four wiring layers M 1 to M 4 . It is seen from FIG. 8B that the wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers).

At the time of designing the system LSI, the IP core IP 1 a having wiring data for forming each of the wiring layers M 1 to M 4 is read out from a library and used, as illustrated in FIGS. 9A and 9B .

As shown in FIG. 10B , the function block IP 2 corresponding to an IP core IP 2 a includes a four-level layer structure having four wiring layers M 1 to M 4 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers).

The wiring pitch of the uppermost wiring layers M 4 is wider than the wiring layers M 1 to M 3 and each of the wiring layers M 4 is thicker than each of the wiring layers M 1 to M 3 . Each of the thick uppermost wiring layers M 4 is used as the power supply line, the signal line or the like.

At the time of designing the system LSI, the IP core IP 2 a having wiring data for forming each of the wiring layers M 1 to M 4 is read out from the library and used, as illustrated in FIG. 10 A.

FIGS. 11A and 11B show an example of a system LSI in which three different function blocks IP 3 , IP 4 and IP 5 are provided on a single chip. FIG. 11A is a plan view of the chip and FIG. 11B is a cross-sectional view showing a main part (wiring layers) of the chip.

Referring to FIG. 11A , the function block IP 3 corresponding to an IP core IP 3 a is formed to include a five-level layer structure having five wiring layers M 1 to M 5 . It is seen from FIG. 11B that the wiring layers M 1 to M 5 have the same wiring pitch and the same thickness (thin wiring layers).

The function block IP 4 corresponding to an IP core IP 4 a includes a five-level layer structure having five wiring layers M 1 to M 5 . The wiring layers M 1 to M 4 in these wiring layers M 1 to M 5 have the same wiring pitch and the same thickness (thin wiring layers), as is seen from FIG. 11 B.

The wiring pitch of the uppermost wiring layers M 5 is wider than the wiring layers M 1 to M 4 and each of the wiring layers M 5 is thicker than each of the wiring layers H 1 to M 4 . Each of the thick uppermost wiring layers M 5 is used as the power supply line, the signal line or the like.

The function block IP 5 corresponding to an IP core IP 5 a includes a four-level layer structure having four wiring layers M 1 to M 4 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers), as is seen from FIG. 11 B.

The wiring pitch of the uppermost wiring layers M 4 is wider than the wiring layers M 1 to M 3 and each of the wiring layers M 4 is thicker than each of the wiring layers M 1 to M 3 . Each of the thick uppermost wiring layers M 4 is used as the power supply line, the signal line or the like.

In this case, also, the IP core IP 3 a for forming each of the wiring layers M 1 to M 5 of the function block IP 3 , the IP core IP 4 a for forming each of the wiring layers M 1 to M 5 of the function block IP 4 , and the IP core IP 5 a for forming each of the wiring layers M 1 to M 4 of the function block IP 5 are stored in the library.

As described above, an IP core adapted to the type of the function block (more specifically the structure of wiring layers) is read out from the library and used to design a general-purpose function block to be formed on a chip. Therefore, it is necessary to prepare IP cores for every each function block of different type in order to design the function blocks with efficiency.

Therefore, general-purpose function blocks can be efficiently designed reusing IP cores. However, there is a problem that PI cores are prepared for each of function blocks of different types.

A semiconductor device according to an aspect of the present invention comprises a plurality of circuits, provided on a semiconductor substrate, each having a plurality of wiring layers, the plurality of circuits being designed using a common design core to which a plurality of wiring data are allocated.

A semiconductor device according to another aspect of the present invention comprises first and second circuits, provided on a semiconductor substrate, each having a plurality of multilayer wiring layers, the first and second circuits being designed using a common design core to which wiring data corresponding to a first multilayer wiring structure common to the first and second circuits and a second wiring layer located on the first multilayer wiring structure is allocated.

FIGS. 1A and 1B is a schematic diagram showing a system LSI (four-layer device) according to a first embodiment.

FIGS. 2A and 2B show an example of a common IP core used for designing the four-layer device.

FIG. 3 is a diagram explaining a method of designing the four-layer device using the common IP core.

FIGS. 4A and 4B are schematic diagrams showing a system LSI (five-layer device) according to a second embodiment.

FIGS. 5A and 5B show an example of a common IP core used for designing the five-layer device.

FIG. 6 is a diagram explaining a method of designing the five-layer device using the common IP core.

FIG. 7 is a schematic diagram of a system LSI taking a semiconductor memory chip using an SRAM as an example in order to explain prior art and its problems.

FIGS. 8A and 8B are schematic diagrams showing a prior art system LSI (four-layer device).

FIGS. 9A and 9B show an example of an IP core used for designing the prior art four-layer device.

FIGS. 10A and 10B show another example of the IP core used for designing the prior art four-layer device.

FIGS. 11A and 11B are schematic diagrams showing a prior art system LSI (five-layer device).

Embodiments will now be described with reference to the accompanying drawings.

FIGS. 1A and 1B show an example of a system LSI according to a first embodiment. The first embodiment is directed to a four-layer device in which two function blocks (circuits) IP 1 and IP 2 each having four-level wiring layers are provided on a single chip. FIG. 1A is a plan view of the chip and FIG. 1B is a cross-sectional view of a main part (wiring layers) of the chip.

Referring to FIGS. 1A and 1B , the function block (second circuit) IP 1 is produced to have a four-level layer structure having four wiring layers M 1 to M 4 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers).

The uppermost wiring layers M 4 (at least part of the plurality of wiring layers) have a wiring pitch wider than the wiring layers M 1 to M 3 and the same thickness as the wiring layers M 1 to M 3 (thin wiring layer).

On the contrary, the function block (first circuit) IP 2 is provided to have a four-level layer structure having four wiring layers M 1 to M 4 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers).

The wiring pitch of the uppermost wiring layers (at least part of the plurality of wiring layers) M 4 is wider than the wiring layers M 1 to M 3 and is thicker than the wiring layers M 1 to M 3 . The thick uppermost wiring layers M 4 are used as the power supply line, the signal line, or the like.

In the case where the system LSI includes function blocks IP 1 and IP 2 having the multilayer wiring structure with different types, it will be designed using a common IP core (design core) described later.

FIGS. 2A and 2B show an example of the common IP core IPa used for designing the foregoing four-layer device.

In the case of the common IP core IPa, in the wiring layers M 1 to M 4 , wiring data M 1 to M 3 for forming the wiring layers M 1 to M 3 have the same wiring pitch and the same thickness (thin wiring layers).

In FIG. 2B , M 4 I and M 4 S indicate wiring data for producing the uppermost wiring layers M 4 . The wiring data (second wiring data) M 4 I has a wiring pitch wider than the wiring layers M 1 to M 3 and the same thickness as that of each of the wiring layers M 1 to M 3 (thin wiring layers).

In contrast, the wiring data (first wiring data) M 4 S has the same wiring pitch as that of the wiring data M 4 I (the pitch is wider than the wiring layers M 1 to M 3 ) and a thickness which is thicker than each of the wiring layers M 1 to M 3 . The wiring data M 4 S is thick wiring layers.

As described above, the two wiring data M 4 I and M 4 S having the wiring pitch and different thickness are allocated to the common IP core IPa in accordance with the uppermost wiring layers (at least part of the wiring layers) M 4 .

When the above four-layer device is designed, the common IP core IPa is read out from a library and thus can be used to form two function blocks IP 1 and IP 2 of different types according to the specifications of the device as shown in, e.g., FIG. 3 .

More specifically, when the function block IP 1 is produced, MDP (mask data processing) is accomplished to produce the uppermost wiring layers M 4 using the wiring data M 4 I of the common IP core IPa. When the function block IP 2 is produced, the MDP is done to form the uppermost wiring layers M 4 using the wiring data M 4 S of the common IP core IPa. Thus, the common IP core can be easily used to form the function block IP 1 having the thin wiring layers as the uppermost wiring layers M 4 or to form the function block IP 2 having the thick wiring layers as the uppermost wiring layers M 4 .

As described above, a plurality of wiring data having the wiring pitch in common can be selected in accordance with the type of function blocks.

Wiring data for producing both the thin wiring layers and the thick wiring layers, which have the wiring pitch in common, are provided as the wiring data of the IP core to form the uppermost wiring layers. Thus, one IP core can be used to design a plurality of function blocks of different types. Therefore, it can be possible to employ one IP core for designing a plurality of function blocks with different types. Consequently, the IP cores need not be prepared for every function blocks of different types and the function blocks can be designed with efficiency.

FIGS. 4A and 4B show an example of a system LSI according to a second embodiment. The second embodiment is directed to a five-layer device in which three function blocks (circuits) IP 3 , IP 4 and IP 5 having a given number of multilayer wiring layers are provided on a single chip. In this device, the use of a thin fourth wiring layers M 4 as the power supply line or the signal line causes a shortage of the current-carrying capacity, and therefore the capacity is reinforced with the fifth wiring layers MS. FIG. 4A is a plan view of the chip and FIG. 4B is a cross-sectional view showing a main part (wiring layers) of the chip.

Referring to FIGS. 4A and 4B , the function block (second circuit) IP 3 is produced as a five-level layer structure having five wiring layers M 1 to M 5 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 5 have the same wiring pitch and the same thickness (thin wiring layers).

The fourth wiring layers M 4 (at least part of the plurality of wiring layers or at least one intermediate wiring layer) have a wiring pitch wider than the wiring layers M 1 to M 3 and the same thickness as the wiring layers M 1 to M 3 (thin wiring layer).

The uppermost wiring layers M 5 (at least part of the plurality of wiring layers) have the same wiring pitch as the wiring layers M 4 (the wiring pitch is wider than the wiring layers M 1 to M 3 ) and the same thickness as the wiring layers M 1 to M 4 (thin wiring layer).

The fourth wiring layers M 4 are used as the power supply line, the signal line or the like. The uppermost wiring layers M 5 are used to reinforce the current-carrying capacity that is decreased due to the use of the fourth wiring layers M 4 for power supply line, the signal line or the like.

On the other hand, the function block (first circuit) IP 4 is formed as a five-level layer structure having five wiring layers M 1 to M 5 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 5 have the same wiring pitch and the same thickness (thin wiring layers).

The fourth wiring layers M 4 (at least part of the plurality of wiring layers or at least one intermediate wiring layer) have a wiring pitch wider than the wiring layers M 1 to M 3 and the same thickness as the wiring layers M 1 to M 3 (thin wiring layers).

The uppermost wiring layers M 5 (at least part of the plurality of wiring layers) have the same wiring pitch as the fourth wiring layers M 4 (the wiring pitch is wider than the wiring layers M 1 to M 3 ) and a thickness thicker than the wiring layers M 1 to M 4 . Therefore, the uppermost wiring layers MS are the thick wiring layers.

In this case, the fourth wiring layers M 4 are used as the power supply line, the signal line or the like. The uppermost wiring layers M 5 are used to reinforce the current-carrying capacity that is decreased due to the use of the thin fourth wiring layers M 4 for the power supply line, the signal line or the like.

The function block (third circuit) IP 5 is provided as a four-level layer structure having four wiring layers M 1 to M 4 . The wiring layers M 1 to M 3 in these wiring layers M 1 to M 4 have the same wiring pitch and the same thickness (thin wiring layers).

The uppermost wiring layers M 4 (at least part of the plurality of wiring layers) have a wiring pitch wider than the wiring layers M 1 to M 3 and a thickness thicker than the wiring layers M 1 to M 3 . Therefore, the uppermost wiring layers M 4 are thick wiring layers. The thick uppermost wiring layers M 4 are used as the power supply line, the signal line, or the like.

The system LSI having function blocks IP 3 , IP 4 and IP 5 whose multilayer wiring structures are different in type is designed using a common IP core (design core) that will be described later.

FIGS. 5A and 5B show an example of a common IP core IPb used for designing the foregoing five-layer device.

In the case of the common IP core IPb, the wiring layers M 1 to M 3 in the wiring layers M 1 to M 5 have the same wiring pitch and the same thickness (thin wiring layers).

In FIG. 5B , M 4 I and M 4 S indicate wiring data for producing the fourth wiring layers M 4 . The wiring data M 4 I (second wiring data) has a wiring pitch wider than the wiring layers M 1 to M 3 and the same thickness as that of each of the wiring layers M 1 to M 3 (thin wiring layers).

The wiring data M 4 S (first wiring data) has the same wiring pitch as the wiring data M 4 I (the pitch is wider than the wiring layers M 1 to M 3 ) and a thickness thicker than the wiring layers M 1 to M 3 . The wiring data M 4 S includes therefore thick wiring layers.

In FIG. 5B , M 5 I, M 5 S and M 5 N indicate wiring data for producing the uppermost wiring layers M 5 respectively. The wiring data M 5 I (second wiring data) has the same wiring pitch as the wiring layers M 4 (the pitch is wider than the wiring layers M 1 to M 3 ) and the same thickness as that of each of the wiring layers M 1 to M 3 (thin wiring layer).

The wiring data M 5 S (first wiring data) has the same wiring pitch as the wiring data M 5 I (the pitch is wider than the wiring layers M 1 to M 3 ) and a thickness thicker than the wiring layers M 1 to M 3 . The wiring data M 5 S includes therefore thick wiring layers.

The wiring data M 5 N (third wiring data) serves as dummy data to prevent the fifth (uppermost) wiring layers M 5 from being formed when the fourth wiring layers M 4 are so thick that the power supply need not be reinforced.

As described above, the two wiring data M 4 I and M 4 S having the wiring pitches in common and also having different thickness are allocated to the common IP core IPb corresponding to the fourth wiring layers M 4 , and the three wiring data M 5 I, M 5 S and M 5 N having the wiring pitches in common and having also different thickness are allocated to the common IP core IPb corresponding to the uppermost wiring layers M 5 .

The wiring pitch of each of the wiring data M 4 I and M 5 I for forming the thin wiring layers is equal to that of the wiring data M 4 S and M 5 S for producing the thick wiring layers.

Accordingly, when the above five-layer device is designed, the common IP core IPb will be read out from the library and thus can be used to form three function blocks IP 3 , IP 4 and IP 5 with different types according to the specifications of the device as shown in, e.g., FIG. 6 .

That is, the common IP core IPb is subjected to the MDP (Mask Data Processing) to obtain the wiring layer structure of each of function blocks IP 3 , IP 4 and IP 5 .

For example, for producing the function block IP 3 , the MDP is executed to form the wiring layers M 4 and M 5 using the wiring data M 4 I and M 5 I of the common IP core IPb. When the function block IP 4 is produced, the MDP is executed to form the wiring layers M 4 and M 5 using the wiring data M 4 I and M 5 S of the common IP core IPb. When the function block IP 5 is formed, the MDP is executed to form the wiring layers M 4 and M 5 using the wiring data M 4 S and M 5 N of the common IP core IPb.

Thus, the common IP core can be easily used to produce the function block IP 3 that reinforces the current-carrying capacity decreased in the fourth wiring layers M 4 with the thin uppermost wiring layers M 5 , the function block IP 4 that reinforces the current-carrying capacity with the thick uppermost wiring layers M 5 , or the function block IP 5 that need not reinforce the current-carrying capacity with the uppermost wiring layers M 5 .

In the five-layer device according to the second embodiment, also, the IP core need not be prepared for each of function blocks of different types and thus the function blocks can be designed with efficiency.

Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.