Circuit and method for repairing column in semiconductor memory device

The present disclosure relates to circuits and methods for repairing a column in a semiconductor memory device, and more particularly, to a circuit and method for repairing a column in a semiconductor memory device which is improved to change an externally inputted block address in a row active state according to a block address for column repair in a structure for sharing row repair lines of an adjacent block memory array.

Generally, under the condition that even one cell among a plurality of fine cells comprising a dynamic random access memory (DRAM) is defective, the DRAM cannot perform a normal function. A redundancy method has been widely employed to increase a production yield by replacing the defective cell with a spare memory cell previously mounted into the DRAM. Such a redundancy method is used for replacing a defective cell with a redundancy cell prepared in rows and columns in advance when a memory cell is checked as defective, thereby wasting no chip.

A conventional repair method is explained with reference to FIGS. 1-3. In particular, a typical 8-block memory array structure comprising one bank 2 in a DRAM, an X-decoder 4 , and a Y-decoder 6 is illustrated in FIG. 1 . Here, the X-decoder 4 and the Y-decoder 6 are configured to provide a signal such as row address and column address for controlling the active state of cells contained in each block.

As shown in FIG. 1, I, J and K are block selecting address, and each block is prepared with a certain number of redundant row/column repair lines for salvaging the defective cell. However, there is a limitation on the amount of cells in one block that may be salvaged by repair. Thus, it is necessary to use repair lines of an adjacent block to increase the repair efficiency.

Further, the adjacent block indicates one of a pair of blocks whose block address bit I and K are identical and which is selected by block address bit J. In this case, an adjacent block selecting signal SELF_PAIRb<0:7> determines which repair line to use among repair lines of the pair of blocks. This adjacent block selecting signal SELF_PAIRb<0:7>, as an output signal from a row fuse box (not shown), is determined based on cut state of a fuse within the row fuse box.

In other words, if the adjacent block selecting signal SELF_PAIRb<i> (i=0-7) is at a high level, the repair lines corresponding to an externally inputted block address are used for repair, or if the adjacent block selecting signal SELF_PAIRb<i> is at a low level, the repair lines of an adjacent block of a block corresponding to an externally inputted block address is used for the repair.

For example, in a case where all row repair lines of block 0 have been put into use, if an additional row repair for block 0 is needed, the adjacent block selecting signal SELF_PAIRb is provided at a low level in order to use row repair lines of block 2 . Thus, even though the block address (e.g., [000]) corresponding to block 0 is inputted, the row repair lines of block 2 are selected by the adjacent block selecting signal SELF_PAIRb<0>.

Because a column repair method also has block address information, the defective column is replaced by a column repair line if any one of columns in a selected block is defective. However, in the conventional repair method for sharing row repair lines of an adjacent block, there is a problem if a column repair state is not considered when a row repair is performed by using the row repair lines of the adjacent block.

In the conventional repair method for sharing rowrepair lines of an adjacent block, a column repair circuit without considering a column repair state is further explained with reference to FIGS. 2 and 3. FIG. 2 is a circuit diagram illustrating a conventional column repair circuit without considering a column repair state in the conventional repair method for sharing row repair lines of an adjacent block. The column repair circuit includes a column redundancy fuse unit 20 , a column redundancy decoding unit 30 and a column redundancy determining unit 40 .

Here, the column redundancy fuse unit 20 receives a column redundancy start signal YREDST and block address RAT<9:11> and inverted block address RAB<9:11>, and generates column address control signals YES<1:7> and an initializing signal YFJB of the column address control signal. Each bit of block address RAT <9:11> is corresponding to block address K, J, I in FIG. 1 . RAB<9:11> is generated by inverting signal level of each bit of RAT<9:11>.

The column redundancy decoding unit 30 decodes column address BYAC<1:7> in response to the column address control signals YFS<1:7> and the initializing signal YFJB of the column address control signal, and generates decoded column address YAJ<1:7>. The column redundancy determining unit 40 generates a column redundancy signal YREDC for column repair based on the decoded column address YAJ<1:7>.

In the column repair circuit, a column repair state is not reflected during a row repair because externally inputted block address RAT<9:11> and RAB<9:11> are inputted into the column repair circuit as they are (i.e., not inverted). As a result, a defect in a column cannot be detected.

Referring to FIG. 3, for example, assuming that a defective column of block 2 is repaired and the row repair of block 0 is performed by using an adjacent block 2 which is an adjacent block, it is necessary to reflect a column defect state for row repair lines of block 2 selected for the row repair of block 0 during the repair. In other words, a defective column of the row repair lines of block 2 needs to be replaced by a column repair line to repair a column defect for the row repair lines of block 2 .

When the adjacent block selecting signal SELF_PAIRb<0> is a high level, row repair lines of the block designated by the inputted block address [000] (i.e., row repair lines of block 0 ) is used, thereby causing no problem. However, when the adjacent block selecting signal SELF_PAIRb<0> is a low level, the row repair lines of the adjacent block(block 2 ) is used. But, because the inputted block address is a block address [000] corresponding to block 0 , not a block address [010] corresponding to block 2 , a defect state of block 2 is not detected. Hence, a column defect state is not reflected during the row repair by using the row repair lines of the adjacent block.

One aspect of the present disclosure is to improve the repair efficiency of a semiconductor memory device by repairing a defective column according to a column defect state when a defect is present in a column of the row repair lines of the adjacent block selected for row repair, in a semiconductor memory device or sharing row repair lines of an adjacent block.

According to one aspect of the present disclosure, there is provided a circuit for repairing a column in a semiconductor memory device comprising an adjacent block selecting fuse circuit for generating an adjacent block selecting signal in response to a column redundancy start signal, the adjacent block selecting signal determining whether to use row repair lines of a block designated by an externally inputted block address or row repair lines of an adjacent block of the block. A column redundancy fuse circuit receives the adjacent block selecting signal, the block address, an inverted block address, and the column redundancy start signal, and generates a plurality of column address control signals and initializing signal of the column address control signal. A column redundancy decoding circuit decodes column address in response to the initializing signal and the plurality of column address control signals, and generates decoded column address. A column redundancy determining circuit generates a column redundancy signal based on the decoded column address. The column redundancy fuse unit includes an address transmission unit to transmit an adjacent block designating bit designating the adjacent block among the block address and an inverted adjacent block designating bit designating the adjacent block among the inverted block address in response to the adjacent block selecting signal.

According to another aspect of the present disclosure, there is provided a method for repairing a column in a semiconductor memory device, which comprises the steps of: generating an adjacent block selecting signal in response to a column redundancy start signal, the adjacent block selecting signal determining whether to use row repair lines of a block designated by an externally inputted block address or row repair lines of an adjacent block of the block; transmitting an adjacent block designating bit for designating the adjacent block among the block address and an inverted adjacent block designating bit for designating the adjacent block among an inverted block address in response to the adjacent block selecting signal; generating a plurality of column address control signals and an initializing signal of the column address control signal in response to the column redundancy start signal, the adjacent block designating bit, the inverted adjacent block designating bit, and a plurality of bit in which the adjacent block designating bit and the inverted adjacent block designating bit are removed form the block address and the inverted block address; generating decoded column address by decoding the initializing signal, the column address control signal and one bit of column address; and repairing a defective column by generating a column redundancy signal in response to decoded column address.

FIG. 1 is a block diagram illustrating a general block structure of one bank of a conventional semiconductor memory device;

FIG. 2 is a block diagram illustrating a conventional column repair circuit;

FIG. 3 is a block diagram illustrating a column defect state of the conventional column repair circuit as shown in FIG. 2;

FIG. 4 is a block diagram illustrating a circuit for repairing a column in a semiconductor memory device constructed in accordance with the teachings of the present invention;

FIG. 5 is a circuit diagram of an adjacent block selecting fuse unit of FIG. 4;

FIG. 6 is a circuit diagram of a column redundancy fuse unit of FIG. 4; and

FIG. 7 is a circuit diagram of a column redundancy decoding unit of FIG. 4 .

FIG. 8 is a circuit diagram of a column redundancy determining unit of FIG. 4 .

Hereinafter, devices constructed in accordance with the teachings of the present disclosure will be described in detail with reference to the accompanying drawings. Referring to FIG. 4, a column repair circuit includes an adjacent block selecting fuse unit 100 , a column redundancy fuse unit 200 , a column redundancy decoding unit 300 and a column redundancy determining unit 400 .

The adjacent block selecting fuse unit 100 receives a column redundancy start signal YREDST, and generates an adjacent block selecting signal SELF_PAIRb. The adjacent block selecting signal SELF_PAIRb determines whether to use either row repair lines of the block designated by an externally inputted block address or row repair lines of an adjacent block.

The column redundancy fuse unit 200 transmits an externally inputted block address bit RAT<10> and an inverted block address bit RAB<10> which is an inverted signal of RAT<10> as it is when the adjacent block selecting signal SELF_PAIRb is at a high level. The column redundancy fuse unit 200 exchanges the block address bit RAT<10> with inverted block adress bit RAB<10> and transmits them when the adjacent block selecting signal SELF_PAIRb is a low level. The column redundancy fuse unit 200 also generates column address control signals YFS<1:7> and an initializing signal YFJB of the column address control signal by using the block address bit RAT<10>, the inverted block address bit RAB<10>, the column redundancy start signal YREDST, block address bit RAT<9>, RAT<11>, and inverted block address bit RAB<9>, RAB<11>.

The column redundancy decoding unit 300 decodes column address BYAC<1:7> in response to the column address control signals YFS<1:7> and the initializing signal YFJB of the column address control signal and, and generates decoded column address YAC<1:7>.

The column redundancy determining unit 400 generates a column redundancy signal YREDC for column repair based on the decoded column address YAJ<1:7>.

Referring to FIG. 5, the illustrated adjacent block selecting fuse unit 100 includes inverters I 1 , I 2 , I 3 , I 4 and I 5 (i.e., a first inverter I 1 , a second inverter I 2 , etc.), PMOS transistors P 1 and P 2 (i.e., a first PMOS transistor P 1 , etc.), NMOS transistors N 1 and N 2 (i.e., a first NMOS transistor N 1 , etc.), a NAND gate ND 1 , and a fuse F 1 . The PMOS transistor P 1 includes a source connected to a power voltage Vdd, and a drain connected to a node A. A column redundancy start signal YREDST is applied to a gate of the PMOS transistor P 1 . The inverter I 3 inverts a signal of the node A. The PMOS transistor P 2 includes a source connected to the power voltage Vdd, and a drain connected to the node A. An output signal of an inverter I 3 is applied to a gate of the PMOS transistor P 2 . The NMOS transistor N 1 includes a source connected to a ground voltage Vss. The column redundancy start signal YREDST is applied to a gate of the NMOS transistor N 1 . The NMOS transistor N 2 includes a source connected to a drain of the NMOS transistor N 1 . The power voltage Vdd is applied to a gate of the NMOS transistor N 2 . The fuse F 1 is connected between the drain of the NMOS transistor N 2 and the node A. Inverters I 1 and I 2 buffer the column redundancy start signal YREDST, which is enabled to a high level in a row active state. The NAND gate ND 1 logically combines an output signal of the inverter I 2 and the signal of the node A. Inverters I 4 and I 5 buffer an output signal of the NAND gate ND 1 to output an adjacent block selecting signal SELF_PAIRb.

Next, the operation of the above-described adjacent block selecting fuse unit 100 will be described with reference to FIG. 5 . The column redundancy start signal YREDST is enabled to a high level in a row active state. When column redundancy start signal YREDST is at a low level, an input of NAND gate ND 1 becomes a low level, and thus the adjacent block selecting signal SELF_PAIRb is enabled to a high level regardless of whether a fuse F 1 is cut or not. Thereby, the column redundancy signal YREDC that is described in detail below, is at a low level in its initial state and thus a main column decoder (not shown) is enabled. At this time, the node A becomes at a high level by turning on PMOS transistor P 1 .

If the fuse F 1 is not cut and the column redundant start signal YREDST is at a high level, in a row active state a discharge path to the NMOS transistor N 1 is formed and thus the adjacent block selecting signal SELF_PAIRb becomes a high level. As a result, row repair lines of the block designated by the inputted block address are used.

In contrast, if the fuse F 1 is cut, in the row active the discharge path to the NMOS transistor N 1 is disconnected and thus the adjacent block selecting signal SELF_PAIRb becomes a low level. As a result, row repair lines of the adjacent block are used.

That is, it is possible to determine whether or not use row repair lines of the adjacent block according to cut state of the fuse F 1 .

Referring to FIG. 6, the column redundancy fuse unit 200 includes an address transmission unit 210 , a fuse unit 220 , a control signal generating unit 230 , and an initializing signal generating unit 240 .

Further, RAT<9:11> represents an externally inputted block address in a row active state, and RAB<9:11> represents an inverted signal of the block address RAT<9:11>. YREDST represents a column redundancy start signal that is enabled to a high level in the row active state. YFJB represents an initialization signal of the column redundancy control signal that is precharged to a high level by the column redundancy start signal YREDST of a low level in its initial state.

In the address transmission unit 210 , the inverters I 6 and I 7 invert the adjacent block selecting signal SELF_PAIRb. Transmission gates T 1 , T 2 , T 3 and T 4 transmit an adjacent block designating bit(J-block address bit) RAT<10> for designating an adjacent block or an inverted adjacent block designating bit RAB<10> under the control of the adjacent block selecting signal SELF_PAIRb and output signals of the inverters I 6 and I 7 .

The address transmission unit 210 transmits an externally inputted block address bit RAT<10> to a gate of NMOS transistors N 6 and transmits an inverted block address bit RAB<10> to gate of NMOS transistor N 7 if the adjacent block selecting signal SELF_PAIRb is at a high level. In contrast, the address transmission unit 210 transmits the externally inputted block address bit RAT<10> to the gate of NMOS transistor N 7 and transmits the inverted block address bit RAB<10> to the gate of NMOS transistor N 6 if the adjacent block selecting signal SELF_PAIRb is at a low level.

The fuse unit 220 receives an output signal of the address transmission unit 210 , the column redundancy start signal YREDST, and K and I block address bit RAT<9>, RAT<11> and inverted K and I block address bit RAB<10>, RAB<11> and determines an output signal of the control signal generating unit 230 by fuse F 2 -F 7 that are cut according to row repair and column repair.

In the fuse unit 220 , the inverters I 8 and I 9 buffer the column redundancy start signal YREDST. The PMOS transistor P 3 includes a source connected to a power voltage Vdd, and a drain connected to a node B. The column redundancy start signal YREDST is applied to a gate of the PMOS transistor P 3 . The inverter I 10 inverts a signal of the node B. The PMOS transistor P 4 includes a source connected to the power voltage Vdd, and a drain connected to the node B. An output signal of the inverter I 10 is applied to a gate of the PMOS transistor P 4 . The NMOS transistor N 3 includes a source connected with the ground voltage Vss. The column redundancy start signal YREDST is applied to a gate of the NMOS transistor N 3 . The NMOS transistor N 4 includes a source connected with a drain of the NMOS transistor N 3 . The block address bit RAT<9> is applied to a gate of the NMOS transistor N 4 . The fuse F 2 is connected between a drain of the NMOS transistor N 4 and the node B. The NMOS transistor N 5 includes a source connected to the drain of the NMOS transistor N 3 . The inverted block address bit RAB<9> is applied to a gate of the NMOS transistor N 5 . The fuse F 3 is connected between, a drain of the NMOS transistor N 5 and the node B. The NMOS transistor N 6 includes a source connected to the drain of the NMOS transistor N 3 . One of output signals of the transmission gates T 1 and T 2 is applied to a gate of the NMOS transistor N 6 . The fuse F 4 is connected between a drain of the NMOS transistor N 6 and the node B. The NMOS transistor N 7 includes a source connected with the drain of the NMOS transistor N 3 . One of output signals of the transmission gates T 3 and T 4 is applied to a gate of the NMOS transistor N 7 . The fuse F 5 is connected between a drain of the NMOS transistor N 7 and the node B. The NMOS transistor N 8 includes a source connected with the drain of the NMOS transistor N 3 . The block address bit RAT<11> is applied to a gate of the NMOS transistor N 8 . The fuse F 6 is connected between a drain of the NMOS transistor N 8 and the node B. The NMOS transistor N 9 includes a source connected with the drain of the NMOS transistor N 3 . The inverted block address bit RAB<11> is applied to a gate of the NMOS transistor N 9 . The fuse F 7 is connected between a drain of the NMOS transistor N 9 and the node B. The NAND gate ND 2 logically combines an output signal of the inverter I 9 and a signal of the node B.

The control signal generating unit 230 includes a plurality of column address control signal generating unit 201 - 207 for generating a plurality of column address control signals YFS<1:7> in response to an output signal of the fuse unit 220 , and a column address initializing signal generating unit 208 for generating an initializing signal YFJB of the column address control signal.

When the initializing signal generating unit 240 receives the column redundancy start signal YREDST of a low level, the initializing signal YFJB of the column address control signals is precharged to a high level in its initial state.

In the column address control signal generating unit 201 , a PMOS transistor P 5 has a source connected to a power voltage Vdd. A signal of a node C is applied to gate of the PMOS transistor P 5 . The NMOS transistor N 12 includes a source connected with a ground voltage Vss. The signal of the node C is applied to a gate of the NMOS transistor N 12 . The fuse F 8 is connected between a drain of the PMOS transistor P 5 and a drain of the NMOS transistor N 12 . The NMOS transistor N 11 includes a source connected with the ground voltage Vss. The column address control signal YFS<1> is applied to a gate of the NMOS transistor N 11 . A drain of the NMOS transistor 11 is connected to a common contact point of the fuse F 8 and the NMOS transistor N 12 . The NMOS transistor N 10 includes a source connected with the ground voltage Vss. A drain of the NMOS transistor N 10 is connected with the gate of the NMOS transistor N 11 . A gate of the NMOS transistor N 10 is connected to the common contact point of the fuse F 8 and the NMOS transistors N 11 and N 12 .

Each of the remaining column address control signal generating units 202 - 207 has a similar structure as the above-described column address control signal generating unit 201 . The column address initializing signal generating unit 208 includes an inverter I 11 for inverting the signal of the node C and an NMOS transistor N 31 including a source connected with the ground voltage Vss. An output signal of the inverter I 11 is applied to a gate of the NMOS transistor N 31 .

In the initializing signal generating unit 240 , the inverter I 12 inverts the column redundancy start signal YREDST. Inverters I 13 and I 14 continuously invert an output signal of the inverter I 12 . The NAND gate ND 3 logically combines the output signal of the inverter I 12 and an output signal of the inverter I 14 . The PMOS transistor P 12 has a source connected to the power voltage Vdd and a drain connected to a drain of the NMOS transistor N 31 in the column address initializing signal generating unit 208 . An output signal of the NAND gate ND 3 is applied to each gate of the PMOS transistor P 12 .

When the column redundancy fuse unit 200 receives the adjacent block selecting signal SELF_PAIRb of a high level, it is necessary to use row repair lines of the block designated by, an block address bit RAT<10>. Thus, the block address bit RAT<10> is inputted to a gate of an NMOS transistor N 6 , and the inverted block address bit RAB<10> is inputted to a gate of an NMOS transistor N 7 . In contrast, if the adjacent block selecting signal SELF_PAIRb is at a low level, it is necessary to use row repair lines of block pair of the block designated by the block address bit RAT<10>. Thus, the inverted block address bit RAB<10> is inputted to the gate of the NMOS transistor N 6 , and the block address bit RAT<10> is inputted to a gate of the NMOS transistor N 7 .

That is, the method for sharing row repair lines between adjacent blocks determines whether or not to automatically exchanges an externally inputted block address bit RAT<10> and an inverted block address bit RAB<10> in the rows active state according to the level of the adjacent block selecting signal SELF_PAIRb. Thereby, even when using row repair lines of the adjacent block, a column defect is detected and thus a defective column is replaced with a column repair line. Accordingly, it is possible to improve the repair efficiency.

Next, the operation of the column redundancy fuse unit 200 will be described in more detail with reference to FIG. 6 .

Fuses F 2 -F 7 of the fuse unit 220 and fuses F 8 -F 14 of the control signal generating unit 230 are cut corresponding to defective block address RAT<9:10> and defective column address BYA<1:7>, respectively. The fuses F 2 , F 4 , F 6 correspond to the block address bit RAT<9>, RAT<10>, RAT<11>, respectively. The fuses F 3 , F 5 , F 7 correspond to the inverted block address bit RAB<9>, RAB<10>, RAB<11>, respectively. The fuses are cut corresponding to each bit of a high level among the defective block address RAT<9:11> and the inverted block address RAB<9:11>. For example, when the block address RAT<9:11> is [010], RAB<9:11> becomes [101]. Thereby, only fuses F 3 , F 4 , F 7 are cut. Also, fuses F 8 -F 14 correspond to the column address bit BYAC<1>-BYAC<7>, respectively. The fuses F 8 -F 14 are cut corresponding to each bit of a low level among defective column address BYAC<1:7>. For example, when the defective column address BYAC<1:7> is [00011111], only fuses F 8 -F 10 are cut.

In a case that SELF_PAIRb is at a low level and the row repair lines of the adjacent block are used, if the externally inputted block address RAT<9:11> is not an adjacent block address of the defective block, at least one of the address bit corresponding to an uncut fuse of the fuse unit 220 is at a high level. Thus, if the column redundant start signal YREDST becomes a high level, any of transistors N 3 -N 9 is turned on. Then, the node B becomes a low level and the node C becomes a high level. As a result, NMOS transistors N 12 , N 13 , N 18 , N 19 , N 24 , N 25 and N 30 are turned on, and NMOS transistors N 10 , N 15 , N 16 , N 21 , N 22 , N 27 and N 28 for discharging the column address control signals YFS<1:7> are turned off. Thus, the column address control signals YFS<1:7> remains a high level of an initial state.

That is, the column address control signal YFS<1:7> remains charged to a high level regardless of whether column address fuses F 8 -F 14 of the control signal generating unit 230 is cut or not. Thus, a NMOS transistor N 31 is turned off because the node C is at a high level. Thus, the initializing signal YFJB of the column address control signal remains a high level of an initial state.

In a case with SELF_PAIRb at a low level and the row repair lines of the adjacent block used, if the externally inputted block address RAT<9:11> is an adjacent block address of the defective block, a gate input of the NMOS transistor connected to the uncut fuse among the NMOS transistors N 4 -N 9 is at a low level, and a gate input of the NMOS transistor connected to the cut fuse is at a high level. Accordingly, even when the column redundant start signal YREDST is at a high level, a discharge path to the NMOS transistor N 3 shown in FIG. 6 is disconnected. As a result, the node B maintains a high level of the initial state, and the node C becomes a low level. At this time, the NMOS transistor N 31 is turned off, and the initializing signal YFJB of the column address control signal is discharged to the ground to be a low level.

In this case, the output of the column address control signal YFS<1:7> is different according to the cut state of column fuses F 8 -F 14 . If the inputted column address BYAC<1:7> is not a column address for column repair, that is, unless an address bit corresponding to an uncut fuse among fuses F 8 -F 14 is an address bit of a high level, a PMOS transistor connected to an uncut fuse among PMOS transistors P 5 -P 11 is turned on. Further, an NMOS transistor connected to the uncut fuse among NMOS transistors N 10 , N 15 , N 16 , N 21 , N 22 , N 27 and N 28 is turned on. Thereby, the column address control signal YFS<i> corresponding to the uncut fuse becomes a low level.

On the contrary, when the inputted column address BYAC<1:7> is a column address for column repair, that is if an address bit corresponding to the cut fuse among the fuses F 8 -F 14 is an address bit of a high level, a NMOS transistor connected to the cut fuse among NMOS transistors N 10 , N 15 , N 16 , N 21 , N 22 , N 27 and N 28 is not turned on. There by, the column address control signal YFS<i> is charged to a high level.

Referring to FIG. 7, the column redundancy decoding unit 300 includes inverters I 15 , I 16 , I 17 , I 18 , and I 19 , PMOS transistors P 13 , P 14 , P 15 , P 16 , and P 17 , NMOS transistors N 33 , N 34 , and N 35 , and NOR gates NR 1 and NR 2 . The inverter I 16 inverts a column address control signal YFS<i>. The PMOS transistor P 13 includes a source connected to a power voltage Vdd and a drain connected a node E. An output signal of the inverter I 16 is applied to a gate of the PMOS transistor P 13 . The inverter I 15 inverts an initializing signal YFJB of the column address control signal. The PMOS transistor P 15 includes a source connected to the power voltage Vdd a drain connected to the node C. An output signal of the inverter I 15 is applied to a gate of the PMOS transistor P 15 . The PMOS transistor P 14 includes a source connected to the power voltage Vdd a drain connected to the node E. The output signal of the inverter I 15 is applied to a gate of the PMOS transistor P 15 . The NOR gate NR 1 logically combines the initializing signal YFJB of the column address control signal and the column address control signal YFS<i>. The NOR gate NR 2 logically combines the initializing signal YFJB of the column address control signal and the output signal of the inverter I 16 . The inverter I 17 inverts an output signal of the NOR gate NR 1 . The inverter I 18 inverts a column address bit BYAC<i>. The PMOS transistors P 16 and P 17 and the NMOS transistors N 33 and N 34 are connected in series between the power voltage Vdd and the ground voltage Vss. An output signal of the inverter I 17 is applied to a gate of the PMOS transistor P 16 . An output signal of the inverter I 18 is applied to each gate of the PMOS transistor P 17 and NMOS transistor and N 33 . The output signal of the NOR gate NR 1 is applied to a gate of the NMOS transistor N 34 . The inverter I 19 inverts an output signal of the NOR gate NR 2 . A transmission gate T 5 transmits the output signal of the inverter I 18 under the control of an output signal of the inverter I 19 and the output signal of the NOR gate NR 2 . The NMOS transistor N 35 includes a source connected to the ground voltage Vss a drain connected to an output terminal of the decoded column address bit YAJ<i>. The initializing signal YFJB of the column address control signal is applied to a gate of the NMOS transistor 35 .

Referring to FIG. 8, the column redundancy determining unit 400 includes NAND gates ND 4 and ND 5 and a NOR gate NR 3 .

In the column redundancy determining unit 400 , the NAND gates ND 4 and ND 5 logically combine the decoded column address YAJ<1:7>. The NOR gate NR 3 logically combines output signals of the NAND gates ND 4 and ND 5 , and outputs a column redundancy signal YREDC.

Referring back to FIG. 6, unless an externally inputted block address RAT<9:11> is an adjacent block address of the defective block, that is, an address corresponding to the cut state of the fuses F 2 , F 5 and F 6 (when fuse is cut, address bit=1, and when fuse is not cut, address bit=0), the node B becomes a low level and the node C becomes a high level. Then, the initializing signal YFJB of the column address control signal having a high level is inputted to the NOR gates NR 1 and NR 2 , and thus, output level of the NOR gate NR 1 and NR 2 become a low level regardless of the level of the column address control signal YFS<i> and the column address bit BYAC<i>. At this time, the NMOS transistor N 35 is turned on and a decoded column address bit YAJ<i> becomes a low level. Next, each bit of the decoded column address YAJ<1:7> is inputted at a low level into the column redundancy determining unit 400 as illustrated in FIG. 8, and thus a column redundancy signal YREDC becomes a low level.

In this case, the column redundancy signal YREDC becomes a low level, and a main column decoder (not shown) is enabled regardless of whether or not the inputted column address BYAC<1:7> is a defective address.

In contrast, if an externally inputted block address RAT<9:11> is an adjacent block address of the defective block, that is, an address corresponding to the cut sate of the fuses F 2 , F 5 and F 6 , the column redundancy start signal YREDST is at a high level. Then, the node B becomes a high level and thus the node C becomes a low level. The initializing signal YFJB of the column address control signal is inputted at a low level to the NOR gates NR 1 and NR 2 . Then, a level of the column address control signal YFS<i> determines whether the output signal of the NOR gate NR 1 is made at a high level or the output signal of the NOR gate NR 2 is made at a high level.

For example, if the externally inputted column address bit BYAC<i> is the defective column address, the fuse corresponding to the column address bit BYAC<i> of a low level among the fuse F 8 -F 14 is cut, and the column address control signal YFS<i> becomes a high level. Then, an output signal of the NOR gate NR 1 becomes a low level, and an output signal of the NOR gate NR 2 becomes a high level. Thereby, the transmission gate T 5 is turned on, and the decoded column address bit YAJ<i> becomes a high level regardless of the on/off of the transistors P 16 , P 17 , N 33 and N 34 .

In contrast, if the fuse corresponding to the column address bit BYAC<i> of a high level among the fuse F 8 -F 14 is not cut, the column address control signal YFS<i> becomes a low level. Then, the output signal of the NOR gate NR 1 becomes a high level and the output signal of the NOR gate NR 2 becomes a low level. Thereby, the transmission gate T 5 and the NMOS transistor N 33 are not turned and PMOS transistor P 16 and P 17 are turned on. Thus, the decoded column address bit YAJ<i> becomes a high level.

That is, if a defective column address corresponding to the cut state of fuses F 8 -F 14 is inputted, the decoded column address bit YAJ<i> becomes a high level regardless of whether the column address bit BYAC<i> is at a low level or a high level. Accordingly, the column redundancy signal YREDC becomes a high level, and thus a repair column decoder (not shown) is enabled. As a result, a defective column is replaced by a column repair line.

Unless an externally inputted column address BYAC<1:7> is a defective column address, YFS<i> corresponding to the column address bit BYAC<i> of a low level becomes a low level, or YFS<i> corresponding to the column address bit BYAC<i> of a high level becomes a high level. That is, BYAC<i> and YFS<i> become at a high level or a low level.

Referring to FIG. 7, when YFJB is at a low level and BYAC<i> and YFS<i> are a high level, transmission gate T 5 is turned on and then YAJ<i> becomes a low level. Also, when YFJB is at a low level and BYAC<i> and YFS<i> are a low level, NMOS transistors N 33 and N 34 are turned on and then YAJ<i> becomes a low level.

Accordingly, referring to FIG. 8, when at least one of YAJ<i> becomes a low level, YREDC becomes a low level except the output signals of NAND gate ND 3 and ND 4 become a low level. That is, unless a defective column address corresponding to the cut state of fuses F 8 -F 14 is inputted, a main column decoder(not shown)is enabled.

As described above, in the repair method for sharing row repair lines of an adjacent block, if an adjacent block selecting signal is at a high level, row repair lines of the block designated by an externally inputted block address are used. If the adjacent block selecting signal is at a low level, row repair lines of an adjacent block are used by inverting an externally inputted block address. Thus, it is possible to improve repair efficiency of a semiconductor memory device by replacing a defective column with a column repair line.

Although certain apparatus constructed in accordance with the teachings of the invention have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all embodiments of the teachings of the invention fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.