Volume circuit using resistive ladder circuits

1. Field of the Invention

This invention relates to volume circuits that use resistive ladder circuits for adjustments of audio signals in volume levels.

2. Description of the Related Art

In the fields of audio devices and technologies, electronic volume circuits for fabricating electronic circuits are conventionally used for adjustments of volumes in audio signals. Japanese patent application No. 2000-28152 (i.e., Japanese Unexamined Patent Publication No. 2001-217660; and U.S. patent application Ser. No. 09/773,646) disclosed an example of an electronic volume circuit that is driven by a single power source and whose components are fabricated together as LSI circuitry.

In the aforementioned electronic volume circuit, the gain (or attenuation) of an input signal is controlled by selecting a tap (or a voltage division point) from series resistance. In particular, when the gain is greatly narrowed down, resistance division points should be extremely reduced in resolutions when selected. Therefore, it is difficult to accurately and sufficiently narrow down the gain of an input signal in a conventional electronic volume circuit.

It is an object of the invention to provide a volume circuit having a high resolution in controlling and narrowing down the gain of an input signal by introducing various improvements in circuit configurations. That is, the volume circuit uses a resistive voltage divider circuit, which can provide a desired tap voltage in a high resolution. In addition, a resistive current control circuit coupled with the resistive voltage divider circuit is designed to eliminate unwanted influences on the output line resistance of the resistive voltage divider circuit.

In a first aspect of the invention, a volume circuit comprises resistive ladder circuits (or resistive networks) and a switch circuit. The resistive ladder circuits provide parallel arrangements of lines of series resistances, which are arranged between terminals IN and OUT, wherein each line has a resistive element realizing a resistance that is ‘n’ (where ‘n’ is an integer not less than ‘2’) times larger than an element resistance ‘R’. Herein, one line having the resistance ‘nR’ is connected in parallel with another line having series resistance that is ‘(n−1)×n’ times greater than the element resistance ‘R’, so that the overall resistance of the following lines in view of one line having the resistance ‘nR’ is equal to ‘(n−1)×nR’. The switch circuit operates to extract a ‘desired’ fraction of the overall voltage applied to the resistive ladder circuits via a desired tap selected from among taps that are linearly arranged with respect to the resistive ladder circuits.

Specifically, each line contains a first resistive element that is not at all connected in parallel with a next line, and a second resistive element that is connected in parallel with a certain resistive element of the next line. Various taps are arranged along the first resistive element of each line, so that numerous taps are linearly arranged along different lines of resistive ladder circuits. Therefore, the switch circuit selects a desired tap from among these taps so as to extract a desired fraction of the overall voltage applied to the resistive ladder circuits as a fractional voltage output. In addition, the second resistive element of each line is connected in parallel with a part of the next line in connection with the ‘common’ terminal OUT. As described above, numerous resistive elements are connected in series and parallel with each other within the resistive ladder circuits, wherein each of them is actualized by various units of the element resistance ‘R’.

An amplifier is used to amplify a fractional voltage output that is extracted from the resistive ladder circuits by the switch circuit. All the aforementioned components (i.e., the resistive elements, switch circuit, and amplifier) are fabricated together on the semiconductor substrate or board.

In a second aspect of the invention, a volume circuit comprises combinations of resistive ladder circuits and amplifiers. That is, the first unit of resistive ladder circuits are actualized by multiple lines of series resistances arranged between terminals IN and OUT, wherein each line is connected in parallel with a part of the next line in connection with the ‘common’ terminal OUT. The fractional voltage output extracted from the resistive ladder circuits is supplied to the amplifier, which in turn provides an amplified output to the terminal OUT. In addition, an input terminal of a secondary amplifier is connected to the terminal OUT, and the second unit of resistive ladder circuits is inserted between the terminal OUT and the output terminal of the secondary amplifier.

The second unit of resistive ladder circuits is actualized by multiple lines of resistive elements, wherein all or a part of resistive elements of one line is connected in parallel with the next line in connection with the ‘common’ terminal OUT. Specifically, the second unit of resistive ladder circuits provides substantially the symmetrical circuit configuration compared with the first unit of resistive ladder circuits with respect to the terminal OUT.

In the resistive ladder circuits, each line has a resistance that is ‘n’ times larger than the element resistance ‘R’ and is connected in parallel with the next line. The total resistance of the following line(s) in view of one line having the resistance ‘nR’ is ‘(n−1)×n’ times greater than the element resistance ‘R’. All the aforementioned components (i.e., the resistive ladder circuits and amplifiers) are fabricated together on the semiconductor substrate or board.

These and other objects, aspects, and embodiments of the present invention will be described in more detail with reference to the following drawing figures, in which:

FIG. 1 is a circuit diagram showing the overall configuration of an electronic volume circuit in accordance with a first embodiment of the invention;

FIG. 2 is a circuit diagram showing electric connections between resitive ladder circuits and a switch circuit shown in FIG. 1 ;

FIG. 3A shows an example of a circuit configuration forming a simple resistive ladder circuit;

FIG. 3B shows an equivalent circuit of the resistive ladder circuit shown in FIG. 3A ;

FIG. 4A shows an original single resistor circuit that is subjected to expansion;

FIG. 4B shows a parallel circuit that is expanded based on the single resistor circuit shown in FIG. 4A ;

FIG. 4C shows a resistor ladder circuit that is expanded based on the parallel circuit shown in FIG. 4B ;

FIG. 5A shows an expanded form of the resistive ladder circuit that is expanded based on the resistive ladder circuit shown in FIG. 4C ;

FIG. 5B shows a complex form of the resistive ladder circuit that is further expanded based on the resistive ladder circuit shown in FIG. 5A ;

FIG. 6 shows a concrete example of resistive ladder circuits R 1 shown in FIGS. 1 and 2 ;

FIG. 7A shows a terminal portion of the resistive ladder circuits R 1 in the side of the terminal IN;

FIG. 7B shows a terminal portion of the resistive ladder circuits R 1 in the side of the terminal OUT;

FIG. 8 shows an example of the arrangement and wiring of element resistors for actualizing the resistive ladder circuits shown in FIG. 6 ;

FIG. 9 is a circuit diagram showing an overall configuration of an electronic volume circuit in accordance with a second embodiment of the invention;

FIG. 10A shows a terminal portion of resistive ladder circuits R 1 and R 2 shown in FIG. 9 , which are used to explain influences due to wiring resistances;

FIG. 10B shows a terminal portion of resistive ladder circuits R 1 and R 2 , which are modified to cancel influences due to wiring resistances;

FIG. 11 shows an example of the overall layout of an LSI circuit realizing the electronic volume circuit of the second embodiment; and

FIG. 12 shows a concrete example of the resistive ladder circuits R 1 and R 2 that are connected in series.

This invention will be described in further detail by way of examples with reference to the accompanying drawings.

First Embodiment

FIG. 1 shows the overall configuration of an electronic volume circuit in accordance with the first embodiment of the invention. The volume circuit of FIG. 1 contains an LSI circuit ‘B1’ (encompassed by dotted lines), which provides a voltage divider realized by resistive ladder circuits R 1 , a switch circuit SW, an inversion-type operation amplifier A 1 that operates by a single source voltage +Vp 1 , a series of resistors R 31 , R 32 , and R 33 that are connected in series with a constant voltage source in order to gain a reference potential, and a series of resistors R 34 and R 35 that are used to output signals.

The LSI circuit B 1 has two input terminals T 1 and T 2 , and four output terminals T 3 to T 6 . A capacitor C 1 for cutting out dc current flowing therethrough is connected to the input terminal T 1 ; and a capacitor C 2 for stabilizing the input of the LSI circuit B 1 is connected to the input terminal T 2 . Hence, an input signal source Si is connected between the input terminals T 1 and T 2 of the LSI circuit B 1 via the capacitors C 1 and C 2 , wherein it is grounded with one terminal of the capacitor C 2 (see the earth ‘E1’). A differential operational amplifier A 3 that operates by bidirectional source voltages +Vp 2 and −Vp 2 is arranged externally of the LSI circuit B 1 , wherein the inverting input (−) terminal is connected to the output terminal T 4 , and the noninverting input (+) terminal is connected to the output terminal T 5 . In addition, a load RL is connected between the output terminal of the differential operational amplifier A 3 and the output terminal T 6 , wherein the output terminal T 6 is grounded (see the earth ‘E2’).

The input signal source Si provides an input signal voltage Vi (corresponding to ac signal components only), which is applied between the input terminals T 1 and T 2 of the LSI circuit B 1 via the capacitors C 1 and C 2 . In the LSI circuit B 1 , one terminal IN of the resistive ladder circuits R 1 is connected to the input terminal T 1 , and the other terminal OUT is connected with the output terminal of the operational amplifier A 1 . FIG. 1 shows an equivalent circuit (i.e., series resistance) of the resistive ladder circuits R 1 . Actually, the resistive ladder circuits R 1 comprise multiple lines of series resistances between the terminals IN and OUT. The switch circuit SW selects one of numerous taps (or voltage division points) that are linearly arranged along the resistive ladder circuits R 1 .

FIG. 2 shows the relationships between the resistive ladder circuits R 1 and the switch circuit SW, and it shows an equivalent circuit (i.e., series resistance) of the resistive ladder circuits R 1 . The resistive ladder circuits R 1 have numerous taps, the number of which is denoted by ‘M’. The switch circuit SW contains numerous switching elements ‘Sm’ (where ‘m’ denotes the tap or switch number, and m=1, 2, 3, . . . , M−1, M), which are inserted between the taps and the line used for the extraction of a fractional voltage output ‘s’. The switch circuit SW also has a decoder D for controlling the switching elements Sm respectively. Volume control data Sv given from the external circuit (not shown) are supplied to control terminals of the decoder D. That is, a specific switching element Sm is turned on in response to the value ‘m’ of the volume control data Sv, so that the voltage of the tap corresponding to the specific switching element Sm is output as the fractional voltage output ‘s’.

The fractional voltage output ‘s’ that is provided from the tap selected by the switch circuit SW is supplied to the inverting input terminal of the operational amplifier A 1 . The resistive ladder circuits R 1 operate in such a way that a specific potential Vs corresponding to the fractional voltage output s is set to a value ranging between potentials Vin and Vout at the terminals IN and OUT when the specific switching element Sm is turned on in response to the volume control data Sv. Herein, a specific division ratio ‘ks’ for ‘Vs−Vout’ (i.e., a voltage difference measured between the fractional voltage output s and the terminal OUT) against ‘Vin−Vout’ (i.e., a voltage difference measured between the terminals IN and OUT) is given by the following equation (1).

ks = Vs - Vout Vin - Vout ( 1 )

Therefore, the ratio for ‘Vs−Vout’ against ‘Vin−Vs’ (i.e., a voltage difference measured between the terminal IN and the divided voltage output s) is given by the following equation (2).

The input terminal T 2 and the noninverting input terminal of the operational amplifier A 1 are connected to the connection point between the resistors R 31 and R 32 that are connected in series. The other end of the resistor R 31 is supplied with a source potential +Vp 1 , which corresponds to the aforementioned source voltage supplied to the operational amplifier A 1 . The other end of the resistor R 32 is connected to the output terminal T 6 , which is grounded (see the earth ‘E2’), via the resistor R 33 . The potential Vt 2 of the input terminal T 2 is given by the equation (3), wherein reference symbols Ra, Rb, and Rc designate resistances of the resistors R 31 , R 32 , and R 33 respectively.

Vt2 = ( + Vp ) × Rb + Rc Ra + Rb + Rc ( 3 ) Ra=Rb+Rc   (4)

If the relationship between Ra, Rb, and Rc is defined by the equation (4), the potential Vt 2 can be retained at the ‘constant’ reference potential, which approximately corresponds to half of the source voltage +Vp 1 of the operational amplifier A 1 .

With respect to the input voltage Vi supplied from the input signal source Si, the output voltage Vout output from the operational amplifier A 1 is given by the equation (5).

The output of the operational amplifier A 1 is connected to the output terminal T 3 via the resistors R 34 and R 35 that are connected in series. The connection point between the resistors R 34 and R 35 is connected to the output terminal T 4 . Herein, the resistances of the resistors R 34 and R 35 are respectively set to Rb and Rc, which also designate resistances of the resistors R 32 and R 33 . With respect to the maximal division ratio ksmax (i.e., the division ratio that is given when the switching element S 1 , providing the maximal level, is turned on in response to the volume control data Sv), it is preferable to provide the following relationship of the equation (6) for the resistances Rb and Rc.

The connection point between the resistors R 32 and R 33 is connected to the output terminal T 5 . It is retained at a certain voltage Vt 5 that depends upon the resistances Ra, Rb, and Rc as well as the aforementioned voltage +Vp, which is applied to the series circuit consisting of the resistors R 31 , R 32 , and R 33 , in accordance with the following equation (7).

The operational amplifier A 3 operates based on the bidirectional source voltages +Vp 2 and −Vp 2 , which realize the maximal amplitude of the input signal Si. With respect to the connections between the operational amplifier A 3 and the LSI circuit B 1 shown in FIG. 1 , the output of the operational amplifier A 3 is connected to the output terminal T 3 , and the inverting input terminal is connected to the output terminal T 4 .

Both the resistors R 32 and R 34 have the same resistance Rb, while both the resistors R 33 and R 35 have the same resistance Rc, wherein these resistances are related to each other by the following ratio K 3 .

The operational amplifier A 3 outputs at the output terminal T 3 a load voltage Vo for the load RL, which is expressed by the following equation.

Vo=−K 3×( V out− Vt 2)  (9)

Next, concrete examples of numeric values for the aforementioned circuit configurations shown in FIGS. 1 and 2 will be described. The input signal Si is an audio signal that varies in amplitude in the maximal range of ±12V, for example. The comprehensive equivalent resistance of the resistive ladder circuits R 1 between the terminals IN and OUT is approximately 12 kΩ. In FIG. 2 , the volume control data Sv consist of eight bits, which express volume control levels in M=256 steps. These volume control levels can be expressed as the gain G by using the prescribed interval (e.g., 0.5 dB) therebetween, so that they are expressed as −16 dB, −16.5 dB, −17 dB, . . . , −143.5 dB, −∞ (mute), for example. In correspondence with these volume control levels, there are provided M=256 switching elements S 1 , S 2 , . . . , S 255 (SM- 1 ), and S 256 (SM) as well as their taps. The gain G (dB) is expressed by the following equation.

G

=

Therefore, a desired tap of the resistive ladder circuits R 1 is selected by turning on the ‘desired’ switching element Sm in response to the level of the volume control data Sv, so that the potential of the selected tap is extracted as the fractional voltage output s. For example, when the volume control data Sv that chooses the level ‘256’ realizing the maximal volume is input, the decoder D turns on the switching element S 256 (SM) of the switch circuit SW, so that the terminal OUT of the resistive ladder circuits R 1 provides the fractional voltage output s.

When the source voltage +Vp 1 of the operational amplifier A 1 is +5V, it can be said that the series circuit consisting of the resistors R 31 , R 32 , and R 33 is connected between the voltage source of +5V (or +Vp 1 ) and the earth (E 2 ), wherein their resistances are selected such that Ra=11.59 kΩ. Rb=1.59 kΩ, and Rc=10 kΩ. In this case, the noninverting input terminal of the operational amplifier A 1 (corresponding to the input terminal T 2 ) is retained at a certain reference potential Vt 2 =+2.5V.

Suppose that the fractional voltage output s is supplied from the terminal OUT of the resistive ladder circuits R 1 by way of the 256th switching element S 256 (SM) wherein the gain G is set to −∞. In this case, the division ratio is minimized as ks=ksmin=0, so that the operational amplifier A 1 provides the output voltage Vout=Vt 2 =2.5V. Suppose that the fractional voltage output s is supplied from the tap corresponding to the first level realizing the maximal gain by turning on the first switching element S 1 , wherein the gain G is set to −16 dB. In this case, the division ratio is maximized as ks=ksmax=0.137, so that the operational amplifier A 1 provides the output voltage Vout as follows:

V out= Vt 2 +0.159 Vi=+ 2.5V+0.159 Vi

In the above, even though the input voltage Vi is varied in the maximal range of ±12V, it is possible to maintain the positive polarity in the output of the operational amplifier A 1 .

When Ra=11.59 kΩ, Rb=1.59 kΩ, and Rc=10 kΩ, the connection point (corresponding to the output terminal T 5 ) between the resistors R 32 and R 33 is retained at a certain voltage Vt 5 =2.16V.

In correspondence with the input voltage Vi that is varied in the maximal range of ±12V, the bidirectional source voltages +Vp 2 and −Vp 2 applied to the operational amplifier A 3 are respectively set to +12V and −12V. When the 256th switching element S 256 is turned on by setting the minimal gain G=−∞ (where the division ratio is minimized as ks=ksmin=0), the operational amplifier A 3 provides the load voltage Vo=0V. When the first switching element S 1 is turned on by setting the maximal gain G=−16 dB (where the division ratio is maximized as ks=ksmax=0.137), the following equations are established.

K3 = Rc Rb = 6.29 V out= Vt 2−0.159 ×Vi

Hence, the operational amplifier A 3 provides the load voltage Vo in accordance with the foregoing equation (9).

Vo=− 6.29×(−0.159 ×Vi )  (10)

In FIG. 2 , the resistive ladder circuits R 1 is a series circuit consisting of resistors r 1 , r 2 , r 3 , . . . , rM−1, and rM, wherein their connection points act as taps which are respectively connected with the switching elements S 1 , S 2 , S 3 , . . . , SM−1, and SM, each of which can be selected in providing the fractional voltage output s. In the case of M=256, it is possible to set the resistors r 1 to rM to prescribed resistance values, which will be described below.

Suppose that the gain G is subjected to fine adjustment using the prescribed interval of 0.5 dB, for example, by precisely controlling the switching element S 1 to SM. In this case, resistances should be sequentially reduced in order as r 1 =10365Ω, r 2 =80Ω, r 3 =76.7Ω, and r 4 =73.4Ω. In addition, in proximity to the minimal gain G, resistances should be extremely reduced as follows:

R 253 (rM- 3 )=53.4 μΩ (−142.5 dB) R 254 (rM- 2 )=50.4 μΩ (−143 dB) R 255 (rM- 1 )=47.6 μΩ (−143.5 dB) R 256 (rM)=0.850 mΩ (−∞)

In general, a sheet resistance ranging from several ohms to several hundreds ohms can be precisely obtained by using the polysilicon or polyside for the LSI circuit. However, it may be unrealistic to form the resistive ladder circuits R 1 using serial connections of resistors.

Next, the principle of the formation of a circuit configuration of a resistive ladder circuit will be described with reference to FIGS. 3A and 3B . This invention employs resistive ladder circuits using parallel connections of resistances, thus realizing fine divisions of resistances for use in fine adjustment of the volume.

For convenience' sake, the same symbol ‘R’ is used to designate the resistance of an element resistor; and ‘n’ designates a division index that is a natural number not less than ‘2’. Hence, ‘nR’ denotes a resistance that is ‘n’ times larger than the resistance ‘R’ of the element resistor. FIG. 3A shows a parallel circuit in which a resistance ‘nR’ is connected in parallel with series resistances realized by ‘n−1’ series of the resistance ‘nR’ (hereinafter, simply referred to as resistance series ‘(n−1)×nR’). FIG. 3B shows an equivalent circuit of the parallel circuit shown in FIG. 3A , which is a simple resistance circuit having a resistance ‘(n−1)R’.

In other words, the comprehensive resistance (n−1)R that is assumed to be connected between terminals IN and OUT shown in FIG. 3B can be expanded in the form of a parallel circuit consisting of the resistance nR and the series resistances ‘(n−1)×nR’ between terminals IN and OUT shown in FIG. 3A . Due to such expansion of the circuit configuration, it is possible to realize the comprehensive resistance (n−1)R while providing ‘n’ fine divisions of the overall voltage by the series resistances (n−1)×nR between the terminals IN and OUT. That is, it is possible to provide ‘n’ times smaller voltages compared with the overall voltage of the simple resistance (n−1)R shown in FIG. 3B . It is possible to provide further fine divisions of resistances by further dividing resistances with respect to an arbitrary number (<n) of series resistances ‘(n−1)R’ arranged in the side of the terminal OUT within the series resistances (n−1)×nR, wherein a certain number of resistances remain without being further divided in the side of the terminal IN. By repeatedly performing the aforementioned resistance dividing operations a certain number of times, the resistive ladder circuits can be further expanded in a complex circuit configuration, which may provide further smaller divisions of voltages in proximity to the terminal OUT.

Suppose that the division index n is set to ‘3’ while the comprehensive resistance is set to ‘2R’, so that an original resistance circuit whose resistance is ‘2R’ is subjected to expansion. The original resistance circuit is expanded by the aforementioned resistance dividing operation to produce a resistive ladder circuit in which a series of two resistances ‘3R’ (simply referred to as a series resistance ‘6R’) are connected in parallel with a resistance ‘3R’. Using the series resistance 6R, it is possible to provide three times smaller divisions of voltages compared with the overall voltage of the original resistance circuit having the resistance 2R. In the above, it is possible to provide a series of three resistances ‘2R’, which are substituted for the series of two resistances ‘3R’ in the resistive ladder circuit. In this case, two resistances 2R remain in the side of the terminal IN, while a resistance dividing operation is further performed with respect to one resistance 2R arranged in the side of the terminal OUT. By repeatedly performing this operation a certain number of times, it is possible to further expand the resistive ladder circuit in a complex circuit configuration.

Resistive ladder circuits are repeatedly expanded to ones, which will be described with reference to FIGS. 4A to 4C , and FIGS. 5A and 5B . Herein, the division index n is set to ‘4’, and an original resistance circuit having a resistance ‘3R’ shown in FIG. 4A is subjected to expansion. That is, a first resistance dividing operation is performed to produce a parallel circuit in which a series of three resistances ‘4R’ (namely, a series resistance ‘12R’) are connected in parallel with a resistance ‘3R’, wherein the overall resistance of the parallel circuit is set to ‘3R’. The aforementioned series resistance 12R can be modified as shown in FIG. 4B , wherein a resistance ‘6R’ arranged in the side of the terminal IN is connected in series with two resistances ‘3R’ arranged in the side of the terminal OUT.

In FIG. 4B , the resistance 6R remains without being expanded while a second resistance dividing operation is performed with respect to the two resistances 3R respectively. Thus, it is possible to produce a resistive ladder circuit shown in FIG. 4C , wherein a resistance 3R is expanded in the form of a parallel circuit consisting of a resistance ‘4R’ and a resistance ‘12R’, while the other is expanded in the form of a parallel circuit in which a resistance ‘4R’ is connected in parallel with a series resistance consisting of a resistance ‘6R’ and two resistances ‘3R’. Then, a third resistance dividing operation is performed with respect to the two resistances 3R arranged in the side of the terminal OUT. Thus, it is possible to produce a ‘complex’ resistive ladder circuit shown in FIG. 5A . By performing the aforementioned resistance dividing operation a certain number of times, it is possible to finally produce a ‘further complex’ resistive ladder circuit shown in FIG. 5B . In such a resistive ladder circuit, it is possible to use a relatively large value of resistance (which may range from one-hundred and several tens of ohms to several hundreds ohms) as each of resistances formed between adjoining taps. Therefore, it is possible to provide fine divisions of the volume gain with a sufficiently high precision.

FIG. 6 shows an example of the detailed circuit configuration of the resistive ladder circuits R 1 (see FIGS. 1 and 2 ) realized by numerous resistance elements arranged in the electronic volume circuit of the first embodiment. FIG. 7A shows a detailed circuit configuration of the resistive ladder circuit in proximity to the terminal IN; and FIG. 7B shows a detailed circuit configuration of the resistive ladder circuit in proximity to the terminal OUT. Similarly to FIGS. 4A-4C and FIGS. 5A-5B , the resistive ladder circuits R 1 shown in FIG. 6 are produced under the precondition where the division index n is set to ‘4’, and the element resistance R is set to 632Ω, so that the overall resistance of the resistive ladder circuits R 1 between the terminals IN and OUT is equal to 19R (=12.008 kΩ).

The resistive ladder circuits of FIG. 6 is constituted by twelve lines of series resistances, wherein resistances 10R, 6R, and 4R are connected in series in the first line; a resistance 6R and two resistances 4R are connected in series in the second line; a resistance 12R, a resistance 6R, and two resistances 4R are connected in series in the third line; . . . ; two resistors 12R are connected in series in the twelfth line. Taps are arranged along the resistance 6R in the second line, resistances 12R and resistances 6R in the third to eleventh lines, and two resistors 12R in the twelfth line, respectively. These taps are connected with ‘256’ switching elements S 1 -S 256 respectively. The switching elements are selectively turned on in response to the volume control data Sv, which designates each of ‘256’ steps of the gain divided by the prescribed interval of 0.5 dB, wherein the maximal gain is set to −16 dB. Therefore, the gain is counted from the maximal gain and can be reduced by each interval. The fractional voltage output s is provided at the tap selected by the switching element that is turned on in response to the volume control data Sv.

The resistive ladder circuit includes k lines of series resistances due to dividing performed a prescribed number of times. The resistive ladder circuit of FIG. 6 is constituted of twelve lines of series resistances, where k=12. In accordance with the principles of resistive ladders, the expansion of the resistive circuit network, and FIGS. 3 to 5 , the first line of series resistances includes a resistance nR where n=4, and the resistance nR is connected in parallel with second to twelfth lines of series resistances, the equivalent resistance of which is n(n−1)R where n=4. In addition, the second line of series resistances includes a resistance nR where n=4, and the resistance nR is connected in parallel with the third to twelfth lines of series resistances, the equivalent resistance of which is n(n−1)R where n=4. Similarly, each of the third, fourth, fifth, . . . , and eleventh lines of series resistances includes a resistance nR where n=4, and the resistance nR is connected in parallel with its following lines, the equivalent resistance of which is n(n−1)R where n=4.

Concrete examples of components of the resistive ladder circuits R 1 in the side of the terminal IN will be described with reference to FIG. 7A . The terminal IN is connected with a series of resistances 10R, 6R, and 4R in the first line of the resistive ladder circuits R 1 , wherein the total resistance of these resistances is set to 10.112 kΩ. A resistance 6R of the second line branches out from a connection point ‘A’ between the resistances 6R and 4R, so that it is connected in parallel with the resistance 4R of the first line. The resistance 6R of the second line is connected with plural switching elements S 1 , S 2 , S 3 , S 4 , . . . That is, the resistance 6R is divided into plural tap resistances re 1 , re 2 , re 3 , re 4 , re 5 , . . . , which will be described below.

re 1 : 1012.9Ω [between the connection point A and the switching element S 1 (−16 dB)] re 2 : 319.7Ω [between the switching elements S 1 -S 2 (−16.5 dB)] re 3 : 306.4Ω [between the switching elements S 2 -S 3 (−17 dB)] re 4 : 293.4Ω [between the switching elements S 3 -S 4 (−17.5 dB)] re 5 : 280.8Ω [between the switching elements S 4 -S 5 (−18 dB)]

Concretely speaking, the resistance 6R of the second line is connected with eleven switching elements S 1 -S 11 , wherein tap resistance re 11 between the switching elements S 10 -S 11 is set to 212.8Ω. In addition, resistance re 12 ′ that lies between the switching element S 11 and a connection point between the resistance 6R and its adjacent resistance 4R in the second line is 138.6Ω. A resistance 12R of the third line branches out from the connection point B between the resistances 6R and 4R of the second line, wherein it is connected in series with a resistance 6R in the third line. In the third line, the resistance 12R is connected with switching elements S 12 -S 24 , and the resistance 6R is connected with switching elements S 25 -S 36 . Resistance re 12 ″ that lies between the connection point B and the switching element S 12 is 257Ω, and tap resistance re 13 that lies between the switching elements S 12 -S 13 is 772.7Ω. Similar to the first line, the other tap resistances (i.e., re 14 , re 15 , . . . ) in the third line are gradually reduced.

Similar to the third line, the fourth to eleventh lines each contain a series of resistances 12R and 6R, detailed description of which will be omitted. In summary, each of the resistances 6R and/or the resistances 12R in the second to twelfth lines can be limited in certain tap resistances, which range from one-hundred and several tens of ohms to several hundreds of ohms.

Concrete examples of components of the resistive ladder circuits R 1 in the side of the terminal OUT will be described with reference to FIG. 7B . The 256th switching element S 256 is connected with the terminal OUT of the resistive ladder circuits R 1 . The twelfth line of the resistive ladder circuits R 1 consists of two resistances 12R, along which plural taps are arranged and are respectively connected with switching elements S 255 , S 254 , S 253 , . . . , which are counted from the side of the terminal OUT. That is, the resistance 12R is divided into plural tap resistances re 256 , re 255 , re 254 , re 253 , . . . , which will be described below.

re 256 : 1470Ω [between the switching elements S 256 (−∞) and S 255 (−143.5 dB)] re 255 : 199.5Ω [between the switching elements S 255 -S 254 (−143 dB)] re 254 : 211.3Ω [between the switching elements S 254 -S 253 (−142.5 dB)] re 253 : 223.8Ω [between the switching elements S 253 -S 252 (−142 dB)]

In the above, tap resistances range from one-hundred and several tens of ohms to several hundreds ohms; therefore, it is possible to obtain a desired volume gain with a high precision. FIG. 8 shows an example of the arrangement and wiring of element resistors, which are connected together in the form of resistive ladder circuits. The arrangement and wiring of element resistors are actualized under the condition where the division index n is set to ‘4’, which have been described before in conjunction with FIGS. 4A-4C , FIGS. 5A-5B , FIG. 6 , and FIGS. 7A-7B . Numerous element resistors ‘R’ (where R=632Ω) are formed in polysilicon resistive films on the LSI circuit board (B 1 ), wherein they are regularly arranged in four lines and are adequately connected together by leads to implement a part of the wiring shown in FIG. 6 . Arrangements of element resistors are divided into various units (encompassed by dotted lines), each of which realizes a certain resistance value. For example, the leftmost unit of element resistors connected together by leads realizes a resistance ‘10R’, and its next unit of element resistors realizes a resistance ‘6R’. Therefore, various units of element resistors are arranged to realize various resistance values such as 10R, 6R, 4R, and 12R. Taps (designated by dots in FIG. 6 ) are arranged with respect to the prescribed units of element resistors realizing the resistances ‘6R’ and ‘12R’. These taps are interconnected with switching elements of the switch circuit SW via leads (not shown). Since the resistive ladder circuits R 1 are actualized by arranging and connecting element resistors R, they can be easily manufactured.

Second Embodiment

FIG. 9 shows the overall configuration of an electronic volume circuit in accordance with a second embodiment of the invention, wherein parts and components identical to those shown in FIG. 1 will be designated by the same reference symbols and numerals. The electronic volume circuit of the second embodiment shown in FIG. 9 provides an LSI circuit B 2 that contains secondary resistive ladder circuits R 2 and a secondary inversion-type operational amplifier A 2 , which operates by the source voltage +Vp 1 , in addition to the resistive ladder circuits R 1 and the operation amplifier A 1 . Due to the provision of the secondary resistive ladder circuits R 2 and the secondary operation amplifier A 2 , the LSI circuit B 2 additionally provides current control functions and wiring resistance cancellation functions compared with the LSI circuit B 1 shown in FIG. 1 . FIG. 9 merely shows an equivalent circuit for representation of series connections between the resistive ladder circuits R 1 and R 2 . The resistive ladder circuits R 1 and R 2 (encompassed in a block as if two resistors are connected in series) have a terminal IN that matches an input terminal of the resistive ladder circuits R 1 , and an terminal OUT that matches a connection point between the resistive ladder circuits R 1 and R 2 . In addition, the fractional voltage output s is extracted from the resistive ladder circuits R 1 via a certain tap and is supplied to the inverting input terminal of the operational amplifier A 1 . With respect to the operational amplifier A 2 , the inverting input terminal corresponds to a certain point of the resistive ladder circuits R 1 ; the noninverting input terminal corresponds to the connection point between the resistive ladder circuits R 1 and R 2 ; and the output terminal corresponds to the other end ‘r’ of the resistive ladder circuits R 2 . In the case where n=4, the total resistance of the resistive ladder circuits R 1 (lying between IN and q) is 12.008 kΩ, and the total resistance of the resistive ladder circuits R 2 (lying between q and r) is 200Ω.

In the above, a gain α of the operational amplifier A 2 is given by the following equation using reference symbols Rpq and Rqr, where ‘Rpq’ denotes a partial resistance of the resistive ladder circuits R 1 between p and q, and ‘Rqr’ denotes the overall resistance of the resistive ladder circuits R 2 between q and r.

α = Rqr Rpq ( 11 )

With respect to a current i 1 that flows from the input terminal T 1 into the resistive ladder circuits R 1 , a voltage Vpq measured between p and q is given by the following equation.

Vpq=i 1× Rpq   (12)

With respect to a current i 2 that flows into the output terminal of the operational amplifier A 2 through the resistive ladder circuits R 2 , a voltage Vrq measured between r and q is given by the following equation.

Vrq=−i 2× Rqr   (13)

The output voltage of the operational amplifier A 2 matches the voltage Vrq measured between r and q, and it is calculated using the equation (11) as follows:

Vrq = - α × Vpq = - ( Rqr Rpq ) × Vpq ( 14 )

Through the aforementioned equations (12) to (14), it is possible to produce the following relationship.

- i2 × Rqr = - ( Rqr Rpq ) × i1 × Rpq

That is, it is possible to set the relationship of ‘i 2 =i 1 ’.

In other words, the current i 1 flowing from the input terminal T 1 is forced to match with the current i 2 that may flow towards the output terminal of the operational amplifier A 2 . Thus, it is possible to perform feed-forward current controls in such a way that most of the current flowing into the input terminal T 1 is substantially absorbed by the operational amplifier A 2 . This prevents unwanted currents from flowing into the operational amplifier A 1 ; therefore, it is possible to realize high-precision volume level controls by using the operational amplifier A 1 .

Next, a description will be given with respect to wiring resistance cancellation functions of the LSI circuit B 2 shown in FIG. 9 . Suppose that the aforementioned resistive ladder circuits R 1 provide a fractional voltage output s that is specifically used for volume level controls. It may be understood from the illustration of FIG. 8 that relatively long lines should be wired between output terminals (t 1 -t 12 ) of respective lines of resistive ladder circuits R 1 and the terminal OUT. This causes wiring resistances Rm that may not be negligible.

Next, a description will be given with respect to influences of wiring resistances Rm in the resistive ladder circuits R 1 (see FIG. 6 ) providing the fractional voltage output s. Herein, it is possible to provide a solution as shown in FIG. 10A in which the output terminal t 1 of the first line of the resistive ladder circuits R 1 is connected to the output terminal of the operational amplifier (A 2 ) via a current absorption control resistance R 2 ′. However, this solution may cause a problem in that potential differences occur between adjoining output terminals (i.e., t 1 -t 2 , t 2 -t 3 , t 3 -t 4 , . . . ) due to wiring resistances Rm therebetween. Potential differences may badly influence the gain of the operational amplifier A 1 . When the wiring resistance Rm is relatively large, the electronic volume circuit may be incapable of accurately limiting the gain thereof down to the ‘desired’ minimal gain (e.g., −143 dB).

The second embodiment is characterized by reconstructing the resistive ladder circuits R 2 as shown in FIG. 10B , wherein the resistive ladder circuits R 2 can provide current control functions as well as wiring resistance cancellation functions. That is, the output terminals t 1 , t 2 , t 3 , . . . of the resistive ladder circuits R 1 that may provide the fractional voltage output s are respectively connected with cancellation resistors Rx, which are followed by other cancellation resistors Ry. These resistors Rx and Ry are adequately set in resistances to provide the same potential with respect to each of the output terminals t 1 , t 2 , t 3 , . . . of the resistive ladder circuits R 1 . The circuitry of FIG. 10B is partially modified using equivalent circuits compared with the circuitry of FIG. 10A in such a way that each parallel circuit consisting of resistances 4R and 12R is replaced by a resistance 3R.

The details of the circuitry of FIG. 10B will be described under the condition where n=4. Due to the current control (or absorption) function of the operational amplifier A 2 , the current i 1 input from the input terminal T 1 is forced to match with the current i 2 that flows into the output terminal of the operational amplifier A 2 , wherein i 1 =i 2 . When each of the output terminals t 1 , t 2 , t 3 , . . . is set to the same potential, no current may flow through the wiring resistance Rm, which is established between adjoining terminals (i.e., t 1 -t 2 , t 2 -t 3 , t 3 -t 4 , . . . ). Hence, terminal currents ia 1 , ia 2 , ia 3 , . . . that flow through the output terminals t 1 , t 2 , t 3 , . . . directly flow through the cancellation resistors Rx, which are connected to the output terminals t 1 , t 2 , t 3 , with respect to the respective lines of the resistive ladder circuits R 1 .

With respect to the second line, a series of resistances 6R and 9 R (i.e., series resistance ‘9R’ in total) derive from a connection point A in the first line. With respect to the third line, a series of resistances 6R and 3R (i.e., series resistance ‘9R’ in total) derive from a connection point B in the second line. Similarly, series resistance ‘9R’ in the fourth line (not shown) derives from a connection point E in the third line. That is, each of following lines contains series resistance ‘9R’ that derives from each of preceding lines. Shunt currents ib 1 , ib 2 , ib 3 , . . . are forced to flow through the series resistances ‘9R’ in the respective lines of the resistive ladder circuits R 1 , wherein they are identical to currents that flow through the cancellation resistors Ry in the resistive ladder circuits R 2 . Ratios between terminal currents and shunt currents, i.e., ia 1 /ib 1 , ia 2 /ib 2 , ia 3 /ib 3 , . . . , are all equal to ‘3’. Generally speaking, the ratio between the terminal current and shunt current is expressed as ‘n−1’ (where ‘n’ denotes the division index).

With respect to the first and second lines of the resistive ladder circuits, for example, the following equations are established.

ia 1=3× ib 1  ( a )

4 R×ia 1=9 R×ib 1+4 R×ia 2  ( b )

Rx×ia 1= Rx×ia 2+ Ry×ib 1  ( c )

From the equations (a) and (b), it is possible to produce the following equation.

ia 1=4× ia 2  ( d )

Hence, it is possible to produce the following equation based on the equations (a), (c), and (d).

It may be obvious by the comparison between the left and right portions of the circuitry of FIG. 10B that the resistive ladder circuits R 2 have the symmetrical circuit configuration compared with the resistive ladder circuits R 1 with respect to the output terminals t 1 -t 12 and the terminal OUT. Due to such symmetry, it is possible to provide the same potential with respect to each of the output terminals t 1 -t 12 and the terminal OUT; hence, it is possible to cancel influences of wiring resistances Rm, regardless of their values.

Due to the aforementioned symmetry, it is possible to easily determine circuit constants and parameters with respect to the resistive ladder circuits R 2 , which may realize the overall resistance ‘R2e’, for example. That is, in the case of the circuitry of FIG. 10B where n=4, the element resistance R is determined as follows:

R = R2e n - 1 = R2e 3

When R 2 e=200Ω, the element resistance R is calculated as follows:

R = R2e 3 = 200 3 = 66.7 ⁢ ⁢ Ω

Hence, the cancellation resistances Rx and Ry can be calculated as follows:

Rx=n×R= 4×66.7Ω=266.7Ω Ry=Rx× 4/9=200×3=600Ω

As described before in conjunction with FIGS. 3A-3B , FIGS. 4A-4C , FIGS. 5A-5B , and FIG. 6 , the comprehensive equivalent resistance of the following lines in view of the cancellation resistance Rx in each line can be calculated as follows:

n ×( n− 1)× R= 4×3× R 2 e/ 3=800Ω

With respect to the output terminal of the last line (i.e., terminal t 12 of the twelfth line shown in FIG. 6 ), the foregoing resistance dividing operation would no longer be required. As shown in FIG. 12 , a series of resistances Rx and Ryo are inserted in connection with the other end of the cancellation resistance Rx in the eleventh line, wherein the resistance Ryo is calculated as follows:

Ryo= 800Ω−266.7Ω−533.3Ω

In summary, in the case of the circuitry of FIG. 10B where n=4, it is possible to provide the following equations with respect to the resistive ladder circuit R 2 having the overall resistance R 2 e (where ‘Ryo’ and ‘12R’ are shown in FIG. 12 ).

Rx

Ry

=

FIG. 11 shows an example of the overall layout of an LSI circuit representing the electronic volume circuit of the second embodiment. FIG. 12 shows an example of the overall configuration of the resistive ladder circuits R 1 and R 2 that are connected in series in accordance with the second embodiment. Herein, the configuration of the resistive ladder circuits R 1 is designed under the same conditions for use in the design of the first embodiment.

Next, the overall operation of the electronic volume circuit of the second embodiment will be briefly described in conjunction with FIG. 12 . That is, the input signal voltage Vi input to the terminal IN is converted to the voltage Vout having an amplitude that substantially matches the fractional voltage output s extracted from the prescribed tap of the resistive ladder circuits R 1 under the operation of the first amplifier (or attenuator) A 1 , so that the voltage Vout is output to the terminal OUT. In FIG. 12 , a resistance 4R is arranged in each of second to eleventh lines of resistive ladder circuits R 1 that lie between the terminals IN and OUT (see FIG. 9 ). Herein, the resistance 4R in one line is connected in parallel with the resistance 12R in the next line. The equivalent resistance viewed from both ends of the resistance 4R in each line is made equal to 3R, which is the original resistance of the series circuit. Herein, resistance values are adjusted in such a way that they become larger as the number of line becomes larger. Hence, it is possible to provide the ‘desired’ fractional voltage output with a high resolution.

The secondary resistive ladder circuits R 2 are introduced to control the second amplifier A 2 that operates to absorb the current flowing into the resistive ladder circuits R 1 , wherein the secondary resistive ladder circuits R 2 are constituted symmetrically with the resistive ladder circuits R 1 . This provides the same potential with respect to all the output terminals t 1 to t 12 of the resistive ladder circuits R 1 ; hence, it is possible to eliminate unwanted influences due to wiring resistances Rm, which are formed between adjoining output terminals within the output terminals t 1 to t 12 . That is, the second embodiment introduces the resistive ladder circuits R 1 for use in the extraction of the fractional voltage output, and the resistive ladder circuits R 2 for use in current controls. Thus, it is possible to provide an electronic volume circuit having a high resolution in fine adjustments of the volume.

As described heretofore, this invention provides a variety of effects and technical features, which will be described below.

(1) The volume circuit of this invention is designed such that the fractional voltage output Vs is extracted from the prescribed tap of the resistive ladder circuits R 1 by the switch circuit SW. The resistive ladder circuits R 1 are constituted by multiple lines of series resistances, wherein numerous element resistors are connected in series and in parallel between the terminals IN and OUT. Each line is connected in parallel with a series resistance that is ‘n’ times larger than the element resistance ‘R’, so that the comprehensive overall resistance of the following lines is increased ‘(n−1)×n’ times larger than the element resistance ‘R’. (2) The total equivalent resistance in view of the resistance ‘nR’ in one line becomes ‘(n−1)’ times larger than the element resistance ‘R’. Therefore, the second line of the resistive ladder circuits arranges taps among series resistances ‘n(n−1)R’ that are ‘n’ times larger than the original overall resistance ‘(n−1)R’. Thus, it is possible to provide ‘desired’ fractional voltage output with a very high precision, which is ‘n’ times greater than that of the first line. In addition, the third line arranges taps with a very high precision (or resolution), which is ‘n’ times greater than that of the second line. That is, this invention can increase the precision (or resolution) in providing the fractional voltage output (or in selecting the prescribed tap) exponentially as the number of lines of resistive ladder circuits becomes large. (3) The volume circuit of this invention can introduce combinations of resistive ladder circuits and amplifiers, wherein the resistive ladder circuits R 1 are specifically used for providing the fractional voltage output, and the other resistive ladder circuits R 2 are used to control currents flowing in the resistive ladder circuits R 1 . The resistive ladder circuits R 1 have multiple lines of series resistances between the terminals IN and OUT, wherein one line is partially connected in parallel with the next line in connection with the ‘common’ terminal OUT. The fractional voltage Vs extracted from the resistive ladder circuits R 1 is input to the first amplifier A 1 , the output terminal of which is connected to the terminal OUT. The input terminal ‘q’ of the second amplifier A 2 is connected to the terminal OUT. In addition, the resistive ladder circuits R 2 are inserted between the terminal OUT and the output terminal ‘r’ of the second amplifier A 2 . (4) Due to the provision of the second amplifier A 2 and the resistive ladder circuits R 2 , the current that flows from the terminal IN into the resistive ladder circuits R 1 is absorbed by the output terminal of the second amplifier A 2 . In addition, the resistive ladder circuits R 2 perform current controls in such a way that the output terminals t 1 -t 12 of the resistive ladder circuits R 1 are all set to the same potential, which prevents the current from flowing between wires interconnecting the output terminals t 1 -t 12 together. Thus, it is possible to eliminate unwanted influences due to wiring resistances Rm, which emerge between adjoining output terminals.

As this invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, the present embodiments are therefore illustrative and not restrictive, since the scope of the invention is defined by the appended claims rather than by the description preceding them, and all changes that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.