Gain-boost nulling amplifier for auto-zero circuit

The invention relates to a method and circuit for reducing noise and charge injection errors and improving DC precision in auto-zeroed circuits.

In nulling amplifiers of auto-zero circuits such as the one shown in FIGS. 1A and 1B, low input-referred noise is achieved by maximizing the transconductance (gm) ratio of a pair of main input transistors to that of a pair of nulling transistors. The gm of the pair of main input transistors is limited by their physical size and by current consumption limitations of the auto-zero circuit and the nulling amplifier thereof. The gm ratio of the pair of main input transistors to that of the nulling pair of transistors may be maximized by decreasing the gm of the nulling pair, but if the gm of the nulling pair is decreased too much, the DC precision of the nulling amplifier and the DC precision of the auto-zeroed amplifier circuit is worsened by gain error effects in the nulling amplifier. In the past, certain limitations of the ratio of the gm of the pair of main input transistors pair to the gm of the nulling pair of transistors for auto-zeroed amplifiers have been accepted as a fundamental design constraint. Specifically, because of constraints on the quiescent current consumption of integrated circuit chips containing auto-zeroed amplifiers, it has been commonly accepted that the ratio of the gm of the pair of main input transistors to the gm of the nulling pair of transistors should be roughly 10. It has been commonly accepted that a larger ratio would result in unacceptably large chip size and power consumption.

Thus, there is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit. There also is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.

There also is an unmet need for an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit without substantially increasing quiescent current consumption, and/or cost of the auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.

Accordingly, it is an object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit.

It is another object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit while maintaining a low value of the corrected input offset voltage of the nulling amplifier.

It is another object of the invention to provide an improved way of reducing the input-referred noise of the nulling amplifier of an auto-zeroed amplifier circuit without substantially increasing power dissipation, size, and/or cost of the auto-zeroed amplifier circuit while maintaining a low input offset voltage of the nulling amplifier.

Briefly described, and in accordance with one embodiment thereof, the invention provides a nulling amplifier ( 52 A) for an auto-zeroed amplifier that includes a first differential stage including first ( 3 ) and second ( 16 ) input transistors and a second differential stage including first ( 18 ) and second ( 19 ) nulling transistors coupled to drains of the first and second input transistors and to a folded cascode circuit ( 48 ) coupled to an output stage ( 59 ). A gain boost circuit controls the output resistance of the auto-zeroed amplifier. The gm ratios of the first and second input transistors and the first and second nulling transistors have values which establish a predetermined low input-referred noise level in the nulling amplifier, and the gain boost circuit provides high gain resulting in low gain error and thereby allows the offset voltage of the nulling amplifier to be reduced.

In the described embodiment, a nulling amplifier ( 52 A) includes a first differential stage including first ( 3 ) and second ( 16 ) input transistors and a first tail current source ( 38 ) coupled to sources of the first and second input transistors. A switching circuit ( 50 ) selectively couples a gate of the second input transistor ( 16 ) to either a first input signal (V in+ ) or to a gate of the first input transistor ( 3 ) in response to a control signal (φ), a second input signal (V in− ) being coupled to the gate of the first input transistor. The second differential stage includes first ( 18 ) and second ( 19 ) nulling transistors, a second tail current source ( 39 ) being coupled to sources of the first and second nulling transistors, a drain of the first nulling transistor being coupled to the drain of the second input transistor, a drain of the second nulling transistor being coupled to the drain of the first input transistor. A first hold capacitor (C 3 ) is coupled between a gate of the first nulling transistor and a first reference voltage, and a second hold capacitor (C 4 ) is coupled between a gate of the second nulling transistor and the first reference voltage. First ( 69 A) and second ( 69 B) switches couple the gates of the first and second nulling transistors to receive first (V out− ) and second(V out+ ) output signals coupled to an output stage ( 59 ) in response to the control signal (φ).

A folded cascode circuit ( 48 ) has an input coupled to the drains of the first ( 3 ) and second ( 16 ) input transistors and an output coupled to the input of the output stage ( 59 ). The folded cascode circuit ( 48 ) includes a first low side constant current source transistor ( 7 ) having a drain coupled to the drain of the second input transistor ( 16 ) and to a source of a first cascode transistor ( 8 ), and a second low side constant current source transistor ( 41 ) having a drain coupled to the drain of the first input transistor ( 3 ) and to a source of a second cascode transistor ( 9 ). The gain boost amplifier circuitry ( 113 , 117 ) includes a low side gain boost amplifier ( 113 ) including a first gain boost amplifier output transistor ( 11 ) coupling the drain of the first low side constant current source transistor ( 7 ) to the source of the first cascode transistor ( 8 ) and a second gain boost amplifier output transistor ( 10 ) coupling the drain of the second low side constant current source transistor ( 41 ) to the source of the second cascode transistor ( 9 ).

The folded cascode circuit ( 48 ) also includes a first high side constant current source transistor ( 4 ) having a drain coupled to the drain of the first cascode transistor ( 8 ), and a second high side constant current source transistor ( 20 ) having a drain coupled to the drain of the second cascode transistor ( 9 ).

The gain boost amplifier circuitry ( 113 , 117 ) also includes a high side gain boost amplifier ( 117 ) including a third gain boost amplifier output transistor ( 1 ) coupling the drain of the first high side constant current source transistor ( 4 ) to the drain of the first cascode transistor ( 8 ) and a fourth gain boost amplifier output transistor ( 2 ) coupling the drain of the second high side constant current source transistor ( 20 ) to the drain of the second cascode transistor ( 9 ).

The low side gain boost amplifier ( 113 ) includes a first feedback input (FBI) coupled to the drain of the first low side constant current source transistor ( 7 ) and a second feedback input (FB 2 ) coupled to the drain of the second low side constant current source transistor ( 41 ). The high side gain boost amplifier ( 117 ) includes a first feedback input (FB 1 ) coupled to the drain of the second high side constant current source transistor ( 20 ) and a second feedback input (FB 2 ) coupled to the drain of the first high side constant current source transistor ( 4 ).

A common mode feedback circuit ( 47 ) is coupled to the first and second switches and the first ( 4 ) and second ( 20 ) high side constant current source transistors to produce a common mode level of the first (V out− ) and second (V out+ ) output signals.

FIGS. 1A and 1B are block diagrams of two operating configurations of the same conventional auto-zeroed amplifier circuit.

FIGS. 2-1 and 2 - 2 constitute a schematic diagram of one of the nulling amplifiers included in FIG. 1 .

FIG. 3 is a schematic diagram of the high side gain boost amplifier 117 of FIG. 2-1.

FIG. 4 is a schematic diagram of the low side gain boost amplifier 113 of FIG. 2-1.

FIG. 5 is a schematic diagram of the analog summing circuit and output stage of FIG. 1 A.

FIG. 6 is a timing diagram useful in describing the operation of the circuitry of FIGS. 1A, 1 B, and 2 - 4 .

Referring to FIGS. 1A and 1B, auto-zeroed amplifier 51 includes two nulling amplifiers 52 and 60 , a feed-forward amplifier 65 , an analog summing circuit 58 , and an output stage 59 . A differential input voltage V in =V in+ −V in− is selectively applied between the (+) and (−) inputs of nulling amplifiers 52 and 60 and feed-forward amplifier 65 . The (+) input of nulling amplifier 52 is connected by a single pole, double throw switch 53 to either Vin+ or the (−) input of nulling amplifier 52 . Similarly, the (+) input of nulling amplifier 60 is connected by a single pole, double throw switch 61 to either Vin+ or the (−) input of nulling amplifier 60 . Output stage 59 may include summing circuit 58 .

Switch 53 is connected to V in+ such that the input voltage V in is applied between the (+) and (−) inputs of nulling amplifier 52 when φ 2 and φ 3 are both high. Switch 53 short-circuits the (+) and (−) inputs of nulling amplifier 52 when φ 2 and φ 3 are both low. The output of nulling amplifier 52 is connected by conductor 55 to one terminal of a switch 56 and to one terminal of a switch 54 . The other terminal of switch 54 is connected to an additional (−) input of nulling amplifier 52 and to one terminal of a hold capacitor C 52 . The other terminal of switch 56 is connected by conductor 57 to a first input of analog summing circuitry 58 . Switch 54 connects hold capacitor C 52 and the additional (−) input of nulling amplifier 52 to conductor 55 only when φ 1 is low. Switch 56 connects conductor 55 to conductor 57 only when φ 3 is high. The waveforms of φ 1 , φ 2 , and φ 3 and their logical complements are shown in FIG. 6 .

Similarly, switch 61 is connected to V in+ such that the input voltage V in is applied between the (+) and (−) inputs of nulling amplifier 60 when φ 1 and φ 2 are both low. Switch 61 short-circuits the (+) and (−) inputs of nulling amplifier 60 when φ 1 and φ 2 are both high. The output of nulling amplifier 60 is connected by conductor 62 to one terminal of a switch 63 and to one terminal of a switch 64 . The other terminal of switch 64 is connected to an additional (−) input of nulling amplifier 60 and to one terminal of a hold capacitor C 60 . The other terminal of switch 63 is connected by conductor 57 to the first input of analog summing circuitry 58 . Switch 64 connects hold capacitor C 60 and the additional (−) input of nulling amplifier 60 to conductor 62 only when φ 3 is high. Switch 63 connects conductor 62 to conductor 57 only when φ 1 is low.

A second input of analog summing circuit 58 is connected to the output 66 of feed-forward amplifier 65 . Thus, the output of nulling amplifier 52 or nulling amplifier 60 and the output of feed-forward amplifier 65 are summed by a summing circuit 58 , which functions as an input circuit of output stage 59 of auto-zeroed amplifier 51 to produce an output voltage V out1 on conductor 68 .

FIG. 1A shows auto-zeroed amplifier 51 with switch 53 connecting the (+) input of nulling amplifier 52 to V in+ , switch 56 closed, and switch 54 open, so that V in is applied between the (+) and (−) inputs of nulling amplifier 52 . Therefore, V in is amplified by the gain of nulling amplifier 52 and applied by conductor 57 to the first input of summing circuit 58 . The voltage being held on capacitor C 52 compensates for the input offset voltage of nulling amplifier 52 . Also, switch 61 short-circuits the (+) and (−) inputs of nulling amplifier 60 , switch 64 is closed, and switch 63 is open. This causes a correction voltage to be stored on capacitor C 60 , which in effect cancels the offset voltage of nulling amplifier 60 . V in also is amplified by the gain of feed-forward amplifier 65 and applied to the second input of summing circuit 58 . The output of summing circuit 58 is amplified by output stage 59 to produce V out1 on conductor 68 . As a practical matter, summing circuit 58 is incorporated in the input circuitry of output stage 59 in a conventional manner, as shown in subsequently described FIG. 5 .

Similarly, FIG. 1B shows auto-zeroed amplifier 51 with switch 61 connecting the (+) input of nulling amplifier 60 to V in+ , switch 63 closed, and switch 64 open, so that V in is applied between the (+) and (−) inputs of nulling amplifier 60 . Therefore, V in is amplified by the gain of nulling amplifier 60 and applied by conductor 57 to the first input of summing circuit 58 . The voltage being held on capacitor C 60 compensates for the input offset voltage of nulling amplifier 60 . Also, switch 53 short-circuits the (+) and (−) inputs of nulling amplifier 52 , switch 54 is closed, and switch 56 is open. This causes another correction voltage to be stored on capacitor C 52 , which in effect cancels the offset voltage of nulling amplifier 52 . V in is also amplified by the gain of feed-forward amplifier 65 and applied to the second input of summing circuit 58 . The output of summing circuit 58 is amplified by output stage 59 to produce V out1 on conductor 68 .

Thus, nulling amplifiers 52 and 60 , one at a time, amplify V in and compensate it for the input offset voltage of one nulling amplifier while the other nulling amplifier samples and stores an updated value of the appropriate correction voltage. Also, V in is constantly amplified by feed-forward amplifier 65 and applied to the second input of summing circuit 58 in order to provide a “continuous-time” path from V in to V out1 despite the switching of nulling amplifiers 52 and 60 and also to provide overall stability of the auto-zero amplifier 51 . The DC gain of each of nulling amplifiers 52 and 60 is much greater than the DC gain of feed-forward amplifier 65 .

It should be understood that the various signals, for example, the signal V out on conductor 57 and the signal V out1 on conductor 68 , can be differential signals. For example, the differential signal V out can be V out =V out+ −V out− where V out+ and V out− are as indicated in subsequently described FIGS. 2-1 and 2 - 2 . As another example, the signal on the nulling input terminal, i.e., the (−) input terminal, of nulling amplifier 52 can be considered to be a single-ended representation of the differential voltage between the gates of transistors 18 and 19 in FIG. 2-1.

FIGS. 2-1 and 2 - 2 show a detailed schematic diagram of an improved nulling amplifier 52 A which can be used in place of each of nulling amplifiers 52 and 60 in FIG. 1 . For simplicity, the input switches 53 and 61 in FIG. 1A are represented by multiplexor 50 in FIGS. 2-1 and 2 - 2 , and the clock signals φ 1 , φ 2 , and φ 3 and their logical complements are as previously described with reference to FIG. 1A, but in FIGS. 2-1 and 2 - 2 they are collectively represented by φ and {overscore (φ)}, respectively. Thus, by way of definition, the term “signal φ” as used herein is intended to encompass either a single clock signal, such as φ 3 , or a group of clock signals, such as φ 1 and φ 2 in combination as previously described with reference to FIG. 1A; the term “signal φ” is intended to be interpreted similarly. For example, nulling amplifier 52 A in FIG. 1A is implemented by nulling amplifier 52 A of FIGS. 2-1 and 2 - 2 with φ connected as shown, and nulling amplifier 60 of FIG. 1A is implemented by nulling amplifier 52 A with φ replaced by {overscore (φ)}. In FIG. 2-1, switches 69 A and 69 B represent either switch 54 or switch 64 in FIG. 1 B.

V in+ is connected to one input of multiplexer circuit 50 , which has a second input connected to V in− . Depending on the state of multiplexer input selection signals φ, the gate of P-channel transistor 16 is connected either to V in+ or to the gate of P-channel transistor 3 . Transistors 3 and 16 constitute a “main differential pair”, and may have their drains connected to diode-connected N-channel voltage clamp transistors 21 and 22 , respectively, although diode-connected voltage clamp transistors 21 and 22 can be omitted in some cases. The sources of transistors 21 and 22 are to connected ground. The sources of transistors 3 and 16 are connected to the drain of a cascode P-channel transistor 17 having its gate connected to a bias voltage V REF1 and having its source connected to the drain of a P-channel current mirror transistor 38 . The source of transistor 38 is connected to a supply voltage V+.

The drains of transistors 3 and 16 also are connected to the drains of P-channel transistors 19 and 18 , respectively, which constitute a “nulling pair”. The gate of transistor 18 is connected to one terminal of a hold capacitor C 3 having another terminal connected to ground. The gate of transistor 18 also is connected to one terminal of a switch 69 A which is controlled by φ, which represents φ 1 for nulling amplifier 52 or φ 3 for nulling amplifier 60 . The gate of transistor 19 is connected to one terminal of a hold capacitor C 4 and to one terminal of a switch 69 B which also is controlled by φ. The other terminal of capacitor C 4 is connected to ground. Another hold capacitor C 5 is connected between the gates of transistors 18 and 19 to increase the total hold capacitor capacitance. The sources of transistors 18 and 19 are connected to the drain of a P-channel current source transistor 39 having its source connected to V+ and its gate connected to the gate of transistor 38 and also to the gate and drain of a P-channel transistor 40 having its source connected to V+. The drain of transistor 40 is connected to the drain of a N-channel current mirror transistor 34 having its source connected to ground and its gate connected to V REF2 and to the gates of N-channel current mirror transistors 28 , 27 , 23 , 7 , 41 , 14 and 24 each having its source connected to ground. The drain of transistor 23 also is connected to V REF2 .

The other terminal of switch 69 A is connected to an output voltage V out− on conductor 57 A, and the other terminal of switch 69 B is connected to a voltage V out+ on conductor 57 B, so switch 56 of FIG. 1 A and switch 63 of FIG. 1A would be used to selectively couple V out+ and V out− of each nulling amplifier to V out of FIG. 1A. V out− is coupled by conductor 57 A to the gate of a P-channel transistor 45 having its source connected to the source of a P-channel transistor 5 and to the drain of a P-channel current mirror transistor 35 having its source connected to V+. V out+ is coupled by conductor 57 B to the gate of a P-channel transistor 33 having its drain connected to ground and to the drain of transistor 45 . The source of transistor 33 is connected to the source of transistor 45 . The gate of transistor 5 is connected to a reference voltage V REF3 . The drain of transistor 5 is connected to the drain and gate of a P-channel current mirror transistor 37 having its source connected to V+. The drain of transistor 5 also is connected to the drain of an N-channel cascode transistor 12 having its gate connected to V REF4 . The source of transistor 12 is connected to the drain of current mirror transistor 14 . The gate of transistor 37 is connected to the gates of P-channel current mirror transistors 4 and 20 , each of which has its source connected to V+. The drain of current mirror transistor 4 is connected to the feedback input FB 2 of a “high side” gain boost amplifier 117 and to the source of a P-channel transistor 1 having its gate connected to the drive output DR 2 of gain boost amplifier 117 . Similarly, the drain of current mirror transistor 20 is connected to the feedback input FBI of high side gain boost amplifier 117 and to the source of a P-channel transistor 2 having its gate connected to the drive output DR 1 of high side gain boost amplifier 117 . Transistors 1 and 2 can be considered to be output transistors or drive transistors of high side gain boost amplifier 117 .

The drain of transistor 1 is connected to the drain of an N-channel cascode transistor 8 having its source connected to the drain of an N-channel transistor 11 . The gate of transistor 11 is connected to the drive output DR 1 of a “low side” gain boost amplifier 113 . The source of 20 transistor 11 is connected to a feedback output FBI of low side gain boost amplifier 113 , to the drain of current mirror transistor 7 , and to the gate and drain of transistor 22 . Similarly, the drain of transistor 2 is connected to the drain of an N-channel cascode transistor 9 having its gate connected to the gate of cascode transistor 8 and its source connected to the drain of an N-channel transistor 10 . The gate of transistor 10 is connected to the drive output DR 2 of low side gain boost amplifier 113 , and the source of transistor 10 is connected to a feedback input FB 2 of low side gain boost amplifier 113 , to the drain of current mirror transistor 41 , and to the gate and drain of transistor 21 . The gates of cascode transistors 8 and 9 are connected to the gate and drain of an N-channel transistor 30 having its source connected to the gate and drain of an N-channel transistor 29 having its source connected to ground. The gate and drain of transistor 30 also are connected to the drain of a P-channel current mirror transistor 6 having its gate connected to the gates of P-channel current mirror transistors 35 and 25 . The sources of current mirror transistors 35 , 6 and 25 are connected to V+. The gate and drain of transistor 25 are connected to the drain of current mirror transistor 24 .

In FIGS. 2-1 and 2 - 2 , transistors 7 and 41 are “low side” constant current sources for a folded cascode stage. Transistors 33 , 45 , 5 , 12 , 14 , 37 , 4 and 20 constitute a common mode feedback circuit 47 . The drain of transistor 7 is connected to the gate and drain of transistor 22 , and the drain of transistor 41 is connected to the gate and drain of transistor 21 . The source voltages of transistors 33 and 45 are produced in response to V out+ and V out− and are approximately equal to the common mode voltage of signals V out+ and V out− plus the average of the V GS voltage of transistors 33 and 45 . The source voltage of transistors 33 and 45 controls cascode transistor 5 by changing the current flowing therein. That changes the amount of current required to flow through current mirror transistor 37 in order to satisfy a constant current source represented by current mirror transistor 14 . That changes how hard current source transistors 4 and 20 are driven and thereby adjusts the common mode output voltage of V out+ and V out− so that it matches V REF3 .

In accordance with the present invention, variations are produced in the drain voltages of low side constant current source transistors 7 and 41 , and these variations are applied to feedback inputs of low side gain boost amplifier 113 and amplified to drive the gate electrodes of transistors 11 and 10 , respectively. Corresponding variations also are produced on the drain of high side current mirror transistors 4 and 20 , and high side gain boost amplifier 117 is provided to receive the feedback signals from the drains of high side current mirror transistors 4 and 20 and amplify them to drive the gate electrodes of transistors 1 and 2 , the drains of which are connected to V out− conductor 57 A and V out+ conductor 57 B, respectively. The amplified V out+ and V out− signals are selectively fed back to the gate electrodes of nulling transistors 19 and 18 , respectively. The result is an increase in the effective impedances at the circuit nodes 57 B and 57 A conducting V out+ and V out− , respectively. Note that the equivalent differential output impedance at V out− conductor 57 A and V out+ conductor 57 B can depend heavily on either one or both of high side gain boost amplifier 117 and low side gain boost amplifier 113 .

It should be appreciated that the gm ratio of input transistors 3 and 16 to the gm ratio of nulling transistors 18 and 19 is determined mainly by the physical sizes of those transistors and the amounts of current through them. Increasing the gm ratio by increasing the physical sizes of input transistors 3 and 16 increases the integrated circuit chip size and hence its cost, and also increases the size and cost of the package in which the integrated circuit chip is to be packaged. That in turn increases the amount of printed circuit board area required, and so on. Also, it should be appreciated that increasing of the gm ratio can be accomplished by increasing the tail current for input transistors 3 and 16 , but this undesirably increases the power dissipation of the nulling amplifier.

However, in accordance with the present invention, when the gates of transistors 3 and 16 are short-circuited together, switches 69 A and 69 B are closed, so the output voltage V out =V out+ −V out− is fed back to and applied between the gates of nulling input transistors 18 and 19 . V out+ and V out− are driven fairly close together so that they satisfy the gain from the nulling input transistors 18 and 19 to the output of nulling amplifier 52 A in a feedback loop. Therefore, the input offset voltage of the pair of main input transistors 3 and 16 is corrected to a degree that depends on the gain from nulling input transistors 18 and 19 to the output of nulling amplifier 52 A.

The following equation represents V out1 as a function of the gain Av 1 of the main differential input stage including input transistors 3 and 16 , the offset voltage Vos 1 of that differential input stage, the gain Av 2 of the differential nulling stage including nulling transistors 18 and 19 , and the offset voltage Vos 2 of the differential nulling stage. Av 1 is the open loop gain from the main differential input transistors 3 and 16 to the output of the nulling amplifier, and Av 2 is the open loop gain from the nulling differential input to the output of the nulling amplifier. Vout1 = Av1 × Vos1 + Av2 × Vos2 1 + Av2 (Equation  1)

Dividing both sides of Equation 1 by Av 1 shows the residual offset voltage referred to the input of the differential input stage including transistors 3 and 16 . Vos = Vout1 Av1 = Vos1 1 + Av2 + ( Av2 Av1 ) × ( Vos2 1 + Av2 ) (Equation  2)

As shown in Equation 2, there is a division factor (1+Av 2 ) in the mathematical expression for the residual offset of nulling amplifier 52 A. In order to reduce gain error in the correction of the offset of transistors 3 and 16 , the forward gain Av 2 should be as high as possible. The Av 2 /Av 1 ratio is independent of the amount of gain boost, so Equation 2 shows that increasing the open loop gain Av 2 by adding gain boost lowers the input-referenced offset voltage V OS =V out1 /Av 1 . In addition, providing gain boost allows Av 2 /Av 1 to be fixed while Av 2 is increased. Lowering Av 2 /Av 1 and increasing Av 2 results in a lower V OS =V out1 /Av 1 of the nulling amplifier.

The gain from nulling transistors 18 and 19 to the output V out+ −V out− between conductors 57 B and 57 A of nulling amplifier 52 A is dependent on the gm of nulling of transistors 18 and 19 . However, to obtain good noise performance and low input offset voltage, the gm of nulling transistors 18 and 19 should be very low. The gain from nulling transistors 18 and 19 to the output V out+ −V out− is proportional to the gm of nulling transistors 18 and 19 . As the gm of nulling transistors 18 and 19 is reduced, the amount of residual error shown by Equation 2 also is increased. The gain from nulling transistors 18 and 19 to the output V out =V out+ −V out− also is proportional to the output resistance of the cascode section 48 of nulling amplifier 52 A. The gain boost circuitry functions by increasing the output resistance and therefore helps to increase the gain of the nulling amplifiers.

The above equations refer to the residual offset of the nulling amplifiers. The following equations describe the overall offset of the auto-zeroed amplifier and show the effect of the offset of the nulling amplifiers on the overall offset of the auto-zeroed amplifier.

For V in =0, i.e., with the (+) and (−) inputs of the one of the nulling amplifiers 52 or 60 which is operatively connected to summing circuit 58 short circuited together, the output voltage of the auto-zeroed amplifier 51 of FIG. 1A is given by

V out1 =Avn×Vosn+Avf×Vosf,   (Equation 3)

where

Avn is the open loop gain from the input of the nulling amplifier to the output of the entire auto-zeroed amplifier,

Vosn is the residual input offset voltage of whichever one of nulling amplifiers 52 and 60 is operatively connected to summing circuit 58 ,

Avf is the open loop gain from the input of feed-forward amplifier 65 to the output of the entire auto-zeroed amplifier, and

Vosf is the input offset voltage of feed-forward amplifier 65 .

The referring of this output voltage to the input of the auto-zeroed amplifier 51 is represented by Vos = Vout1 Avn + Avf = Vosn     Avn Avn + Avf + Vosf     Avf Avn + Avf . (Equation  4)

However, auto-zeroed amplifier 51 is designed so that Avn is much greater than Avf. Therefore, the input-referred offset voltage of auto-zeroed amplifier 51 is represented by Vos ≈ Vosn + Vosf     Avf Avn ≈ Vosn . (Equation  5)

Thus, the offset voltage of auto-zeroed amplifier 51 is dominated by the offset voltages of nulling amplifiers 52 and 60 .

In accordance with the present invention, providing the high side gain boost amplifier 117 and the low side gain boost amplifier 113 connected as shown in FIGS. 2-1 and 2 - 2 increases the equivalent output resistance at circuit nodes 57 A and 57 B so that the product of gm multiplied by the equivalent output resistance is high even though the gm of nulling transistors 18 and 19 is reduced as much as possible to minimize noise referred to the input. Consequently, the amount of gain error in the feedback loop is minimized so that the offset voltage remains low.

Referring to FIG. 3, “high side” gain boost amplifier 117 includes two amplifier stages connected to establish the source voltage of both transistors 1 and 2 in FIGS. 2-1 and 2 - 2 and compare those source voltages to a reference voltage that is internally derived within gain boost amplifier 117 . The gates of N-channel transistors 82 and 83 of the first stage are connected to the feedback terminals FB 1 and FB 2 of high side gain boost amplifier 117 . Transistors 82 and 83 are connected differentially with respect to a reference voltage established on the gate of N-channel transistor 80 by a reference current source I REF and circuitry including transistors 70 , 71 , 76 , 77 , 78 and 79 . Feedback from the sources of transistors 1 and 2 (see FIGS. 2-1 and 2 - 2 ) establishes the voltages on terminals FB 2 and FB 1 , respectively, and forces them to be nearly equal to the reference voltage established on the gate of transistor 80 . The currents through the drains of transistors 82 and 83 modulate the currents that are routed to flow through P-channel cascode transistors 85 and 90 . The gates of cascode transistors 85 and 90 are connected to receive a reference voltage V REF5 . The drains of cascode transistors 85 and 90 are connected to the DR 1 and DR 2 terminals, respectively, of high side gain boost amplifier 117 .

The differences between the drains currents of transistors 80 , 82 , and 83 and the drain currents of transistors 72 , 73 and 74 , respectively, are folded into cascode transistors 84 , 85 and 90 , which produce the high output impedance/resistance of the output of the folded cascode stage. Current source transistors 87 , 89 and 92 provide loads for cascode transistors 84 , 85 and 90 , respectively. The current drive into transistor 87 of gain boost amplifier 117 is mirrored to the current in transistors 89 and 92 in order to establish the voltages on terminals DR 1 and DR 2 , which drive transistors 1 and 2 of FIG. 2-1. Since transistors 1 and 2 of FIG. 2-1 have relatively constant drain currents, the voltages of their sources follow their drain voltages. Therefore, as the source voltages of transistors 1 and 2 move in response to the signals on terminals DR 1 and DR 2 of gain boost amplifier 117 , the source voltages of transistors 1 and 2 provide feedback to the FB 1 and FB 2 terminals of gain boost amplifier 117 . Since the feedback terminals FB 1 and FB 2 are connected to the gates of transistors 82 and 83 , respectively, the voltages of the gates of transistors 82 and 83 are forced by the feedback to be equal the reference voltage established on the gate of transistor 80 , which is set at a specified voltage below V+. Additionally, as the voltages of the gates of transistors 82 and 83 move with respect to one another, they force the voltages of terminals DR 1 and DR 2 to move so as to keep the voltages of terminals FB 1 and FB 2 nearly equal. This function provides high differential output impedance of V out+ conductor 57 B and V out− conductor 57 A.

Low side gain boost amplifier 113 of FIG. 4 is shown for completeness. However, it is very similar in both structure and operation to high side gain boost amplifier 117 , and therefore is not described in detail.

The way that the auto zeroed-circuit operates is that one of the two nulling amplifiers is in the configuration shown in FIG. 1 A and the other is in the configuration shown in FIG. 1B, or vice versa, wherein one nulling amplifier drives the output of the auto-zeroed amplifier when the other operates in a configuration with its inputs shorted together. The two nulling amplifiers alternately swap configurations, so there is always a continuous signal path from V in is applied to the output V out− The two nulling amplifiers therefore operate to correct their own offsets and the offset of the entire auto-zeroed amplifier.

FIG. 5 shows a simplified practical differential implementation 51 A of the auto-zeroed amplifier 51 of FIG. 1A, wherein the hold capacitors and associated switches shown in FIG. 1A are omitted for convenience. The (+) and (−) outputs of nulling amplifier 52 are coupled by switches 56 - 1 and 56 - 2 to conductors 57 - 1 and 57 - 2 , respectively. The (+) and (−) outputs of nulling amplifier 60 are connected by switches 63 - 1 and 63 - 2 to conductors 57 - 1 and 57 - 2 , respectively. Switches 56 - 1 and 56 - 2 are controlled by φ 3 , and switches 63 - 1 and 63 - 2 a controlled by {overscore (φ)} 1 . Conductor 57 - 1 conducts V outp and is connected to the gate of a P-channel transistor 95 , which has its source connected to a constant tail current source. Conductor 57 - 2 conducts V outn and is connected to the gate of the P-channel transistor 94 which has its source connected to the source of transistor 95 . The drain of transistor 94 is connected to the common sources of P-channel transistors 96 A and 96 B, wherein the channel-width-to-channel-length ratio of transistor 96 A is 3 times (or any other suitable factor) that of transistor 96 B. Similarly, the drain of transistor 95 is connected to the common sources of P-channel transistors 97 A and 97 B, wherein the channel-width-to-channel-length ratio of transistor 97 B is 3 (or the other suitable factor) times that of transistor 97 A. The gates of transistors 96 A and 97 A are connected to receive V in− , and the gates of transistors 96 B and 97 B are connected to receive V in+ . The drains of “ 3 x ” transistor 96 A and “ 1 x ” transistor 97 A are connected to one input of “folded cascode and output driver” circuit 98 , and drains of “ 1 x ”transistor 96 B and “ 3 x ” transistor 97 B are connected to another input of folded cascode and output driver circuit 98 , the output of which is a differential or single-ended output voltage V out1 . Transistors 96 A, 96 B, 97 A and 97 B are included in feed-forward amplifier 65 of FIG. 1A, as indicated by dashed lines 65 in FIG. 5 . The output driver circuit in block 98 corresponds to output stage 59 in FIG. 1 A. Transistors 96 A, 96 B, 97 A, 97 B, 94 and 95 comprise the summing circuit 58 of FIG. 1 A.

Transistors 94 and 95 steer the constant tail current between the transistor pair 96 A,B and the transistor pair 97 A,B in accordance with the magnitude and polarity of V in . Because of the 3-to-1 imbalance in the size of transistor 96 A relative to transistor 96 B and the 3-to-1 imbalance in the size of transistor 97 B relative to transistor 97 A, the effective “input offset voltage” between the transistor pair 97 A,B and the transistor pair 96 A,B is adjusted in accordance with how much current is steered through each pair. This effect of V in as amplified by nulling amplifiers 52 and 60 is selectively combined with or added to the effect of V in being applied between the gates of transistors 96 A and 97 A and transistors 96 B and 97 B as shown in FIG. 5 . The resulting current flowing into the two inputs of the conventional folded cascode circuitry included in block 98 results in a value of V out1 that is effectively compensated for the input offset voltages of nulling amplifiers 52 and 60 and for the offset voltages of the input transistors 96 A and 96 B and the input transistors 97 A and 97 B.

The above described preferred embodiment of invention allows the ratio of the gm of the pair of transistors 3 and 16 to the gm of the nulling pair of transistors 18 and 19 to be increased from the previously accepted upper limit of 10 to the value of 23 without increasing the integrated circuit chip quiescent current consumption, and therefore allows a substantial reduction of the input-referred noise without substantially increasing the integrated circuit quiescent current consumption or the offset voltage of the entire auto-zeroed amplifier.

Each of nulling amplifiers has its own residual offset voltage, given by Equation 2. If the residual offset voltages of nulling amplifiers 52 and 60 are different, then the outputs of nulling amplifiers 52 and 60 will settle to 2 different voltages as switches 56 and 63 are operated to alternately connect and disconnect nulling amplifiers 52 and 60 to conductor 57 in FIG. 1 A. This causes a ripple voltage component to propagate to the output V out1 . The gain boost technique provided by the present invention causes the residual offset voltages of nulling amplifiers 52 and 60 to be reduced, and thereby also reduces the foregoing ripple voltage component in V out1 .

Those skilled in the art will understand that the input-referred noise can be optimized by changing the circuit speed of the nulling loop relative to the speed of the clock signal, and that the noise can be lowered by running the clock signal faster and/or by reducing the bandwidth of the nulling loop. An advantage of the gain boost provided according to the present invention is that it allows charge injection errors, for example at switches 69 A and 69 B, to be smaller when they are referred back to the input. That allows a higher clock frequency to be used without introducing substantial offset voltage degradation.

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all elements or steps which are insubstantially different or perform substantially the same function in substantially the same way to achieve the same result as what is claimed are within the scope of the invention:

For example, the nulling circuit 52 A can be utilized in an auto-zeroed amplifier that includes only a single nulling amplifier. In this case, feed-forward amplifier 65 is essential. In some cases, the feed-forward amplifier 65 may be omitted from the configuration of FIG. 1A wherein two nulling amplifiers are utilized. In some cases, nulling amplifier 52 A might have only high side gain boost amplifier 117 or only low side gain boost amplifier 113 , depending on whether “high side” or “low side” circuitry is causing the impedance at conductors 57 A and 57 B to be too low.