USPatent applicationPatented

High-speed laser driver including wave-shaping circuits

Granted 28 Sep 2004 · no office action yet

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Abstract

A high-speed laser driver for signal noise on the electrical analysis point. The driver includes a power supply, for providing a test voltage in the system; a pulse generator, for providing a test frequency in a noise testing of the system; a regulable test IC with different signal pads capable of regulable testing signal noise with the test frequency from the pulse generator and the test voltage from the power supply in a plurality of built-in specific structures, under the basis of an assigned current standard; and a digital detection device with a display, for displaying and recording the result of the regulable test.

Description

6 parts
›Pursuant to 35 U.S.C. §119(a)-(d), this application claims…

Pursuant to 35 U.S.C. §119(a)-(d), this application claims priority from Taiwanese application no. 91104506, filed on Mar. 11, 2002.

›BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a laser driver, and especially to a high-speed laser driver including wave shaping and dynamic control circuits, which uses a source degeneration resistor instead of a prior constant current source to increase the operating speed, a buffer with a dynamic loading source resistor to buffer the output differential signals to the next circuit, and a tunable device to control output gain and prevent overshoot.

2. Description of Related Art

FIG. 1 is a block diagram of a typical laser driver 10 . As shown in FIG. 1, the laser circuit 10 includes a wave-shaping circuit 11 to receive and shape signals Sdp and Sdn externally, an output control circuit 12 to adjust signals Sdp and Sdn to desired signals Swu and Swl, and an output stage circuit 13 to convert signals Swu and Swl into a desired output I for the laser diode 14 by externally inputting the signal CG to set the desired modulation current. As such, the laser circuit 10 drives the modulation current Im of a laser diode 14 . When the laser diode 14 functions, the required bias voltage is provided by a bias current source 15 . However, for high-speed and broadband (NRZ signal) requirements of laser drivers, such a conversional MOS constant current source differential pair structure cannot meet the design specification because the speed limitation comes from the parasitic capacitance and some physical behavior of MOS devices. Thus, the laser drive with the conversional structure has poor performance. For example, FIG. 2 is an example of the wave-shaping circuit 11 of FIG. 1 . As shown in FIG. 2, the wave-shaping circuit 11 has constant current source differential pairs. These constant current source differential pairs serve as gain stages and limit the output swing to a desired level. For simplification, only the last differential stage 111 consisting of resistors R 1 , R 2 , MOSs M 1 , M 2 , and a constant current source CS 1 is shown. Further, circuit 112 serves as an output stage to drive the next circuit and adjusts the output voltage level to a desired swing. A wave-shaping circuit like 11 can convert a differential sine wave pair Sdp, Sdn into a differential square wave pair Swu, Swl or a single-end signal into a differential pair (not shown). However, as mentioned above, the operating speed of a constant current source differential pair is limited by the non-ideal characteristics and of MOS current source. Thus, as shown in FIG. 3, a parasitic capacitance Cp is formed due to the junction voltage difference Vd−Vb between the drain D and bulk B of the MOS, for example M 1 (FIG. 2) when an external current Iext is input to the drain D of M 1 . The parasitic capacitance Cp causes the current source CS 1 , CS 2 and CS 3 in FIG. 2 to be non-ideal current sources such that the operating speed of the differential pair M 1 , M 2 is limited. When operating at high speed, the total current of NMOSs M 1 and M 2 is equal to the current of CS 1 in ideal. However, the parasitic capacitance Cp in the non-ideal constant current sources can cause signal distortion. For example, when a 0.35 μm CMOS manufacturing process is used to shape a 1.25G clock pulse, as shown in FIG. 4, the signal such as Swu may change the waveform from V 1 to V 2 and cause a signal distortion. If the signals Swu, Swl are unchanged, and sent to the next output control circuit 12 , as shown in FIG. 5, the circuit 12 also includes MOSs M 51 - 53 , causing output signal distortion. That is, the MOS M 53 becomes a non-ideal constant current source and the signals Sout 1 , Sout 2 sent to the next output stage circuit 13 (FIG. 1) change the waveform from V 1 to V 2 (FIG. 4) so as to cause output signal distortion. Likewise, the waveform distortion may present in the output stage circuit 13 consisting of, for example, a resistor R 53 , MOSs M 54 -M 56 as mentioned above.

›SUMMARY OF THE INVENTION

Accordingly, an object of the invention is to provide a high-speed laser driver including a wave-shaping circuit, which performs wave shaping for the laser driver at high speeds.

Another object of the invention is to provide a high-speed laser driver including wave-shaping and dynamic control circuits, which performs the wave shaping and the dynamic control for the laser driver at high speed.

The invention provides a high-speed laser driver including wave-shaping circuits, which performs wave shaping for driving the laser at high speed. The laser driver includes a wave-shaping circuit having a source degeneration resistor instead of a prior constant current source to increase the operating speed and a buffer with a dynamic loading source resistor to buffer the output differential signals to the next circuit. The laser driver further includes a dynamic control circuit having a tunable device to control output gain and prevent overshoot.

›BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a typical laser driver;

FIG. 2 is a diagram of the typical wave-shaping circuit of FIG. 1;

FIG. 3 is a diagram illustrating the feature of a non-ideal MOS used as a constant current source of FIG. 2;

FIG. 4 is a comparison diagram of the ideal to non-ideal wave shaping output signals of FIG. 2;

FIG. 5 is a diagram of typical output control and output stage circuits of FIG. 1;

FIG. 6 shows a circuit diagram of a high-speed laser driver according to the invention;

FIG. 7 is an enlarged view of the wave-shaping circuit of FIG. 6 according to the invention;

FIG. 8 is an enlarged view of the dynamic control circuit and the output stage circuit of FIG. 6 according to the invention;

FIG. 9 is an example of the level shift circuit of FIG. 6 according to the invention; and

FIG. 10 is a comparison diagram of the output waveforms of the prior and invention.

›DETAILED DESCRIPTION OF THE INVENTION · 1 of 2

FIG. 6 shows a circuit diagram of a high-speed laser driver according to the invention. In FIG. 6, the high-speed laser driver includes: a wave-shaping circuit 61 , a dynamic control circuit 631 , an output stage circuit 632 and a level shift circuit 633 . As shown in FIG. 6, for simplification, only a wave-shaping circuit 61 is shown. In practice, multiple cascade wave-shaping circuits are generally used to achieve a desired wave shaping output for driving the next output stage. More detailed description is shown in FIGS. 7-9. FIG. 7 is an enlarged view of the wave shaping 61 . FIG. 8 is an enlarged view of the dynamic control circuit 631 and the output stage circuit 632 . FIG. 9 is an embodiment of the level shift circuit 633 .

As shown in FIG. 7, the wave-shaping circuit 61 includes a shaping stage and a buffering stage. The shaping stage is formed by resistors R 61 -R 63 and an NMOS differential pair M 61 , M 62 . The buffering stage is formed by two NMOS differential pairs M 63 -M 66 . The differential pair M 61 , M 62 determine the total current on the resistor R 63 . When an input signal swing to the differential pair M 61 , M 62 is too small, the differential pair M 61 , M 62 are both turned on to amplify the input signal swing. On the other hand, when the input signal swing to the differential pair M 61 , M 62 is too large, one of the differential pair M 61 , M 62 is turned on and the other is fully turned off, so as to reduce the input signal swing. Such a shaping stage can work at high speed without use of the non-ideal constant current source and thereby avoiding the distortion. In addition, the buffering stage follows the shaping stage as an output buffer to meet the requirement as multiple shaping stages are connected in series and further provide desired high speed operation without distortion. The devices M 65 , M 66 serve as dynamic loading source resistor. The devices M 65 , M 66 work either in saturation region or in triode region to respectively determine the current on device M 63 and M 64 . The equation: output stage voltage level (V)=current (I) X resistance (R) can determine a desired output voltage level by adjusting the values of a resistor and the current flowing on the resistor. Therefore, for a low voltage level, the device M 65 or M 66 changes to work in triode region for a lower resistance. On the other hand, for a high voltage level, the device M 65 or M 66 changes to work in saturation region for a higher resistance. As such, this dynamic loading buffer improves the speed performance and the driving power compared to the prior art. In practice, because the input signal may be very small, multiple wave-shaping circuits like the device 61 cascade are necessary so that a sine wave input signal can be converted into a desired square wave output signal (see signals Swu, Swl of FIG. 1 ). The devices M 65 and M 66 can be a tunable resistor.

As shown in FIG. 8, the dynamic control circuit 631 , the output stage circuit 632 and the level shift circuit 633 form an output stage 63 . The circuit 631 is formed by resistors R 64 -R 66 and NMOSs M 67 -M 69 . The circuit 632 is formed by NMOSs M 611 -M 613 . A resistor R 67 and a laser diode LD can be the external circuits. The resistor R 67 is optional. The laser diode 14 acts as a signal output device of this driver. In the circuit 631 , the device M 69 serves as a tunable resistor and operates in triode region. In the circuit 632 , the device 613 is controlled by the control voltage Vset and operated in saturation region acting as a driving source of the output current Iout. Due to the different operating region, the gate voltage of M 69 is higher than that of M 613 . For a larger current in M 613 , the voltage Vset to the gate of M 613 is set higher. In addition, the gate voltage of M 69 must be higher for a suitable value to create larger output swings of R 64 and R 65 to the stage 632 through output terminal O 1 and O 2 to make sure M 611 or M 612 fully turned off to prevent overshoot. For a smaller current in M 613 , the voltage Vset to the gate of M 613 is set lower. Also, the gate voltage of M 69 must be lower for a suitable value to create smaller output swings of R 64 and R 65 to the stage 632 through output terminal O 1 and O 2 to make sure that M 611 or M 612 are fully turned off to prevent overshoot. The level shift circuit 633 can be any kind of level shift circuit meeting the requirement of operating with the circuits 631 and 632 . An example of the level shift circuit 633 is given in FIG. 9 and described in the following.

As shown in FIG. 9, the circuit 633 is formed by PMOSs M 614 , M 615 , an NMOS M 616 and a resistor R 68 . For a larger current in M 613 , the voltage Vset to the gate of M 613 is set higher so that the voltage to the gate of M 616 is higher. Thus, the falling voltage on R 68 is higher and the gate voltage of M 69 input through an output terminal A (FIGS. 8 and 9) is higher and suitable to create a higher falling voltage swing on R 64 and R 65 . The higher falling voltages on R 64 and R 65 are sent to the stage 632 through the output terminals O 1 and O 2 , respectively, to make sure the device M 611 or M 612 is fully turned off to prevent overshoot. For a smaller current in M 613 , the voltage Vset to the gate of M 613 is set lower so that the voltage to the gate of M 616 is smaller. Thus, the falling voltage on R 68 is smaller and the gate voltage of M 69 input through an output terminal A (FIGS. 8 and 9) is smaller and suitable to create a smaller falling voltage swing on R 64 and R 65 . The smaller falling voltages on R 64 and R 65 are sent to the stage 632 through the output terminals O 1 and O 2 , respectively, to make sure the device M 611 or M 612 is fully turned off to prevent overshoot.

FIG. 10 is a comparison of FIGS. 1 and 6. In FIG. 10, the solid line represents the invention and the dotted line represents the prior art. As shown in FIG. 10, the output waveform in the invention is the same square waveform (i.e., having platform portions on two ends of the output) as that of the input voltage and no overshoot. The output waveform in the prior art, however, has become a sine wave. By the comparison, the present invention can concurrently prevent overshoot issues and operate at high speed. Thus, during operation of the input voltage conversion between M 61 and M 62 or M 67 and M 68 , the resistor, instead of the constant current source in the wave-shaping circuit, can solve speed limitation from the non-ideal features of the constant current source and increase operating speed. Moreover, additional level shift circuit in combination with a tunable device, for example a tunable resistor or a MOS, adjusts the voltage output to the output stage to prevent overshoot issues without reducing the operating speed.

›DETAILED DESCRIPTION OF THE INVENTION · 2 of 2

Although the present invention has been described in its preferred embodiment, it is not intended to limit the invention to the precise embodiment disclosed herein. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this invention. Therefore, the scope of the present invention shall be defined and protected by the following claims and their equivalents.

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Classifications

8 codes
IPC · International Patent Classification
Section H — Electricity
  • H01S5/00
  • H01S5/062
  • H01S5/042
USPC · US Patent Classification
372/38.2372/38.7327/112372/38.4327/110

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⤢ drag to zoomJul 2002Oct 2002Jan 2003Apr 2003Jul 2003Oct 2003Jan 2004Apr 2004Jul 2004Oct 2004USPTOApplicantNotice of allowance
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840 days filing → grant
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Examiner
Don Wong
art unit 2828 · TC 2800
Citations: 10 back · 1 forward

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